Index: lib/Target/PowerPC/PPCCTRLoops.cpp
===================================================================
--- lib/Target/PowerPC/PPCCTRLoops.cpp
+++ lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -572,6 +572,12 @@
     if (SE->getTypeSizeInBits(EC->getType()) > (TM->isPPC64() ? 64 : 32))
       continue;
 
+    // If this exiting block is contained in a nested loop, it is not eligible
+    // for insertion of the branch-and-decrement since the inner loop would
+    // end up messing up the value in the CTR.
+    if (LI->getLoopFor(*I) != L)
+      continue;
+
     // We now have a loop-invariant count of loop iterations (which is not the
     // constant zero) for which we know that this loop will not exit via this
     // exisiting block.
Index: test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll
===================================================================
--- test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll
+++ test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+define hidden fastcc void @gen_bitlen() {
+; CHECK-LABEL: gen_bitlen:
+; CHECK-NOT: mtctr
+; CHECK-NOT: bdnz
+; CHECK-NOT: bdz
+; CHECK:     Lfunc_end0
+  br i1 undef, label %lab_1, label %lab_28
+
+lab_1:                                      ; preds = %0
+  br label %lab_2
+
+lab_2:                                      ; preds = %lab_7, %lab_1
+  br i1 undef, label %lab_7, label %lab_3
+
+lab_3:                                      ; preds = %lab_2
+  br i1 undef, label %lab_5, label %lab_4
+
+lab_4:                                      ; preds = %lab_3
+  br label %lab_5
+
+lab_5:                                      ; preds = %lab_4, %lab_3
+  br i1 undef, label %lab_7, label %lab_6
+
+lab_6:                                      ; preds = %lab_5
+  br label %lab_7
+
+lab_7:                                      ; preds = %lab_6, %lab_5, %lab_2
+  br i1 undef, label %lab_2, label %lab_8
+
+lab_8:                                      ; preds = %lab_7
+  br i1 undef, label %lab_28, label %lab_9
+
+lab_9:                                      ; preds = %lab_8
+  br label %lab_10
+
+lab_10:                                     ; preds = %lab_12, %lab_9
+  br label %lab_11
+
+lab_11:                                     ; preds = %lab_11, %lab_10
+  br i1 undef, label %lab_11, label %lab_12
+
+lab_12:                                     ; preds = %lab_11
+  br i1 undef, label %lab_10, label %lab_13
+
+lab_13:                                     ; preds = %lab_12
+  br i1 undef, label %lab_28, label %lab_14
+
+lab_14:                                     ; preds = %lab_13
+  br label %lab_15
+
+lab_15:                                     ; preds = %lab_27, %lab_14
+  br label %lab_16
+
+lab_16:                                     ; preds = %lab_25, %lab_15
+  %phi_17 = phi i32 [ %add_26, %lab_25 ], [ undef, %lab_15 ]
+  %icmp_18 = icmp eq i32 %phi_17, 0
+  br label %lab_19
+
+lab_19:                                     ; preds = %lab_20, %lab_16
+  br i1 %icmp_18, label %lab_27, label %lab_20
+
+lab_20:                                     ; preds = %lab_19
+  %ld_21 = load i32, i32* undef, align 4
+  %icmp_22 = icmp sgt i32 %ld_21, 0
+  br i1 %icmp_22, label %lab_19, label %lab_23
+
+lab_23:                                     ; preds = %lab_20
+  br i1 undef, label %lab_25, label %lab_24
+
+lab_24:                                     ; preds = %lab_23
+  br label %lab_25
+
+lab_25:                                     ; preds = %lab_24, %lab_23
+  %add_26 = add nsw i32 %phi_17, -1
+  br label %lab_16
+
+lab_27:                                     ; preds = %lab_19
+  br i1 undef, label %lab_28, label %lab_15
+
+lab_28:                                     ; preds = %lab_27, %lab_13, %lab_8, %0
+  ret void
+}