Index: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td @@ -934,22 +934,27 @@ let ParserMatchClass = ZPRVectorList<64, 4>; } -class ZPRExtendAsmOperand - : AsmOperandClass { - let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale; +class ZPRExtendAsmOperand : AsmOperandClass { + let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale + # !if(ScaleAlwaysSame, "Only", ""); + let PredicateMethod = "isSVEVectorRegWithShiftExtend<" # RegWidth # ", AArch64::ZPRRegClassID, " # "AArch64_AM::" # ShiftExtend # ", " - # Scale # ">"; + # Scale # ", " + # !if(ScaleAlwaysSame, "true", "false") + # ">"; let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale; let RenderMethod = "addRegOperands"; let ParserMethod = "tryParseSVEDataVector"; } class ZPRExtendRegisterOperand : RegisterOperand { + int RegWidth, int Scale, string Suffix = ""> + : RegisterOperand { let ParserMatchClass = - !cast("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale); + !cast("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix); let PrintMethod = "printRegWithShiftExtend<" # !if(SignExtend, "true", "false") # ", " # Scale # ", " @@ -959,22 +964,26 @@ foreach RegWidth = [32, 64] in { // UXTW(8|16|32|64) + def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>; def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>; def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>; def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>; def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>; + def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">; def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>; def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>; def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>; def ZPR#RegWidth#ExtUXTW64 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>; // SXTW(8|16|32|64) + def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>; def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>; def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>; def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>; def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>; + def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">; def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>; def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>; def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>; @@ -986,7 +995,6 @@ def ZPR64AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", 64, 16>; def ZPR64AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", 64, 32>; def ZPR64AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", 64, 64>; - def ZPR64ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 8>; def ZPR64ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 16>; def ZPR64ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 32>; Index: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -108,10 +108,10 @@ // Gathers using unscaled 32-bit offsets, e.g. // ld1h z0.s, p0/z, [x0, z0.s, uxtw] - defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; - defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; - defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; - defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; + defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; + defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; + defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; + defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; @@ -190,10 +190,10 @@ // Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g. // ld1h z0.d, p0/z, [x0, z0.d, uxtw] - defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; - defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; - defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; - defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; + defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; + defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; + defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; + defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -877,14 +877,25 @@ } template + AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth, + bool ShiftWidthAlwaysSame> DiagnosticPredicate isSVEVectorRegWithShiftExtend() const { if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) return DiagnosticPredicateTy::NoMatch; - if (isSVEVectorRegOfWidth() && - ShiftExtendTy == getShiftExtendType() && - getShiftExtendAmount() == Log2_32(ShiftWidth / 8)) + if (!isSVEVectorRegOfWidth()) + return DiagnosticPredicateTy::NearMatch; + + // Give a more specific diagnostic when the user has explicitly typed in + // a shift-amount that does not match what is expected, but for which + // there is also an unscaled addressing mode (e.g. sxtw/uxtw). + bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); + if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW || + ShiftExtendTy == AArch64_AM::SXTW) && + !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8) + return DiagnosticPredicateTy::NoMatch; + + if (MatchShift && ShiftExtendTy == getShiftExtendType()) return DiagnosticPredicateTy::Match; return DiagnosticPredicateTy::NearMatch; Index: llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -80,12 +80,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -120,22 +120,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -119,22 +119,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -104,12 +104,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -119,12 +119,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -105,22 +105,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, z0.s, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -59,12 +59,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s @@ -69,22 +69,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1h z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1h z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -63,22 +63,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -59,12 +59,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -74,12 +74,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -69,22 +69,22 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.s, p0/z, [x0, z0.s, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.s, p0/z, [x0, z0.s, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: