Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -203,20 +203,6 @@ let Inst{15-0} = offset; } -class SIGN_EXTEND_FM_MMR6 funct> - : MMR6Arch { - bits<5> rd; - bits<5> rt; - - bits<32> Inst; - - let Inst{31-26} = 0b000000; - let Inst{25-21} = rd; - let Inst{20-16} = rt; - let Inst{15-6} = funct; - let Inst{5-0} = 0b111100; -} - class PCREL19_FM_MMR6 funct> : MipsR6Inst { bits<5> rt; bits<19> imm; Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -136,8 +136,6 @@ class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>; -class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>; -class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>; class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>; class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>; @@ -529,8 +527,6 @@ class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>; -class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>; -class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>; class ALUIPC_MMR6_DESC_BASE : MMR6Arch { dag OutOperandList = (outs GPROpnd:$rt); @@ -1382,8 +1378,6 @@ def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6; def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6; -def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6; -def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6; def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, ISA_MICROMIPS32R6; def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, @@ -1660,10 +1654,6 @@ def : MipsInstAlias<"not $rt, $rs", (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MICROMIPS32R6; -def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, - ISA_MICROMIPS32R6; -def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, - ISA_MICROMIPS32R6; def : MipsInstAlias<"lapc $rd, $imm", (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MICROMIPS32R6; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -927,9 +927,9 @@ /// Sign Ext In Register Instructions. def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, - SEB_FM_MM<0x0ac>, ISA_MIPS32R2; + SEB_FM_MM<0x0ac>, ISA_MICROMIPS; def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, - SEB_FM_MM<0x0ec>, ISA_MIPS32R2; + SEB_FM_MM<0x0ec>, ISA_MICROMIPS; /// Word Swap Bytes Within Halfwords def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, @@ -1325,9 +1325,9 @@ (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, ISA_MICROMIPS; def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, - ISA_MIPS32R2_NOT_32R6_64R6; + ISA_MICROMIPS; def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, - ISA_MIPS32R2_NOT_32R6_64R6; + ISA_MICROMIPS; def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS; def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>, ISA_MICROMIPS; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -2285,13 +2285,13 @@ ISA_MIPS1_NOT_32R6_64R6; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, ISA_MIPS1_NOT_32R6_64R6; -} /// Sign Ext In Register Instructions. def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>, ISA_MIPS32R2; def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>, ISA_MIPS32R2; +} /// Count Leading def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, Index: llvm/trunk/test/MC/Mips/micromips/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/valid.s +++ llvm/trunk/test/MC/Mips/micromips/valid.s @@ -150,9 +150,13 @@ clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c] clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c] seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c] + # CHECK-NEXT: #