Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -948,45 +948,53 @@ J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>, IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6; -let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { +let DecoderNamespace = "MicroMips" in { let DecoderMethod = "DecodeJumpTargetMM" in { - def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>; - def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>; + def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>, + ISA_MICROMIPS32_NOT_MIPS32R6; } def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>, ISA_MICROMIPS32_NOT_MIPS32R6; - def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>; + def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>, + ISA_MICROMIPS32_NOT_MIPS32R6; /// Jump Instructions - Short Delay Slot - def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>; - def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>; + def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>, + ISA_MICROMIPS32_NOT_MIPS32R6; /// Branch Instructions def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>, - BEQ_FM_MM<0x25>; + BEQ_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6; def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>, - BEQ_FM_MM<0x2d>; + BEQ_FM_MM<0x2d>, ISA_MICROMIPS32_NOT_MIPS32R6; def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>, - BGEZ_FM_MM<0x2>; + BGEZ_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>, - BGEZ_FM_MM<0x6>; + BGEZ_FM_MM<0x6>, ISA_MICROMIPS32_NOT_MIPS32R6; def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>, - BGEZ_FM_MM<0x4>; + BGEZ_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6; def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>, - BGEZ_FM_MM<0x0>; + BGEZ_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6; def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>, - BGEZAL_FM_MM<0x03>; + BGEZAL_FM_MM<0x03>, ISA_MICROMIPS32_NOT_MIPS32R6; def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>, - BGEZAL_FM_MM<0x01>; + BGEZAL_FM_MM<0x01>, ISA_MICROMIPS32_NOT_MIPS32R6; + def BAL_BR_MM : BAL_BR_Pseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; /// Branch Instructions - Short Delay Slot def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, - GPR32Opnd>, BGEZAL_FM_MM<0x13>; + GPR32Opnd>, BGEZAL_FM_MM<0x13>, + ISA_MICROMIPS32_NOT_MIPS32R6; def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, - GPR32Opnd>, BGEZAL_FM_MM<0x11>; -} -def B_MM : UncondBranch, IsBranch, ISA_MICROMIPS; -let DecoderNamespace = "MicroMips" in { + GPR32Opnd>, BGEZAL_FM_MM<0x11>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def B_MM : UncondBranch, IsBranch, + ISA_MICROMIPS32_NOT_MIPS32R6; /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS; @@ -1213,7 +1221,7 @@ (LH_MM addr:$a)>; defm : BrcondPats; + SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6; defm : SeteqPats; defm : SetlePats; @@ -1323,6 +1331,8 @@ def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS; def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>, ISA_MICROMIPS; + def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>, + ISA_MICROMIPS32_NOT_MIPS32R6; } def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>, ISA_MICROMIPS32R5, ASE_VIRT; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1649,9 +1649,9 @@ PseudoInstExpansion<(JumpInst RO:$rs)>; } -class BAL_BR_Pseudo : - PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>, - PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { +class BAL_BR_Pseudo : + PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>, + PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; @@ -2146,54 +2146,61 @@ def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; } - /// Jump and Branch Instructions +let AdditionalPredicates = [NotInMicroMips, RelocNotPIC] in def J : MMRel, JumpFJ, FJ<2>, - AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch; + IsBranch, ISA_MIPS1; + +let AdditionalPredicates = [NotInMicroMips] in { def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; -def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; +def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>, + ISA_MIPS1; def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; -def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; +def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>, + ISA_MIPS1; def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>, BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, - BGEZ_FM<1, 1>; + BGEZ_FM<1, 1>, ISA_MIPS1; def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>, BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, - BGEZ_FM<7, 0>; + BGEZ_FM<7, 0>, ISA_MIPS1; def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>, BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, - BGEZ_FM<6, 0>; + BGEZ_FM<6, 0>, ISA_MIPS1; def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>, BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, - BGEZ_FM<1, 0>; + BGEZ_FM<1, 0>, ISA_MIPS1; def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>, BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; -def B : UncondBranch, - AdditionalRequires<[NotInMicroMips]>; +def B : UncondBranch, ISA_MIPS1; + +def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1; -def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; -let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in { - def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; - def JALRPseudo : JumpLinkRegPseudo; } -def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, - ISA_MIPS32_NOT_32R6_64R6; -def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, - ISA_MIPS1_NOT_32R6_64R6; -def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>, - BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; -def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, - ISA_MIPS1_NOT_32R6_64R6; -def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, - BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; -def BAL_BR : BAL_BR_Pseudo; +let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in { + def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1; + def JALRPseudo : JumpLinkRegPseudo, ISA_MIPS1; +} +let AdditionalPredicates = [NotInMicroMips] in { + def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, + ISA_MIPS32_NOT_32R6_64R6; + def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, + ISA_MIPS1_NOT_32R6_64R6; + def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>, + BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; + def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, + ISA_MIPS1_NOT_32R6_64R6; + def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, + BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; + def BAL_BR : BAL_BR_Pseudo; +} let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in { def TAILCALL : TailCall; } Index: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp +++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp @@ -285,7 +285,7 @@ const unsigned BalOp = Subtarget.hasMips32r6() ? Subtarget.inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC - : Mips::BAL_BR; + : Subtarget.inMicroMipsMode() ? Mips::BAL_BR_MM : Mips::BAL_BR; if (!ABI.IsN64()) { // Pre R6: Index: llvm/trunk/test/CodeGen/Mips/br-jmp.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/br-jmp.ll +++ llvm/trunk/test/CodeGen/Mips/br-jmp.ll @@ -5,7 +5,7 @@ ; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMM ; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMM ; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMMR6 -; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMMR6 @@ -22,5 +22,6 @@ ; STATIC: j $BB0_1 #