Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -793,21 +793,22 @@
 
   /// Load and Store Instructions - aligned
   let DecoderMethod = "DecodeMemMMImm16" in {
-    def LB_MM  : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>,
-                 MMRel, LW_FM_MM<0x7>;
-    def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>,
-                 MMRel, LW_FM_MM<0x5>;
+    def LB_MM  : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
+                 MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
+    def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,
+                 MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;
     def LH_MM  : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
-                            addrDefault>, MMRel, LW_FM_MM<0xf>;
+                            addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;
     def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
-                 MMRel, LW_FM_MM<0xd>;
-    def LW_MM  : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>;
-    def SB_MM  : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel,
-                 LW_FM_MM<0x6>;
-    def SH_MM  : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel,
-                 LW_FM_MM<0xe>;
+                 MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;
+    def LW_MM  : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,
+                 ISA_MICROMIPS;
+    def SB_MM  : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
+                 LW_FM_MM<0x6>, ISA_MICROMIPS;
+    def SH_MM  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,
+                 LW_FM_MM<0xe>, ISA_MICROMIPS;
     def SW_MM  : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
-                 LW_FM_MM<0x3e>;
+                 LW_FM_MM<0x3e>, ISA_MICROMIPS;
   }
 }
 let DecoderNamespace = "MicroMips" in {
@@ -1185,6 +1186,19 @@
                 (LW_MM addr:$addr)>;
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
                 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
+
+  def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu_MM addr:$src)>,
+        ISA_MICROMIPS;
+
+  def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu_MM addr:$src)>,
+        ISA_MICROMIPS;
+
+  def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
+        ISA_MICROMIPS;
+
+  let AddedComplexity = 40 in
+    def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
+                  (LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
 }
 
 def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
@@ -1195,14 +1209,8 @@
 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
               (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
-let AddedComplexity = 40 in {
-  def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
-                (LH_MM addrRegImm:$a)>;
-}
 def : MipsPat<(atomic_load_16 addr:$a),
               (LH_MM addr:$a)>;
-def : MipsPat<(i32 (extloadi16 addr:$src)),
-              (LHu_MM addr:$src)>;
 
 defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
                   SLTiu_MM, ZERO>;
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -2037,23 +2037,21 @@
 
 /// Load and Store Instructions
 ///  aligned
-def LB  : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,
-          LW_FM<0x20>;
-def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,
-                     addrDefault>, MMRel, LW_FM<0x24>;
 let AdditionalPredicates = [NotInMicroMips] in {
+  def LB  : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,
+            LW_FM<0x20>;
+  def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,
+                       addrDefault>, MMRel, LW_FM<0x24>;
   def LH  : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
                        addrDefault>, MMRel, LW_FM<0x21>;
   def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
             MMRel, LW_FM<0x25>;
   def LW  : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
             LW_FM<0x23>;
-}
-def SB  : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
-          LW_FM<0x28>;
-def SH  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
-let AdditionalPredicates = [NotInMicroMips] in {
-def SW  : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
+  def SB  : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
+            LW_FM<0x28>;
+  def SH  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
+  def SW  : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
 }
 
 /// load/store left/right
@@ -3021,9 +3019,9 @@
 }
 
 // extended loads
-def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
-def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
 let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
+  def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
   def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
 }
 
@@ -3126,10 +3124,12 @@
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
-  def : LoadRegImmPat<LBu, i32, zextloadi8>;
   let AdditionalPredicates = [NotInMicroMips] in {
-    def : LoadRegImmPat<LH, i32, sextloadi16>;
-    def : LoadRegImmPat<LW, i32, load>;
+    def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1;
+    def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1;
+    def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1;
+    def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1;
+    def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1;
   }
 }
 
Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll
@@ -0,0 +1,1022 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
+; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
+; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3
+; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
+
+; Test subword and word loads.
+
+@a = common global i8 0, align 4
+@b = common global i16 0, align 4
+@c = common global i32 0, align 4
+@d = common global i64 0, align 8
+
+define i8 @f1() {
+; MIPS32-LABEL: f1:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR3-LABEL: f1:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R6-LABEL: f1:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR6-LABEL: f1:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f1:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS3-NEXT:    # <MCOperand Reg:321>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS64-LABEL: f1:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS64-NEXT:    # <MCOperand Reg:321>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS64R6-LABEL: f1:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS64R6-NEXT:    # <MCOperand Reg:321>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+entry:
+  %0 = load i8, i8 * @a
+  ret i8 %0
+}
+
+define i32 @f2() {
+; MIPS32-LABEL: f2:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR3-LABEL: f2:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R6-LABEL: f2:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR6-LABEL: f2:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f2:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS3-NEXT:    # <MCOperand Reg:321>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS64-LABEL: f2:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS64-NEXT:    # <MCOperand Reg:321>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS64R6-LABEL: f2:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS64R6-NEXT:    # <MCOperand Reg:321>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+entry:
+  %0 = load i8, i8 * @a
+  %1 = sext i8 %0 to i32
+  ret i32 %1
+}
+
+define i16 @f3() {
+; MIPS32-LABEL: f3:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR3-LABEL: f3:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R6-LABEL: f3:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR6-LABEL: f3:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f3:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS3-NEXT:    # <MCOperand Reg:321>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS64-LABEL: f3:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS64-NEXT:    # <MCOperand Reg:321>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS64R6-LABEL: f3:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS64R6-NEXT:    # <MCOperand Reg:321>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+entry:
+  %0 = load i16, i16 * @b
+  ret i16 %0
+}
+
+define i32 @f4() {
+; MIPS32-LABEL: f4:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR3-LABEL: f4:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R6-LABEL: f4:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR6-LABEL: f4:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f4:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS3-NEXT:    # <MCOperand Reg:321>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS64-LABEL: f4:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS64-NEXT:    # <MCOperand Reg:321>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS64R6-LABEL: f4:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS64R6-NEXT:    # <MCOperand Reg:321>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+entry:
+  %0 = load i16, i16 * @b
+  %1 = sext i16 %0 to i32
+  ret i32 %1
+}
+
+define i32 @f5() {
+; MIPS32-LABEL: f5:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR3-LABEL: f5:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R6-LABEL: f5:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR6-LABEL: f5:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f5:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS3-NEXT:    # <MCOperand Reg:321>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64-LABEL: f5:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS64-NEXT:    # <MCOperand Reg:321>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64R6-LABEL: f5:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS64R6-NEXT:    # <MCOperand Reg:321>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+entry:
+  %0 = load i32, i32 * @c
+  ret i32 %0
+}
+
+define i64 @f6() {
+; MIPS32-LABEL: f6:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32-NEXT:    # <MCOperand Reg:322>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:21>
+; MIPS32-NEXT:    # <MCOperand Imm:0>>
+;
+; MMR3-LABEL: f6:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR3-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Imm:0>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR3-NEXT:    # <MCOperand Reg:322>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R6-LABEL: f6:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R6-NEXT:    # <MCOperand Reg:322>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Imm:0>>
+;
+; MMR6-LABEL: f6:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR6-NEXT:    # <MCOperand Reg:322>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR6-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Imm:0>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f6:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
+; MIPS3-NEXT:    # <MCOperand Reg:416>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64-LABEL: f6:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
+; MIPS64-NEXT:    # <MCOperand Reg:416>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64R6-LABEL: f6:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+entry:
+  %0 = load i32, i32 * @c
+  %1 = zext i32 %0 to i64
+  ret i64 %1
+}
+
+define i64 @f7() {
+; MIPS32-LABEL: f7:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32-NEXT:    # <MCOperand Reg:322>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
+; MIPS32-NEXT:    # <MCOperand Reg:321>
+; MIPS32-NEXT:    # <MCOperand Reg:322>
+; MIPS32-NEXT:    # <MCOperand Imm:31>>
+;
+; MMR3-LABEL: f7:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR3-NEXT:    # <MCOperand Reg:322>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:322>
+; MMR3-NEXT:    # <MCOperand Imm:31>>
+;
+; MIPS32R6-LABEL: f7:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R6-NEXT:    # <MCOperand Reg:322>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
+; MIPS32R6-NEXT:    # <MCOperand Reg:321>
+; MIPS32R6-NEXT:    # <MCOperand Reg:322>
+; MIPS32R6-NEXT:    # <MCOperand Imm:31>>
+;
+; MMR6-LABEL: f7:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR6-NEXT:    # <MCOperand Reg:322>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:322>
+; MMR6-NEXT:    # <MCOperand Imm:31>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS3-LABEL: f7:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:301>>
+; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
+; MIPS3-NEXT:    # <MCOperand Reg:416>
+; MIPS3-NEXT:    # <MCOperand Reg:30>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64-LABEL: f7:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:301>>
+; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
+; MIPS64-NEXT:    # <MCOperand Reg:416>
+; MIPS64-NEXT:    # <MCOperand Reg:30>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64R6-LABEL: f7:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+entry:
+  %0 = load i32, i32 * @c
+  %1 = sext i32 %0 to i64
+  ret i64 %1
+}
Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll
@@ -0,0 +1,494 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
+; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
+; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
+; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
+
+; Test subword and word stores.
+
+@a = common global i8 0, align 4
+@b = common global i16 0, align 4
+@c = common global i32 0, align 4
+@d = common global i64 0, align 8
+
+define void @f1(i8 %a) {
+; MIPS32-LABEL: f1:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
+; MIPS32-NEXT:    # <MCOperand Reg:22>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR3-LABEL: f1:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
+; MMR3-NEXT:    # <MCOperand Reg:22>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R6-LABEL: f1:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
+; MIPS32R6-NEXT:    # <MCOperand Reg:22>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR6-LABEL: f1:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
+; MMR6-NEXT:    # <MCOperand Reg:22>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS4-LABEL: f1:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS4-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
+; MIPS4-NEXT:    # <MCOperand Reg:356>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS64R6-LABEL: f1:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
+; MIPS64R6-NEXT:    # <MCOperand Reg:356>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+  store i8 %a, i8 * @a
+  ret void
+}
+
+define void @f2(i16 %a) {
+; MIPS32-LABEL: f2:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
+; MIPS32-NEXT:    # <MCOperand Reg:22>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR3-LABEL: f2:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
+; MMR3-NEXT:    # <MCOperand Reg:22>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R6-LABEL: f2:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
+; MIPS32R6-NEXT:    # <MCOperand Reg:22>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR6-LABEL: f2:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
+; MMR6-NEXT:    # <MCOperand Reg:22>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS4-LABEL: f2:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS4-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
+; MIPS4-NEXT:    # <MCOperand Reg:356>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS64R6-LABEL: f2:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
+; MIPS64R6-NEXT:    # <MCOperand Reg:356>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+  store i16 %a, i16 * @b
+  ret void
+}
+
+define void @f3(i32 %a) {
+; MIPS32-LABEL: f3:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32-NEXT:    # <MCOperand Reg:22>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR3-LABEL: f3:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR3-NEXT:    # <MCOperand Reg:22>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R6-LABEL: f3:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R6-NEXT:    # <MCOperand Reg:22>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR6-LABEL: f3:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR6-NEXT:    # <MCOperand Reg:22>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS4-LABEL: f3:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
+; MIPS4-NEXT:    # <MCOperand Reg:1>
+; MIPS4-NEXT:    # <MCOperand Reg:22>
+; MIPS4-NEXT:    # <MCOperand Imm:0>>
+; MIPS4-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS4-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
+; MIPS4-NEXT:    # <MCOperand Reg:1>
+; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS64R6-LABEL: f3:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:1>
+; MIPS64R6-NEXT:    # <MCOperand Reg:22>
+; MIPS64R6-NEXT:    # <MCOperand Imm:0>>
+; MIPS64R6-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
+; MIPS64R6-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
+; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
+; MIPS64R6-NEXT:    # <MCOperand Reg:1>
+; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+  store i32 %a, i32 * @c
+  ret void
+}
+
+define void @f4(i64 %a) {
+; MIPS32-LABEL: f4:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MIPS32-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32-NEXT:    # <MCOperand Reg:22>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32-NEXT:    # <MCOperand Reg:23>
+; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Imm:4>>
+;
+; MMR3-LABEL: f4:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MMR3-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR3-NEXT:    # <MCOperand Reg:22>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR3-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
+; MMR3-NEXT:    # <MCOperand Reg:23>
+; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Imm:4>>
+; MMR3-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR3-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS32R6-LABEL: f4:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MIPS32R6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R6-NEXT:    # <MCOperand Reg:22>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32R6-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:21>
+; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R6-NEXT:    # <MCOperand Reg:23>
+; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Imm:4>>
+;
+; MMR6-LABEL: f4:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MMR6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR6-NEXT:    # <MCOperand Reg:22>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR6-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
+; MMR6-NEXT:    # <MCOperand Reg:23>
+; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Imm:4>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:19>>
+;
+; MIPS4-LABEL: f4:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(d))>>
+; MIPS4-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(d))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
+; MIPS4-NEXT:    # <MCOperand Reg:356>
+; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(d))>>
+;
+; MIPS64R6-LABEL: f4:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(d))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(d))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:355>
+; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
+; MIPS64R6-NEXT:    # <MCOperand Reg:356>
+; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+  store i64 %a, i64 * @d
+  ret void
+}
Index: llvm/trunk/test/MC/Mips/micromips/invalid.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s
@@ -121,10 +121,10 @@
   xori $3, 65536      # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   not $3, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   lb $32, 8($5)       # CHECK: :[[@LINE]]:6: error: invalid register number
-  lb $4, -2147483649($5)  # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
-  lb $4, 2147483648($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
+  lb $4, -2147483649($5)  # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+  lb $4, 2147483648($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
   lb $4, 8($32)       # CHECK: :[[@LINE]]:12: error: invalid register number
   lbu $32, 8($5)      # CHECK: :[[@LINE]]:7: error: invalid register number
-  lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
-  lbu $4, 2147483648($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
+  lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+  lbu $4, 2147483648($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
   lbu $4, 8($32)      # CHECK: :[[@LINE]]:13: error: invalid register number
Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
@@ -253,12 +253,12 @@
   xori $3, 65536           # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   not $3, 4                # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   lb $32, 8($5)            # CHECK: :[[@LINE]]:6: error: invalid register number
-  lb $4, -2147483649($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
-  lb $4, 2147483648($5)    # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
+  lb $4, -2147483649($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+  lb $4, 2147483648($5)    # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
   lb $4, 8($32)            # CHECK: :[[@LINE]]:12: error: invalid register number
   lbu $32, 8($5)           # CHECK: :[[@LINE]]:7: error: invalid register number
-  lbu $4, -2147483649($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
-  lbu $4, 2147483648($5)   # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
+  lbu $4, -2147483649($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+  lbu $4, 2147483648($5)   # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
   lbu $4, 8($32)           # CHECK: :[[@LINE]]:13: error: invalid register number
   ldc1 $f32, 300($10)      # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
   ldc1 $f7, -32769($10)    # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset