Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -793,21 +793,22 @@ /// Load and Store Instructions - aligned let DecoderMethod = "DecodeMemMMImm16" in { - def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>, - MMRel, LW_FM_MM<0x7>; - def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>, - MMRel, LW_FM_MM<0x5>; + def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>, + MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS; + def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>, + MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS; def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, - addrDefault>, MMRel, LW_FM_MM<0xf>; + addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS; def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, - MMRel, LW_FM_MM<0xd>; - def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>; - def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel, - LW_FM_MM<0x6>; - def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel, - LW_FM_MM<0xe>; + MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS; + def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>, + ISA_MICROMIPS; + def SB_MM : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, + LW_FM_MM<0x6>, ISA_MICROMIPS; + def SH_MM : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, + LW_FM_MM<0xe>, ISA_MICROMIPS; def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel, - LW_FM_MM<0x3e>; + LW_FM_MM<0x3e>, ISA_MICROMIPS; } } let DecoderNamespace = "MicroMips" in { @@ -1185,6 +1186,19 @@ (LW_MM addr:$addr)>; def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; + + def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>, + ISA_MICROMIPS; + + def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>, + ISA_MICROMIPS; + + def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>, + ISA_MICROMIPS; + + let AddedComplexity = 40 in + def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)), + (LH_MM addrRegImm:$a)>, ISA_MICROMIPS; } def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>, @@ -1195,14 +1209,8 @@ def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; -let AddedComplexity = 40 in { - def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)), - (LH_MM addrRegImm:$a)>; -} def : MipsPat<(atomic_load_16 addr:$a), (LH_MM addr:$a)>; -def : MipsPat<(i32 (extloadi16 addr:$src)), - (LHu_MM addr:$src)>; defm : BrcondPats; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -2037,23 +2037,21 @@ /// Load and Store Instructions /// aligned -def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel, - LW_FM<0x20>; -def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, - addrDefault>, MMRel, LW_FM<0x24>; let AdditionalPredicates = [NotInMicroMips] in { + def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel, + LW_FM<0x20>; + def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, + addrDefault>, MMRel, LW_FM<0x24>; def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM<0x21>; def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, LW_FM<0x23>; -} -def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, - LW_FM<0x28>; -def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; -let AdditionalPredicates = [NotInMicroMips] in { -def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; + def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, + LW_FM<0x28>; + def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; + def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; } /// load/store left/right @@ -3021,9 +3019,9 @@ } // extended loads -def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; -def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; + def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; } @@ -3126,10 +3124,12 @@ // Load halfword/word patterns. let AddedComplexity = 40 in { - def : LoadRegImmPat; let AdditionalPredicates = [NotInMicroMips] in { - def : LoadRegImmPat; - def : LoadRegImmPat; + def : LoadRegImmPat, ISA_MIPS1; + def : LoadRegImmPat, ISA_MIPS1; + def : LoadRegImmPat, ISA_MIPS1; + def : LoadRegImmPat, ISA_MIPS1; + def : LoadRegImmPat, ISA_MIPS1; } } Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/load.ll @@ -0,0 +1,1022 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3 +; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6 +; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3 +; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64 +; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6 + +; Test subword and word loads. + +@a = common global i8 0, align 4 +@b = common global i16 0, align 4 +@c = common global i32 0, align 4 +@d = common global i64 0, align 8 + +define i8 @f1() { +; MIPS32-LABEL: f1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(a) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: lbu $2, %lo(a)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(a) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lbu $2, %lo(a)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(a) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(a) # +; MMR6-NEXT: # > +; MMR6-NEXT: lbu $2, %lo(a)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(a) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(a) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(a) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lbu $2, %lo(a)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(a) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(a) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(a) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lbu $2, %lo(a)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(a) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i8, i8 * @a + ret i8 %0 +} + +define i32 @f2() { +; MIPS32-LABEL: f2: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(a) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: lb $2, %lo(a)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f2: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(a) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lb $2, %lo(a)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f2: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(a) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lb $2, %lo(a)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f2: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(a) # +; MMR6-NEXT: # > +; MMR6-NEXT: lb $2, %lo(a)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f2: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(a) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(a) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(a) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lb $2, %lo(a)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f2: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(a) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(a) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(a) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lb $2, %lo(a)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f2: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(a) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lb $2, %lo(a)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i8, i8 * @a + %1 = sext i8 %0 to i32 + ret i32 %1 +} + +define i16 @f3() { +; MIPS32-LABEL: f3: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(b) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: lhu $2, %lo(b)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f3: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(b) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lhu $2, %lo(b)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f3: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(b) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f3: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(b) # +; MMR6-NEXT: # > +; MMR6-NEXT: lhu $2, %lo(b)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f3: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(b) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(b) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(b) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lhu $2, %lo(b)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f3: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(b) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(b) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(b) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lhu $2, %lo(b)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f3: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(b) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i16, i16 * @b + ret i16 %0 +} + +define i32 @f4() { +; MIPS32-LABEL: f4: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(b) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: lh $2, %lo(b)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f4: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(b) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lh $2, %lo(b)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(b) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lh $2, %lo(b)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f4: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(b) # +; MMR6-NEXT: # > +; MMR6-NEXT: lh $2, %lo(b)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f4: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(b) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(b) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(b) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lh $2, %lo(b)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(b) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(b) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(b) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lh $2, %lo(b)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(b) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lh $2, %lo(b)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i16, i16 * @b + %1 = sext i16 %0 to i32 + ret i32 %1 +} + +define i32 @f5() { +; MIPS32-LABEL: f5: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(c) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: lw $2, %lo(c)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f5: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(c) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lw $2, %lo(c)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f5: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(c) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lw $2, %lo(c)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f5: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(c) # +; MMR6-NEXT: # > +; MMR6-NEXT: lw $2, %lo(c)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f5: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(c) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lw $2, %lo(c)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f5: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(c) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lw $2, %lo(c)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f5: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(c) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lw $2, %lo(c)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i32, i32 * @c + ret i32 %0 +} + +define i64 @f6() { +; MIPS32-LABEL: f6: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(c) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: lw $3, %lo(c)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: addiu $2, $zero, 0 # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f6: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(c) # +; MMR3-NEXT: # > +; MMR3-NEXT: li16 $2, 0 # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: lw $3, %lo(c)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f6: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(c) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lw $3, %lo(c)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: addiu $2, $zero, 0 # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f6: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(c) # +; MMR6-NEXT: # > +; MMR6-NEXT: lw $3, %lo(c)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: li16 $2, 0 # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f6: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(c) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lwu $2, %lo(c)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f6: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(c) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lwu $2, %lo(c)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f6: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(c) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i32, i32 * @c + %1 = zext i32 %0 to i64 + ret i64 %1 +} + +define i64 @f7() { +; MIPS32-LABEL: f7: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, %hi(c) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: lw $3, %lo(c)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: sra $2, $3, 31 # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f7: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: lui $1, %hi(c) # +; MMR3-NEXT: # > +; MMR3-NEXT: lw $3, %lo(c)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: sra $2, $3, 31 # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f7: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lui $1, %hi(c) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: lw $3, %lo(c)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sra $2, $3, 31 # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f7: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: lui $1, %hi(c) # +; MMR6-NEXT: # > +; MMR6-NEXT: lw $3, %lo(c)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: sra $2, $3, 31 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS3-LABEL: f7: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: lui $1, %highest(c) # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %higher(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: daddiu $1, $1, %hi(c) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: dsll $1, $1, 16 # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: lw $2, %lo(c)($1) # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > +; +; MIPS64-LABEL: f7: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %highest(c) # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: dsll $1, $1, 16 # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: lw $2, %lo(c)($1) # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > +; +; MIPS64R6-LABEL: f7: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: lui $1, %highest(c) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lw $2, %lo(c)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +entry: + %0 = load i32, i32 * @c + %1 = sext i32 %0 to i64 + ret i64 %1 +} Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/store.ll @@ -0,0 +1,494 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3 +; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6 +; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4 +; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6 + +; Test subword and word stores. + +@a = common global i8 0, align 4 +@b = common global i16 0, align 4 +@c = common global i32 0, align 4 +@d = common global i64 0, align 8 + +define void @f1(i8 %a) { +; MIPS32-LABEL: f1: +; MIPS32: # %bb.0: +; MIPS32-NEXT: lui $1, %hi(a) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: sb $4, %lo(a)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f1: +; MMR3: # %bb.0: +; MMR3-NEXT: lui $1, %hi(a) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: sb $4, %lo(a)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f1: +; MIPS32R6: # %bb.0: +; MIPS32R6-NEXT: lui $1, %hi(a) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sb $4, %lo(a)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f1: +; MMR6: # %bb.0: +; MMR6-NEXT: lui $1, %hi(a) # +; MMR6-NEXT: # > +; MMR6-NEXT: sb $4, %lo(a)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS4-LABEL: f1: +; MIPS4: # %bb.0: +; MIPS4-NEXT: lui $1, %highest(a) # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %higher(a) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %hi(a) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: sb $4, %lo(a)($1) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; +; MIPS64R6-LABEL: f1: +; MIPS64R6: # %bb.0: +; MIPS64R6-NEXT: lui $1, %highest(a) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: sb $4, %lo(a)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > + store i8 %a, i8 * @a + ret void +} + +define void @f2(i16 %a) { +; MIPS32-LABEL: f2: +; MIPS32: # %bb.0: +; MIPS32-NEXT: lui $1, %hi(b) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: sh $4, %lo(b)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f2: +; MMR3: # %bb.0: +; MMR3-NEXT: lui $1, %hi(b) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: sh $4, %lo(b)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f2: +; MIPS32R6: # %bb.0: +; MIPS32R6-NEXT: lui $1, %hi(b) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sh $4, %lo(b)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f2: +; MMR6: # %bb.0: +; MMR6-NEXT: lui $1, %hi(b) # +; MMR6-NEXT: # > +; MMR6-NEXT: sh $4, %lo(b)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS4-LABEL: f2: +; MIPS4: # %bb.0: +; MIPS4-NEXT: lui $1, %highest(b) # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %higher(b) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %hi(b) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: sh $4, %lo(b)($1) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; +; MIPS64R6-LABEL: f2: +; MIPS64R6: # %bb.0: +; MIPS64R6-NEXT: lui $1, %highest(b) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: sh $4, %lo(b)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > + store i16 %a, i16 * @b + ret void +} + +define void @f3(i32 %a) { +; MIPS32-LABEL: f3: +; MIPS32: # %bb.0: +; MIPS32-NEXT: lui $1, %hi(c) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: sw $4, %lo(c)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f3: +; MMR3: # %bb.0: +; MMR3-NEXT: lui $1, %hi(c) # +; MMR3-NEXT: # > +; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: sw $4, %lo(c)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; +; MIPS32R6-LABEL: f3: +; MIPS32R6: # %bb.0: +; MIPS32R6-NEXT: lui $1, %hi(c) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sw $4, %lo(c)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f3: +; MMR6: # %bb.0: +; MMR6-NEXT: lui $1, %hi(c) # +; MMR6-NEXT: # > +; MMR6-NEXT: sw $4, %lo(c)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS4-LABEL: f3: +; MIPS4: # %bb.0: +; MIPS4-NEXT: sll $1, $4, 0 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: lui $2, %highest(c) # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $2, $2, %higher(c) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $2, $2, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $2, $2, %hi(c) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $2, $2, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: sw $1, %lo(c)($2) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; +; MIPS64R6-LABEL: f3: +; MIPS64R6: # %bb.0: +; MIPS64R6-NEXT: sll $1, $4, 0 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: lui $2, %highest(c) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $2, $2, %higher(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $2, $2, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $2, $2, %hi(c) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $2, $2, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: sw $1, %lo(c)($2) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > + store i32 %a, i32 * @c + ret void +} + +define void @f4(i64 %a) { +; MIPS32-LABEL: f4: +; MIPS32: # %bb.0: +; MIPS32-NEXT: lui $1, %hi(d) # +; MIPS32-NEXT: # > +; MIPS32-NEXT: sw $4, %lo(d)($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; MIPS32-NEXT: addiu $1, $1, %lo(d) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: sw $5, 4($1) # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > +; +; MMR3-LABEL: f4: +; MMR3: # %bb.0: +; MMR3-NEXT: lui $1, %hi(d) # +; MMR3-NEXT: # > +; MMR3-NEXT: sw $4, %lo(d)($1) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; MMR3-NEXT: addiu $2, $1, %lo(d) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; MMR3-NEXT: sw16 $5, 4($2) # +; MMR3-NEXT: # +; MMR3-NEXT: # > +; MMR3-NEXT: jrc $ra # > +; +; MIPS32R6-LABEL: f4: +; MIPS32R6: # %bb.0: +; MIPS32R6-NEXT: lui $1, %hi(d) # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sw $4, %lo(d)($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: jr $ra # +; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: sw $5, 4($1) # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > +; +; MMR6-LABEL: f4: +; MMR6: # %bb.0: +; MMR6-NEXT: lui $1, %hi(d) # +; MMR6-NEXT: # > +; MMR6-NEXT: sw $4, %lo(d)($1) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: addiu $2, $1, %lo(d) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: sw16 $5, 4($2) # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MIPS4-LABEL: f4: +; MIPS4: # %bb.0: +; MIPS4-NEXT: lui $1, %highest(d) # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %higher(d) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: daddiu $1, $1, %hi(d) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: dsll $1, $1, 16 # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: sd $4, %lo(d)($1) # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > +; +; MIPS64R6-LABEL: f4: +; MIPS64R6: # %bb.0: +; MIPS64R6-NEXT: lui $1, %highest(d) # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: dsll $1, $1, 16 # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: jr $ra # +; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: sd $4, %lo(d)($1) # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > + store i64 %a, i64 * @d + ret void +} Index: llvm/trunk/test/MC/Mips/micromips/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/invalid.s +++ llvm/trunk/test/MC/Mips/micromips/invalid.s @@ -121,10 +121,10 @@ xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number - lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset - lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset + lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset + lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset lb $4, 8($32) # CHECK: :[[@LINE]]:12: error: invalid register number lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number - lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset - lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset + lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset + lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset lbu $4, 8($32) # CHECK: :[[@LINE]]:13: error: invalid register number Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -253,12 +253,12 @@ xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number - lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset - lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset + lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset + lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset lb $4, 8($32) # CHECK: :[[@LINE]]:12: error: invalid register number lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number - lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset - lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset + lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset + lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset lbu $4, 8($32) # CHECK: :[[@LINE]]:13: error: invalid register number ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset