Index: test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll @@ -0,0 +1,822 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s + +; https://bugs.llvm.org/show_bug.cgi?id=37104 + +; All the advanced stuff (negative tests, commutativity) is handled in the +; scalar version of the test only. + +; ============================================================================ ; +; 8-bit vector width +; ============================================================================ ; + +define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind { +; CHECK-LABEL: out_v1i8: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <1 x i8> %x, %mask + %notmask = xor <1 x i8> %mask, + %my = and <1 x i8> %y, %notmask + %r = or <1 x i8> %mx, %my + ret <1 x i8> %r +} + +; ============================================================================ ; +; 16-bit vector width +; ============================================================================ ; + +define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind { +; CHECK-LABEL: out_v2i8: +; CHECK: // %bb.0: +; CHECK-NEXT: movi d3, #0x0000ff000000ff +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: and v1.8b, v1.8b, v2.8b +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %mx = and <2 x i8> %x, %mask + %notmask = xor <2 x i8> %mask, + %my = and <2 x i8> %y, %notmask + %r = or <2 x i8> %mx, %my + ret <2 x i8> %r +} + +define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind { +; CHECK-LABEL: out_v1i16: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <1 x i16> %x, %mask + %notmask = xor <1 x i16> %mask, + %my = and <1 x i16> %y, %notmask + %r = or <1 x i16> %mx, %my + ret <1 x i16> %r +} + +; ============================================================================ ; +; 32-bit vector width +; ============================================================================ ; + +define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-LABEL: out_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: movi d3, #0xff00ff00ff00ff +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: and v1.8b, v1.8b, v2.8b +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %mx = and <4 x i8> %x, %mask + %notmask = xor <4 x i8> %mask, + %my = and <4 x i8> %y, %notmask + %r = or <4 x i8> %mx, %my + ret <4 x i8> %r +} + +define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-LABEL: out_v4i8_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: movi d3, #0xff00ff00ff00ff +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: and v1.8b, v1.8b, v2.8b +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %mx = and <4 x i8> %x, %mask + %notmask = xor <4 x i8> %mask, + %my = and <4 x i8> %y, %notmask + %r = or <4 x i8> %mx, %my + ret <4 x i8> %r +} + +define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind { +; CHECK-LABEL: out_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: movi d3, #0x00ffff0000ffff +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: and v1.8b, v1.8b, v2.8b +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %mx = and <2 x i16> %x, %mask + %notmask = xor <2 x i16> %mask, + %my = and <2 x i16> %y, %notmask + %r = or <2 x i16> %mx, %my + ret <2 x i16> %r +} + +define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind { +; CHECK-LABEL: out_v1i32: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <1 x i32> %x, %mask + %notmask = xor <1 x i32> %mask, + %my = and <1 x i32> %y, %notmask + %r = or <1 x i32> %mx, %my + ret <1 x i32> %r +} + +; ============================================================================ ; +; 64-bit vector width +; ============================================================================ ; + +define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind { +; CHECK-LABEL: out_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <8 x i8> %x, %mask + %notmask = xor <8 x i8> %mask, + %my = and <8 x i8> %y, %notmask + %r = or <8 x i8> %mx, %my + ret <8 x i8> %r +} + +define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-LABEL: out_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <4 x i16> %x, %mask + %notmask = xor <4 x i16> %mask, + %my = and <4 x i16> %y, %notmask + %r = or <4 x i16> %mx, %my + ret <4 x i16> %r +} + +define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-LABEL: out_v4i16_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <4 x i16> %x, %mask + %notmask = xor <4 x i16> %mask, + %my = and <4 x i16> %y, %notmask + %r = or <4 x i16> %mx, %my + ret <4 x i16> %r +} + +define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind { +; CHECK-LABEL: out_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <2 x i32> %x, %mask + %notmask = xor <2 x i32> %mask, + %my = and <2 x i32> %y, %notmask + %r = or <2 x i32> %mx, %my + ret <2 x i32> %r +} + +define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind { +; CHECK-LABEL: out_v1i64: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <1 x i64> %x, %mask + %notmask = xor <1 x i64> %mask, + %my = and <1 x i64> %y, %notmask + %r = or <1 x i64> %mx, %my + ret <1 x i64> %r +} + +; ============================================================================ ; +; 128-bit vector width +; ============================================================================ ; + +define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind { +; CHECK-LABEL: out_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <16 x i8> %x, %mask + %notmask = xor <16 x i8> %mask, + %my = and <16 x i8> %y, %notmask + %r = or <16 x i8> %mx, %my + ret <16 x i8> %r +} + +define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind { +; CHECK-LABEL: out_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <8 x i16> %x, %mask + %notmask = xor <8 x i16> %mask, + %my = and <8 x i16> %y, %notmask + %r = or <8 x i16> %mx, %my + ret <8 x i16> %r +} + +define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-LABEL: out_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <4 x i32> %x, %mask + %notmask = xor <4 x i32> %mask, + %my = and <4 x i32> %y, %notmask + %r = or <4 x i32> %mx, %my + ret <4 x i32> %r +} + +define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-LABEL: out_v4i32_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <4 x i32> %x, %mask + %notmask = xor <4 x i32> %mask, + %my = and <4 x i32> %y, %notmask + %r = or <4 x i32> %mx, %my + ret <4 x i32> %r +} + +define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind { +; CHECK-LABEL: out_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret + %mx = and <2 x i64> %x, %mask + %notmask = xor <2 x i64> %mask, + %my = and <2 x i64> %y, %notmask + %r = or <2 x i64> %mx, %my + ret <2 x i64> %r +} + +; ============================================================================ ; +; 256-bit vector width +; ============================================================================ ; + +define <32 x i8> @out_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask) nounwind { +; CHECK-LABEL: out_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b +; CHECK-NEXT: bsl v5.16b, v1.16b, v3.16b +; CHECK-NEXT: mov v0.16b, v4.16b +; CHECK-NEXT: mov v1.16b, v5.16b +; CHECK-NEXT: ret + %mx = and <32 x i8> %x, %mask + %notmask = xor <32 x i8> %mask, + %my = and <32 x i8> %y, %notmask + %r = or <32 x i8> %mx, %my + ret <32 x i8> %r +} + +define <16 x i16> @out_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) nounwind { +; CHECK-LABEL: out_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b +; CHECK-NEXT: bsl v5.16b, v1.16b, v3.16b +; CHECK-NEXT: mov v0.16b, v4.16b +; CHECK-NEXT: mov v1.16b, v5.16b +; CHECK-NEXT: ret + %mx = and <16 x i16> %x, %mask + %notmask = xor <16 x i16> %mask, + %my = and <16 x i16> %y, %notmask + %r = or <16 x i16> %mx, %my + ret <16 x i16> %r +} + +define <8 x i32> @out_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) nounwind { +; CHECK-LABEL: out_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b +; CHECK-NEXT: bsl v5.16b, v1.16b, v3.16b +; CHECK-NEXT: mov v0.16b, v4.16b +; CHECK-NEXT: mov v1.16b, v5.16b +; CHECK-NEXT: ret + %mx = and <8 x i32> %x, %mask + %notmask = xor <8 x i32> %mask, + %my = and <8 x i32> %y, %notmask + %r = or <8 x i32> %mx, %my + ret <8 x i32> %r +} + +define <4 x i64> @out_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-LABEL: out_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b +; CHECK-NEXT: bsl v5.16b, v1.16b, v3.16b +; CHECK-NEXT: mov v0.16b, v4.16b +; CHECK-NEXT: mov v1.16b, v5.16b +; CHECK-NEXT: ret + %mx = and <4 x i64> %x, %mask + %notmask = xor <4 x i64> %mask, + %my = and <4 x i64> %y, %notmask + %r = or <4 x i64> %mx, %my + ret <4 x i64> %r +} + +define <4 x i64> @out_v4i64_undef(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-LABEL: out_v4i64_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b +; CHECK-NEXT: bsl v5.16b, v1.16b, v3.16b +; CHECK-NEXT: mov v0.16b, v4.16b +; CHECK-NEXT: mov v1.16b, v5.16b +; CHECK-NEXT: ret + %mx = and <4 x i64> %x, %mask + %notmask = xor <4 x i64> %mask, + %my = and <4 x i64> %y, %notmask + %r = or <4 x i64> %mx, %my + ret <4 x i64> %r +} + +; ============================================================================ ; +; 512-bit vector width +; ============================================================================ ; + +define <64 x i8> @out_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %mask) nounwind { +; CHECK-LABEL: out_v64i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: bsl v16.16b, v0.16b, v4.16b +; CHECK-NEXT: bsl v17.16b, v1.16b, v5.16b +; CHECK-NEXT: bsl v18.16b, v2.16b, v6.16b +; CHECK-NEXT: bsl v19.16b, v3.16b, v7.16b +; CHECK-NEXT: mov v0.16b, v16.16b +; CHECK-NEXT: mov v1.16b, v17.16b +; CHECK-NEXT: mov v2.16b, v18.16b +; CHECK-NEXT: mov v3.16b, v19.16b +; CHECK-NEXT: ret + %mx = and <64 x i8> %x, %mask + %notmask = xor <64 x i8> %mask, + %my = and <64 x i8> %y, %notmask + %r = or <64 x i8> %mx, %my + ret <64 x i8> %r +} + +define <32 x i16> @out_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> %mask) nounwind { +; CHECK-LABEL: out_v32i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: bsl v16.16b, v0.16b, v4.16b +; CHECK-NEXT: bsl v17.16b, v1.16b, v5.16b +; CHECK-NEXT: bsl v18.16b, v2.16b, v6.16b +; CHECK-NEXT: bsl v19.16b, v3.16b, v7.16b +; CHECK-NEXT: mov v0.16b, v16.16b +; CHECK-NEXT: mov v1.16b, v17.16b +; CHECK-NEXT: mov v2.16b, v18.16b +; CHECK-NEXT: mov v3.16b, v19.16b +; CHECK-NEXT: ret + %mx = and <32 x i16> %x, %mask + %notmask = xor <32 x i16> %mask, + %my = and <32 x i16> %y, %notmask + %r = or <32 x i16> %mx, %my + ret <32 x i16> %r +} + +define <16 x i32> @out_v16i32(<16 x i32> %x, <16 x i32> %y, <16 x i32> %mask) nounwind { +; CHECK-LABEL: out_v16i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: bsl v16.16b, v0.16b, v4.16b +; CHECK-NEXT: bsl v17.16b, v1.16b, v5.16b +; CHECK-NEXT: bsl v18.16b, v2.16b, v6.16b +; CHECK-NEXT: bsl v19.16b, v3.16b, v7.16b +; CHECK-NEXT: mov v0.16b, v16.16b +; CHECK-NEXT: mov v1.16b, v17.16b +; CHECK-NEXT: mov v2.16b, v18.16b +; CHECK-NEXT: mov v3.16b, v19.16b +; CHECK-NEXT: ret + %mx = and <16 x i32> %x, %mask + %notmask = xor <16 x i32> %mask, + %my = and <16 x i32> %y, %notmask + %r = or <16 x i32> %mx, %my + ret <16 x i32> %r +} + +define <8 x i64> @out_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-LABEL: out_v8i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: bsl v16.16b, v0.16b, v4.16b +; CHECK-NEXT: bsl v17.16b, v1.16b, v5.16b +; CHECK-NEXT: bsl v18.16b, v2.16b, v6.16b +; CHECK-NEXT: bsl v19.16b, v3.16b, v7.16b +; CHECK-NEXT: mov v0.16b, v16.16b +; CHECK-NEXT: mov v1.16b, v17.16b +; CHECK-NEXT: mov v2.16b, v18.16b +; CHECK-NEXT: mov v3.16b, v19.16b +; CHECK-NEXT: ret + %mx = and <8 x i64> %x, %mask + %notmask = xor <8 x i64> %mask, + %my = and <8 x i64> %y, %notmask + %r = or <8 x i64> %mx, %my + ret <8 x i64> %r +} + +define <8 x i64> @out_v8i64_undef(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-LABEL: out_v8i64_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: bsl v16.16b, v0.16b, v4.16b +; CHECK-NEXT: bsl v17.16b, v1.16b, v5.16b +; CHECK-NEXT: bsl v18.16b, v2.16b, v6.16b +; CHECK-NEXT: bsl v19.16b, v3.16b, v7.16b +; CHECK-NEXT: mov v0.16b, v16.16b +; CHECK-NEXT: mov v1.16b, v17.16b +; CHECK-NEXT: mov v2.16b, v18.16b +; CHECK-NEXT: mov v3.16b, v19.16b +; CHECK-NEXT: ret + %mx = and <8 x i64> %x, %mask + %notmask = xor <8 x i64> %mask, + %my = and <8 x i64> %y, %notmask + %r = or <8 x i64> %mx, %my + ret <8 x i64> %r +} + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Should be the same as the previous one. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; ============================================================================ ; +; 8-bit vector width +; ============================================================================ ; + +define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind { +; CHECK-LABEL: in_v1i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <1 x i8> %x, %y + %n1 = and <1 x i8> %n0, %mask + %r = xor <1 x i8> %n1, %y + ret <1 x i8> %r +} + +; ============================================================================ ; +; 16-bit vector width +; ============================================================================ ; + +define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind { +; CHECK-LABEL: in_v2i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <2 x i8> %x, %y + %n1 = and <2 x i8> %n0, %mask + %r = xor <2 x i8> %n1, %y + ret <2 x i8> %r +} + +define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind { +; CHECK-LABEL: in_v1i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <1 x i16> %x, %y + %n1 = and <1 x i16> %n0, %mask + %r = xor <1 x i16> %n1, %y + ret <1 x i16> %r +} + +; ============================================================================ ; +; 32-bit vector width +; ============================================================================ ; + +define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-LABEL: in_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <4 x i8> %x, %y + %n1 = and <4 x i8> %n0, %mask + %r = xor <4 x i8> %n1, %y + ret <4 x i8> %r +} + +define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind { +; CHECK-LABEL: in_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <2 x i16> %x, %y + %n1 = and <2 x i16> %n0, %mask + %r = xor <2 x i16> %n1, %y + ret <2 x i16> %r +} + +define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind { +; CHECK-LABEL: in_v1i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <1 x i32> %x, %y + %n1 = and <1 x i32> %n0, %mask + %r = xor <1 x i32> %n1, %y + ret <1 x i32> %r +} + +; ============================================================================ ; +; 64-bit vector width +; ============================================================================ ; + +define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind { +; CHECK-LABEL: in_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <8 x i8> %x, %y + %n1 = and <8 x i8> %n0, %mask + %r = xor <8 x i8> %n1, %y + ret <8 x i8> %r +} + +define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-LABEL: in_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <4 x i16> %x, %y + %n1 = and <4 x i16> %n0, %mask + %r = xor <4 x i16> %n1, %y + ret <4 x i16> %r +} + +define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind { +; CHECK-LABEL: in_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <2 x i32> %x, %y + %n1 = and <2 x i32> %n0, %mask + %r = xor <2 x i32> %n1, %y + ret <2 x i32> %r +} + +define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind { +; CHECK-LABEL: in_v1i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %n0 = xor <1 x i64> %x, %y + %n1 = and <1 x i64> %n0, %mask + %r = xor <1 x i64> %n1, %y + ret <1 x i64> %r +} + +; ============================================================================ ; +; 128-bit vector width +; ============================================================================ ; + +define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind { +; CHECK-LABEL: in_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: and v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %n0 = xor <16 x i8> %x, %y + %n1 = and <16 x i8> %n0, %mask + %r = xor <16 x i8> %n1, %y + ret <16 x i8> %r +} + +define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind { +; CHECK-LABEL: in_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: and v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %n0 = xor <8 x i16> %x, %y + %n1 = and <8 x i16> %n0, %mask + %r = xor <8 x i16> %n1, %y + ret <8 x i16> %r +} + +define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-LABEL: in_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: and v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %n0 = xor <4 x i32> %x, %y + %n1 = and <4 x i32> %n0, %mask + %r = xor <4 x i32> %n1, %y + ret <4 x i32> %r +} + +define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind { +; CHECK-LABEL: in_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: and v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %n0 = xor <2 x i64> %x, %y + %n1 = and <2 x i64> %n0, %mask + %r = xor <2 x i64> %n1, %y + ret <2 x i64> %r +} + +; ============================================================================ ; +; 256-bit vector width +; ============================================================================ ; + +define <32 x i8> @in_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask) nounwind { +; CHECK-LABEL: in_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: and v0.16b, v0.16b, v4.16b +; CHECK-NEXT: and v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: ret + %n0 = xor <32 x i8> %x, %y + %n1 = and <32 x i8> %n0, %mask + %r = xor <32 x i8> %n1, %y + ret <32 x i8> %r +} + +define <16 x i16> @in_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) nounwind { +; CHECK-LABEL: in_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: and v0.16b, v0.16b, v4.16b +; CHECK-NEXT: and v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: ret + %n0 = xor <16 x i16> %x, %y + %n1 = and <16 x i16> %n0, %mask + %r = xor <16 x i16> %n1, %y + ret <16 x i16> %r +} + +define <8 x i32> @in_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) nounwind { +; CHECK-LABEL: in_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: and v0.16b, v0.16b, v4.16b +; CHECK-NEXT: and v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: ret + %n0 = xor <8 x i32> %x, %y + %n1 = and <8 x i32> %n0, %mask + %r = xor <8 x i32> %n1, %y + ret <8 x i32> %r +} + +define <4 x i64> @in_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-LABEL: in_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: and v0.16b, v0.16b, v4.16b +; CHECK-NEXT: and v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: ret + %n0 = xor <4 x i64> %x, %y + %n1 = and <4 x i64> %n0, %mask + %r = xor <4 x i64> %n1, %y + ret <4 x i64> %r +} + +; ============================================================================ ; +; 512-bit vector width +; ============================================================================ ; + +define <64 x i8> @in_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %mask) nounwind { +; CHECK-LABEL: in_v64i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: and v3.16b, v3.16b, v19.16b +; CHECK-NEXT: and v2.16b, v2.16b, v18.16b +; CHECK-NEXT: and v1.16b, v1.16b, v17.16b +; CHECK-NEXT: and v0.16b, v0.16b, v16.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: ret + %n0 = xor <64 x i8> %x, %y + %n1 = and <64 x i8> %n0, %mask + %r = xor <64 x i8> %n1, %y + ret <64 x i8> %r +} + +define <32 x i16> @in_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> %mask) nounwind { +; CHECK-LABEL: in_v32i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: and v3.16b, v3.16b, v19.16b +; CHECK-NEXT: and v2.16b, v2.16b, v18.16b +; CHECK-NEXT: and v1.16b, v1.16b, v17.16b +; CHECK-NEXT: and v0.16b, v0.16b, v16.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: ret + %n0 = xor <32 x i16> %x, %y + %n1 = and <32 x i16> %n0, %mask + %r = xor <32 x i16> %n1, %y + ret <32 x i16> %r +} + +define <16 x i32> @in_v16i32(<16 x i32> %x, <16 x i32> %y, <16 x i32> %mask) nounwind { +; CHECK-LABEL: in_v16i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: and v3.16b, v3.16b, v19.16b +; CHECK-NEXT: and v2.16b, v2.16b, v18.16b +; CHECK-NEXT: and v1.16b, v1.16b, v17.16b +; CHECK-NEXT: and v0.16b, v0.16b, v16.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: ret + %n0 = xor <16 x i32> %x, %y + %n1 = and <16 x i32> %n0, %mask + %r = xor <16 x i32> %n1, %y + ret <16 x i32> %r +} + +define <8 x i64> @in_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-LABEL: in_v8i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q16, q17, [sp] +; CHECK-NEXT: ldp q18, q19, [sp, #32] +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: and v3.16b, v3.16b, v19.16b +; CHECK-NEXT: and v2.16b, v2.16b, v18.16b +; CHECK-NEXT: and v1.16b, v1.16b, v17.16b +; CHECK-NEXT: and v0.16b, v0.16b, v16.16b +; CHECK-NEXT: eor v0.16b, v0.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: ret + %n0 = xor <8 x i64> %x, %y + %n1 = and <8 x i64> %n0, %mask + %r = xor <8 x i64> %n1, %y + ret <8 x i64> %r +} Index: test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll @@ -0,0 +1,11134 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=-sse,-sse2,-sse4.1,-avx,-avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-BASELINE +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,-sse2,-sse4.1,-avx,-avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-SSE +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,-sse4.1,-avx,-avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-SSE2 +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,-avx,-avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-SSE41 +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,+avx,-avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-AVX +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,+avx,+avx2,-avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-AVX2 +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,+avx,+avx2,+avx512f,-avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-AVX512F +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,+avx,+avx2,+avx512f,+avx512dq,-avx512vl < %s | FileCheck %s --check-prefix=CHECK-AVX512DQ +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2,+sse4.1,+avx,+avx2,+avx512f,+avx512dq,+avx512vl < %s | FileCheck %s --check-prefix=CHECK-AVX512VL + +; https://bugs.llvm.org/show_bug.cgi?id=37104 + +; All the advanced stuff (negative tests, commutativity) is handled in the +; scalar version of the test only. + +; ============================================================================ ; +; 8-bit vector width +; ============================================================================ ; + +define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v1i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb %sil, %dl +; CHECK-BASELINE-NEXT: orb %dil, %dl +; CHECK-BASELINE-NEXT: movl %edx, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v1i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb %sil, %dl +; CHECK-SSE-NEXT: orb %dil, %dl +; CHECK-SSE-NEXT: movl %edx, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v1i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: notb %dl +; CHECK-SSE2-NEXT: andb %sil, %dl +; CHECK-SSE2-NEXT: orb %dil, %dl +; CHECK-SSE2-NEXT: movl %edx, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v1i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: notb %dl +; CHECK-SSE41-NEXT: andb %sil, %dl +; CHECK-SSE41-NEXT: orb %dil, %dl +; CHECK-SSE41-NEXT: movl %edx, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v1i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: notb %dl +; CHECK-AVX-NEXT: andb %sil, %dl +; CHECK-AVX-NEXT: orb %dil, %dl +; CHECK-AVX-NEXT: movl %edx, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v1i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: notb %dl +; CHECK-AVX2-NEXT: andb %sil, %dl +; CHECK-AVX2-NEXT: orb %dil, %dl +; CHECK-AVX2-NEXT: movl %edx, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v1i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: notb %dl +; CHECK-AVX512F-NEXT: andb %sil, %dl +; CHECK-AVX512F-NEXT: orb %dil, %dl +; CHECK-AVX512F-NEXT: movl %edx, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v1i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: notb %dl +; CHECK-AVX512DQ-NEXT: andb %sil, %dl +; CHECK-AVX512DQ-NEXT: orb %dil, %dl +; CHECK-AVX512DQ-NEXT: movl %edx, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v1i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: notb %dl +; CHECK-AVX512VL-NEXT: andb %sil, %dl +; CHECK-AVX512VL-NEXT: orb %dil, %dl +; CHECK-AVX512VL-NEXT: movl %edx, %eax +; CHECK-AVX512VL-NEXT: retq + %mx = and <1 x i8> %x, %mask + %notmask = xor <1 x i8> %mask, + %my = and <1 x i8> %y, %notmask + %r = or <1 x i8> %mx, %my + ret <1 x i8> %r +} + +; ============================================================================ ; +; 16-bit vector width +; ============================================================================ ; + +define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v2i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: notb %r8b +; CHECK-BASELINE-NEXT: notb %r9b +; CHECK-BASELINE-NEXT: andb %cl, %r9b +; CHECK-BASELINE-NEXT: andb %dl, %r8b +; CHECK-BASELINE-NEXT: orb %dil, %r8b +; CHECK-BASELINE-NEXT: orb %sil, %r9b +; CHECK-BASELINE-NEXT: movl %r8d, %eax +; CHECK-BASELINE-NEXT: movl %r9d, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v2i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: notb %r8b +; CHECK-SSE-NEXT: notb %r9b +; CHECK-SSE-NEXT: andb %cl, %r9b +; CHECK-SSE-NEXT: andb %dl, %r8b +; CHECK-SSE-NEXT: orb %dil, %r8b +; CHECK-SSE-NEXT: orb %sil, %r9b +; CHECK-SSE-NEXT: movl %r8d, %eax +; CHECK-SSE-NEXT: movl %r9d, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v2i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v2i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v2i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v2i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v2i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v2i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v2i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <2 x i8> %x, %mask + %notmask = xor <2 x i8> %mask, + %my = and <2 x i8> %y, %notmask + %r = or <2 x i8> %mx, %my + ret <2 x i8> %r +} + +define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v1i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andl %esi, %edx +; CHECK-BASELINE-NEXT: orl %edi, %edx +; CHECK-BASELINE-NEXT: movl %edx, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v1i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andl %esi, %edx +; CHECK-SSE-NEXT: orl %edi, %edx +; CHECK-SSE-NEXT: movl %edx, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v1i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: notl %edx +; CHECK-SSE2-NEXT: andl %esi, %edx +; CHECK-SSE2-NEXT: orl %edi, %edx +; CHECK-SSE2-NEXT: movl %edx, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v1i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: notl %edx +; CHECK-SSE41-NEXT: andl %esi, %edx +; CHECK-SSE41-NEXT: orl %edi, %edx +; CHECK-SSE41-NEXT: movl %edx, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v1i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: notl %edx +; CHECK-AVX-NEXT: andl %esi, %edx +; CHECK-AVX-NEXT: orl %edi, %edx +; CHECK-AVX-NEXT: movl %edx, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v1i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: notl %edx +; CHECK-AVX2-NEXT: andl %esi, %edx +; CHECK-AVX2-NEXT: orl %edi, %edx +; CHECK-AVX2-NEXT: movl %edx, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v1i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: notl %edx +; CHECK-AVX512F-NEXT: andl %esi, %edx +; CHECK-AVX512F-NEXT: orl %edi, %edx +; CHECK-AVX512F-NEXT: movl %edx, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v1i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: notl %edx +; CHECK-AVX512DQ-NEXT: andl %esi, %edx +; CHECK-AVX512DQ-NEXT: orl %edi, %edx +; CHECK-AVX512DQ-NEXT: movl %edx, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v1i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: notl %edx +; CHECK-AVX512VL-NEXT: andl %esi, %edx +; CHECK-AVX512VL-NEXT: orl %edi, %edx +; CHECK-AVX512VL-NEXT: movl %edx, %eax +; CHECK-AVX512VL-NEXT: retq + %mx = and <1 x i16> %x, %mask + %notmask = xor <1 x i16> %mask, + %my = and <1 x i16> %y, %notmask + %r = or <1 x i16> %mx, %my + ret <1 x i16> %r +} + +; ============================================================================ ; +; 32-bit vector width +; ============================================================================ ; + +define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: andb %bl, %r8b +; CHECK-BASELINE-NEXT: andb %al, %cl +; CHECK-BASELINE-NEXT: andb %r11b, %dl +; CHECK-BASELINE-NEXT: andb %r10b, %sil +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb %r9b, %r10b +; CHECK-BASELINE-NEXT: orb %sil, %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %r8b, %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %cl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %dl, %r11b +; CHECK-BASELINE-NEXT: movb %bl, 3(%rdi) +; CHECK-BASELINE-NEXT: movb %al, 2(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: andb %bl, %r8b +; CHECK-SSE-NEXT: andb %al, %cl +; CHECK-SSE-NEXT: andb %r11b, %dl +; CHECK-SSE-NEXT: andb %r10b, %sil +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb %r9b, %r10b +; CHECK-SSE-NEXT: orb %sil, %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %r8b, %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %cl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %dl, %r11b +; CHECK-SSE-NEXT: movb %bl, 3(%rdi) +; CHECK-SSE-NEXT: movb %al, 2(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 1(%rdi) +; CHECK-SSE-NEXT: movb %r10b, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX2-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX512F-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX512DQ-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i8> %x, %mask + %notmask = xor <4 x i8> %mask, + %my = and <4 x i8> %y, %notmask + %r = or <4 x i8> %mx, %my + ret <4 x i8> %r +} + +define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i8_undef: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %al, %r8b +; CHECK-BASELINE-NEXT: andb %r11b, %dl +; CHECK-BASELINE-NEXT: andb %r10b, %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb %r9b, %r10b +; CHECK-BASELINE-NEXT: orb %sil, %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %r8b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %dl, %r11b +; CHECK-BASELINE-NEXT: movb %cl, 2(%rdi) +; CHECK-BASELINE-NEXT: movb %al, 3(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i8_undef: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %al, %r8b +; CHECK-SSE-NEXT: andb %r11b, %dl +; CHECK-SSE-NEXT: andb %r10b, %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb %r9b, %r10b +; CHECK-SSE-NEXT: orb %sil, %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %r8b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %dl, %r11b +; CHECK-SSE-NEXT: movb %cl, 2(%rdi) +; CHECK-SSE-NEXT: movb %al, 3(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 1(%rdi) +; CHECK-SSE-NEXT: movb %r10b, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i8_undef: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i8_undef: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i8_undef: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i8_undef: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX2-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i8_undef: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX512F-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i8_undef: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255] +; CHECK-AVX512DQ-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i8_undef: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i8> %x, %mask + %notmask = xor <4 x i8> %mask, + %my = and <4 x i8> %y, %notmask + %r = or <4 x i8> %mx, %my + ret <4 x i8> %r +} + +define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v2i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: notl %r9d +; CHECK-BASELINE-NEXT: andl %ecx, %r9d +; CHECK-BASELINE-NEXT: orl %esi, %r9d +; CHECK-BASELINE-NEXT: andl %edx, %r8d +; CHECK-BASELINE-NEXT: orl %edi, %r8d +; CHECK-BASELINE-NEXT: movl %r8d, %eax +; CHECK-BASELINE-NEXT: movl %r9d, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v2i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: notl %r9d +; CHECK-SSE-NEXT: andl %ecx, %r9d +; CHECK-SSE-NEXT: orl %esi, %r9d +; CHECK-SSE-NEXT: andl %edx, %r8d +; CHECK-SSE-NEXT: orl %edi, %r8d +; CHECK-SSE-NEXT: movl %r8d, %eax +; CHECK-SSE-NEXT: movl %r9d, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v2i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v2i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v2i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v2i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v2i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v2i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v2i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <2 x i16> %x, %mask + %notmask = xor <2 x i16> %mask, + %my = and <2 x i16> %y, %notmask + %r = or <2 x i16> %mx, %my + ret <2 x i16> %r +} + +define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v1i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andl %esi, %edx +; CHECK-BASELINE-NEXT: orl %edi, %edx +; CHECK-BASELINE-NEXT: movl %edx, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v1i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andl %esi, %edx +; CHECK-SSE-NEXT: orl %edi, %edx +; CHECK-SSE-NEXT: movl %edx, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v1i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: notl %edx +; CHECK-SSE2-NEXT: andl %esi, %edx +; CHECK-SSE2-NEXT: orl %edi, %edx +; CHECK-SSE2-NEXT: movl %edx, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v1i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: notl %edx +; CHECK-SSE41-NEXT: andl %esi, %edx +; CHECK-SSE41-NEXT: orl %edi, %edx +; CHECK-SSE41-NEXT: movl %edx, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v1i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: notl %edx +; CHECK-AVX-NEXT: andl %esi, %edx +; CHECK-AVX-NEXT: orl %edi, %edx +; CHECK-AVX-NEXT: movl %edx, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v1i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: notl %edx +; CHECK-AVX2-NEXT: andl %esi, %edx +; CHECK-AVX2-NEXT: orl %edi, %edx +; CHECK-AVX2-NEXT: movl %edx, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v1i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: notl %edx +; CHECK-AVX512F-NEXT: andl %esi, %edx +; CHECK-AVX512F-NEXT: orl %edi, %edx +; CHECK-AVX512F-NEXT: movl %edx, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v1i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: notl %edx +; CHECK-AVX512DQ-NEXT: andl %esi, %edx +; CHECK-AVX512DQ-NEXT: orl %edi, %edx +; CHECK-AVX512DQ-NEXT: movl %edx, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v1i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: notl %edx +; CHECK-AVX512VL-NEXT: andl %esi, %edx +; CHECK-AVX512VL-NEXT: orl %edi, %edx +; CHECK-AVX512VL-NEXT: movl %edx, %eax +; CHECK-AVX512VL-NEXT: retq + %mx = and <1 x i32> %x, %mask + %notmask = xor <1 x i32> %mask, + %my = and <1 x i32> %y, %notmask + %r = or <1 x i32> %mx, %my + ret <1 x i32> %r +} + +; ============================================================================ ; +; 64-bit vector width +; ============================================================================ ; + +define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v8i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %al, %r9b +; CHECK-BASELINE-NEXT: andb %bl, %r8b +; CHECK-BASELINE-NEXT: andb %r14b, %cl +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: andb %r11b, %dl +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: andb %r10b, %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: andb %r12b, %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb %r15b, %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: andb %bpl, %dl +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: notb %r14b +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: notb %r15b +; CHECK-BASELINE-NEXT: notb %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: orb %r13b, %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: orb %cl, %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %dl, %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %r9b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %r8b, %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: orb {{[-0-9]+}}(%r{{[sb]}}p), %r14b # 1-byte Folded Reload +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb {{[-0-9]+}}(%r{{[sb]}}p), %r11b # 1-byte Folded Reload +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %sil, %r10b +; CHECK-BASELINE-NEXT: movb %r12b, 7(%rdi) +; CHECK-BASELINE-NEXT: movb %r15b, 6(%rdi) +; CHECK-BASELINE-NEXT: movb %bpl, 5(%rdi) +; CHECK-BASELINE-NEXT: movb %al, 4(%rdi) +; CHECK-BASELINE-NEXT: movb %bl, 3(%rdi) +; CHECK-BASELINE-NEXT: movb %r14b, 2(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v8i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %al, %r9b +; CHECK-SSE-NEXT: andb %bl, %r8b +; CHECK-SSE-NEXT: andb %r14b, %cl +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: andb %r11b, %dl +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: andb %r10b, %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: andb %r12b, %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb %r15b, %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: andb %bpl, %dl +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: notb %r14b +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: notb %r15b +; CHECK-SSE-NEXT: notb %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: orb %r13b, %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: orb %cl, %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %dl, %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %r9b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %r8b, %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: orb {{[-0-9]+}}(%r{{[sb]}}p), %r14b # 1-byte Folded Reload +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb {{[-0-9]+}}(%r{{[sb]}}p), %r11b # 1-byte Folded Reload +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %sil, %r10b +; CHECK-SSE-NEXT: movb %r12b, 7(%rdi) +; CHECK-SSE-NEXT: movb %r15b, 6(%rdi) +; CHECK-SSE-NEXT: movb %bpl, 5(%rdi) +; CHECK-SSE-NEXT: movb %al, 4(%rdi) +; CHECK-SSE-NEXT: movb %bl, 3(%rdi) +; CHECK-SSE-NEXT: movb %r14b, 2(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 1(%rdi) +; CHECK-SSE-NEXT: movb %r10b, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v8i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v8i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v8i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v8i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v8i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v8i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v8i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <8 x i8> %x, %mask + %notmask = xor <8 x i8> %mask, + %my = and <8 x i8> %y, %notmask + %r = or <8 x i8> %mx, %my + ret <8 x i8> %r +} + +define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %ebx, %esi +; CHECK-BASELINE-NEXT: andl %eax, %r8d +; CHECK-BASELINE-NEXT: andl %r11d, %ecx +; CHECK-BASELINE-NEXT: andl %r10d, %edx +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andl %r9d, %ebx +; CHECK-BASELINE-NEXT: orl %esi, %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: orl %r8d, %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: orl %ecx, %r11d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: orl %edx, %r10d +; CHECK-BASELINE-NEXT: movw %bx, (%rdi) +; CHECK-BASELINE-NEXT: movw %ax, 6(%rdi) +; CHECK-BASELINE-NEXT: movw %r11w, 4(%rdi) +; CHECK-BASELINE-NEXT: movw %r10w, 2(%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %ebx, %esi +; CHECK-SSE-NEXT: andl %eax, %r8d +; CHECK-SSE-NEXT: andl %r11d, %ecx +; CHECK-SSE-NEXT: andl %r10d, %edx +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: notl %r11d +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andl %r9d, %ebx +; CHECK-SSE-NEXT: orl %esi, %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: orl %r8d, %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: orl %ecx, %r11d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: orl %edx, %r10d +; CHECK-SSE-NEXT: movw %bx, (%rdi) +; CHECK-SSE-NEXT: movw %ax, 6(%rdi) +; CHECK-SSE-NEXT: movw %r11w, 4(%rdi) +; CHECK-SSE-NEXT: movw %r10w, 2(%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX2-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX512F-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX512DQ-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i16> %x, %mask + %notmask = xor <4 x i16> %mask, + %my = and <4 x i16> %y, %notmask + %r = or <4 x i16> %mx, %my + ret <4 x i16> %r +} + +define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i16_undef: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %eax, %esi +; CHECK-BASELINE-NEXT: andl %r11d, %r8d +; CHECK-BASELINE-NEXT: andl %r10d, %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andl %r9d, %eax +; CHECK-BASELINE-NEXT: orl %esi, %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: orl %r8d, %r11d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: orl %edx, %r10d +; CHECK-BASELINE-NEXT: movw %cx, 4(%rdi) +; CHECK-BASELINE-NEXT: movw %ax, (%rdi) +; CHECK-BASELINE-NEXT: movw %r11w, 6(%rdi) +; CHECK-BASELINE-NEXT: movw %r10w, 2(%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i16_undef: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %eax, %esi +; CHECK-SSE-NEXT: andl %r11d, %r8d +; CHECK-SSE-NEXT: andl %r10d, %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: notl %r11d +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andl %r9d, %eax +; CHECK-SSE-NEXT: orl %esi, %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: orl %r8d, %r11d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: orl %edx, %r10d +; CHECK-SSE-NEXT: movw %cx, 4(%rdi) +; CHECK-SSE-NEXT: movw %ax, (%rdi) +; CHECK-SSE-NEXT: movw %r11w, 6(%rdi) +; CHECK-SSE-NEXT: movw %r10w, 2(%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i16_undef: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i16_undef: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i16_undef: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i16_undef: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX2-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i16_undef: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX512F-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i16_undef: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm3 = [65535,65535,65535,65535] +; CHECK-AVX512DQ-NEXT: vxorps %xmm3, %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i16_undef: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i16> %x, %mask + %notmask = xor <4 x i16> %mask, + %my = and <4 x i16> %y, %notmask + %r = or <4 x i16> %mx, %my + ret <4 x i16> %r +} + +define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v2i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: notl %r9d +; CHECK-BASELINE-NEXT: andl %ecx, %r9d +; CHECK-BASELINE-NEXT: orl %esi, %r9d +; CHECK-BASELINE-NEXT: andl %edx, %r8d +; CHECK-BASELINE-NEXT: orl %edi, %r8d +; CHECK-BASELINE-NEXT: movl %r8d, %eax +; CHECK-BASELINE-NEXT: movl %r9d, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v2i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: notl %r9d +; CHECK-SSE-NEXT: andl %ecx, %r9d +; CHECK-SSE-NEXT: orl %esi, %r9d +; CHECK-SSE-NEXT: andl %edx, %r8d +; CHECK-SSE-NEXT: orl %edi, %r8d +; CHECK-SSE-NEXT: movl %r8d, %eax +; CHECK-SSE-NEXT: movl %r9d, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v2i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE2-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v2i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: andps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v2i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v2i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v2i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v2i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v2i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <2 x i32> %x, %mask + %notmask = xor <2 x i32> %mask, + %my = and <2 x i32> %y, %notmask + %r = or <2 x i32> %mx, %my + ret <2 x i32> %r +} + +define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v1i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andq %rdx, %rdi +; CHECK-BASELINE-NEXT: notq %rdx +; CHECK-BASELINE-NEXT: andq %rsi, %rdx +; CHECK-BASELINE-NEXT: orq %rdi, %rdx +; CHECK-BASELINE-NEXT: movq %rdx, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v1i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andq %rdx, %rdi +; CHECK-SSE-NEXT: notq %rdx +; CHECK-SSE-NEXT: andq %rsi, %rdx +; CHECK-SSE-NEXT: orq %rdi, %rdx +; CHECK-SSE-NEXT: movq %rdx, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v1i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andq %rdx, %rdi +; CHECK-SSE2-NEXT: notq %rdx +; CHECK-SSE2-NEXT: andq %rsi, %rdx +; CHECK-SSE2-NEXT: orq %rdi, %rdx +; CHECK-SSE2-NEXT: movq %rdx, %rax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v1i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andq %rdx, %rdi +; CHECK-SSE41-NEXT: notq %rdx +; CHECK-SSE41-NEXT: andq %rsi, %rdx +; CHECK-SSE41-NEXT: orq %rdi, %rdx +; CHECK-SSE41-NEXT: movq %rdx, %rax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v1i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: andq %rdx, %rdi +; CHECK-AVX-NEXT: notq %rdx +; CHECK-AVX-NEXT: andq %rsi, %rdx +; CHECK-AVX-NEXT: orq %rdi, %rdx +; CHECK-AVX-NEXT: movq %rdx, %rax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v1i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: andq %rdx, %rdi +; CHECK-AVX2-NEXT: notq %rdx +; CHECK-AVX2-NEXT: andq %rsi, %rdx +; CHECK-AVX2-NEXT: orq %rdi, %rdx +; CHECK-AVX2-NEXT: movq %rdx, %rax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v1i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: andq %rdx, %rdi +; CHECK-AVX512F-NEXT: notq %rdx +; CHECK-AVX512F-NEXT: andq %rsi, %rdx +; CHECK-AVX512F-NEXT: orq %rdi, %rdx +; CHECK-AVX512F-NEXT: movq %rdx, %rax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v1i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: andq %rdx, %rdi +; CHECK-AVX512DQ-NEXT: notq %rdx +; CHECK-AVX512DQ-NEXT: andq %rsi, %rdx +; CHECK-AVX512DQ-NEXT: orq %rdi, %rdx +; CHECK-AVX512DQ-NEXT: movq %rdx, %rax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v1i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: andq %rdx, %rdi +; CHECK-AVX512VL-NEXT: notq %rdx +; CHECK-AVX512VL-NEXT: andq %rsi, %rdx +; CHECK-AVX512VL-NEXT: orq %rdi, %rdx +; CHECK-AVX512VL-NEXT: movq %rdx, %rax +; CHECK-AVX512VL-NEXT: retq + %mx = and <1 x i64> %x, %mask + %notmask = xor <1 x i64> %mask, + %my = and <1 x i64> %y, %notmask + %r = or <1 x i64> %mx, %my + ret <1 x i64> %r +} + +; ============================================================================ ; +; 128-bit vector width +; ============================================================================ ; + +define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v16i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %al, %sil +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %sil, %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %cl, %sil +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %sil, %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %dl, %sil +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: orb %sil, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %bl, %sil +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %sil, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r13b, %sil +; CHECK-BASELINE-NEXT: notb %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: orb %sil, %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r12b, %sil +; CHECK-BASELINE-NEXT: notb %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: orb %sil, %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r15b, %sil +; CHECK-BASELINE-NEXT: notb %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: orb %sil, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r14b, %sil +; CHECK-BASELINE-NEXT: notb %r14b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: orb %sil, %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %bpl, %sil +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %sil, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r11b, %sil +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %sil, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb %r10b, %sil +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %sil, %r10b +; CHECK-BASELINE-NEXT: movb %al, 15(%rdi) +; CHECK-BASELINE-NEXT: movb %cl, 14(%rdi) +; CHECK-BASELINE-NEXT: movb %dl, 13(%rdi) +; CHECK-BASELINE-NEXT: movb %bl, 12(%rdi) +; CHECK-BASELINE-NEXT: movb %r13b, 11(%rdi) +; CHECK-BASELINE-NEXT: movb %r12b, 10(%rdi) +; CHECK-BASELINE-NEXT: movb %r15b, 9(%rdi) +; CHECK-BASELINE-NEXT: movb %r14b, 8(%rdi) +; CHECK-BASELINE-NEXT: movb %bpl, 7(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 6(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %al, %r9b +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %r9b, %al +; CHECK-BASELINE-NEXT: movb %r10b, 5(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb %cl, %r8b +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %r8b, %cl +; CHECK-BASELINE-NEXT: movb %al, 4(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 3(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %cl, %dl +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %dl, %cl +; CHECK-BASELINE-NEXT: movb %al, 2(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %al, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v16i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %al, %sil +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %sil, %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %cl, %sil +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %sil, %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %dl, %sil +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: orb %sil, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %bl, %sil +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %sil, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r13b, %sil +; CHECK-SSE-NEXT: notb %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: orb %sil, %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r12b, %sil +; CHECK-SSE-NEXT: notb %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: orb %sil, %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r15b, %sil +; CHECK-SSE-NEXT: notb %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: orb %sil, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r14b, %sil +; CHECK-SSE-NEXT: notb %r14b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: orb %sil, %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %bpl, %sil +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %sil, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r11b, %sil +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %sil, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb %r10b, %sil +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %sil, %r10b +; CHECK-SSE-NEXT: movb %al, 15(%rdi) +; CHECK-SSE-NEXT: movb %cl, 14(%rdi) +; CHECK-SSE-NEXT: movb %dl, 13(%rdi) +; CHECK-SSE-NEXT: movb %bl, 12(%rdi) +; CHECK-SSE-NEXT: movb %r13b, 11(%rdi) +; CHECK-SSE-NEXT: movb %r12b, 10(%rdi) +; CHECK-SSE-NEXT: movb %r15b, 9(%rdi) +; CHECK-SSE-NEXT: movb %r14b, 8(%rdi) +; CHECK-SSE-NEXT: movb %bpl, 7(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 6(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %al, %r9b +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %r9b, %al +; CHECK-SSE-NEXT: movb %r10b, 5(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb %cl, %r8b +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %r8b, %cl +; CHECK-SSE-NEXT: movb %al, 4(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 3(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %cl, %dl +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %dl, %cl +; CHECK-SSE-NEXT: movb %al, 2(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 1(%rdi) +; CHECK-SSE-NEXT: movb %al, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v16i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v16i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v16i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v16i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v16i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v16i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v16i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <16 x i8> %x, %mask + %notmask = xor <16 x i8> %mask, + %my = and <16 x i8> %y, %notmask + %r = or <16 x i8> %mx, %my + ret <16 x i8> %r +} + +define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v8i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andw %r14w, %bx +; CHECK-BASELINE-NEXT: notl %r14d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-BASELINE-NEXT: orl %ebx, %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andw %r11w, %bx +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: orl %ebx, %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andw %r10w, %bx +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: orl %ebx, %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %ebx, %r9d +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: orl %r9d, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %eax, %r8d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: orl %r8d, %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: andl %ebp, %ecx +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: orl %ecx, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: andl %ecx, %edx +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %edx, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andl %edx, %esi +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: orl %esi, %edx +; CHECK-BASELINE-NEXT: movw %r14w, 14(%rdi) +; CHECK-BASELINE-NEXT: movw %r11w, 12(%rdi) +; CHECK-BASELINE-NEXT: movw %r10w, 10(%rdi) +; CHECK-BASELINE-NEXT: movw %bx, 8(%rdi) +; CHECK-BASELINE-NEXT: movw %ax, 6(%rdi) +; CHECK-BASELINE-NEXT: movw %bp, 4(%rdi) +; CHECK-BASELINE-NEXT: movw %cx, 2(%rdi) +; CHECK-BASELINE-NEXT: movw %dx, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v8i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andw %r14w, %bx +; CHECK-SSE-NEXT: notl %r14d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-SSE-NEXT: orl %ebx, %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andw %r11w, %bx +; CHECK-SSE-NEXT: notl %r11d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: orl %ebx, %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andw %r10w, %bx +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: orl %ebx, %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %ebx, %r9d +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: orl %r9d, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %eax, %r8d +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: orl %r8d, %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: andl %ebp, %ecx +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: orl %ecx, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: andl %ecx, %edx +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %edx, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andl %edx, %esi +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: orl %esi, %edx +; CHECK-SSE-NEXT: movw %r14w, 14(%rdi) +; CHECK-SSE-NEXT: movw %r11w, 12(%rdi) +; CHECK-SSE-NEXT: movw %r10w, 10(%rdi) +; CHECK-SSE-NEXT: movw %bx, 8(%rdi) +; CHECK-SSE-NEXT: movw %ax, 6(%rdi) +; CHECK-SSE-NEXT: movw %bp, 4(%rdi) +; CHECK-SSE-NEXT: movw %cx, 2(%rdi) +; CHECK-SSE-NEXT: movw %dx, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v8i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v8i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v8i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v8i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v8i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v8i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v8i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <8 x i16> %x, %mask + %notmask = xor <8 x i16> %mask, + %my = and <8 x i16> %y, %notmask + %r = or <8 x i16> %mx, %my + ret <8 x i16> %r +} + +define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %ebx, %r8d +; CHECK-BASELINE-NEXT: andl %eax, %ecx +; CHECK-BASELINE-NEXT: andl %r11d, %edx +; CHECK-BASELINE-NEXT: andl %r10d, %esi +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andl %r9d, %r10d +; CHECK-BASELINE-NEXT: orl %esi, %r10d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: orl %r8d, %ebx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: orl %ecx, %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: orl %edx, %r11d +; CHECK-BASELINE-NEXT: movl %ebx, 12(%rdi) +; CHECK-BASELINE-NEXT: movl %eax, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %r11d, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %r10d, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r9d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r8d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %edx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %esi, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm1[0] +; CHECK-SSE-NEXT: andps %xmm3, %xmm4 +; CHECK-SSE-NEXT: andnps %xmm2, %xmm3 +; CHECK-SSE-NEXT: orps %xmm4, %xmm3 +; CHECK-SSE-NEXT: movaps %xmm3, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i32> %x, %mask + %notmask = xor <4 x i32> %mask, + %my = and <4 x i32> %y, %notmask + %r = or <4 x i32> %mx, %my + ret <4 x i32> %r +} + +define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i32_undef: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %eax, %r8d +; CHECK-BASELINE-NEXT: andl %r11d, %edx +; CHECK-BASELINE-NEXT: andl %r10d, %esi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andl %r9d, %r10d +; CHECK-BASELINE-NEXT: orl %esi, %r10d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: orl %r8d, %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: orl %edx, %r11d +; CHECK-BASELINE-NEXT: movl %ecx, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %eax, 12(%rdi) +; CHECK-BASELINE-NEXT: movl %r11d, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %r10d, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i32_undef: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r9d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r8d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %edx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %esi, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm1[0] +; CHECK-SSE-NEXT: andps %xmm3, %xmm4 +; CHECK-SSE-NEXT: andnps %xmm2, %xmm3 +; CHECK-SSE-NEXT: orps %xmm4, %xmm3 +; CHECK-SSE-NEXT: movaps %xmm3, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i32_undef: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i32_undef: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i32_undef: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i32_undef: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i32_undef: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i32_undef: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i32_undef: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i32> %x, %mask + %notmask = xor <4 x i32> %mask, + %my = and <4 x i32> %y, %notmask + %r = or <4 x i32> %mx, %my + ret <4 x i32> %r +} + +define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v2i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: andq %r9, %rsi +; CHECK-BASELINE-NEXT: andq %r8, %rdi +; CHECK-BASELINE-NEXT: notq %r8 +; CHECK-BASELINE-NEXT: notq %r9 +; CHECK-BASELINE-NEXT: andq %rcx, %r9 +; CHECK-BASELINE-NEXT: orq %rsi, %r9 +; CHECK-BASELINE-NEXT: andq %rdx, %r8 +; CHECK-BASELINE-NEXT: orq %rdi, %r8 +; CHECK-BASELINE-NEXT: movq %r8, %rax +; CHECK-BASELINE-NEXT: movq %r9, %rdx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v2i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: andq %r9, %rsi +; CHECK-SSE-NEXT: andq %r8, %rdi +; CHECK-SSE-NEXT: notq %r8 +; CHECK-SSE-NEXT: notq %r9 +; CHECK-SSE-NEXT: andq %rcx, %r9 +; CHECK-SSE-NEXT: orq %rsi, %r9 +; CHECK-SSE-NEXT: andq %rdx, %r8 +; CHECK-SSE-NEXT: orq %rdi, %r8 +; CHECK-SSE-NEXT: movq %r8, %rax +; CHECK-SSE-NEXT: movq %r9, %rdx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v2i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE2-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v2i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm1, %xmm2 +; CHECK-SSE41-NEXT: orps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v2i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v2i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v2i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v2i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v2i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandnps %xmm1, %xmm2, %xmm1 +; CHECK-AVX512VL-NEXT: vorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <2 x i64> %x, %mask + %notmask = xor <2 x i64> %mask, + %my = and <2 x i64> %y, %notmask + %r = or <2 x i64> %mx, %my + ret <2 x i64> %r +} + +; ============================================================================ ; +; 256-bit vector width +; ============================================================================ ; + +define <32 x i8> @out_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v32i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, %r14 +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r15b, %al +; CHECK-BASELINE-NEXT: notb %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: orb %al, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r12b, %al +; CHECK-BASELINE-NEXT: notb %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: orb %al, %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r13b, %al +; CHECK-BASELINE-NEXT: notb %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: orb %al, %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: orb %al, %dl +; CHECK-BASELINE-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: orb %al, %sil +; CHECK-BASELINE-NEXT: movb %sil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dil, %al +; CHECK-BASELINE-NEXT: notb %dil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: orb %al, %dil +; CHECK-BASELINE-NEXT: movb %dil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bpl, %al +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %al, %bpl +; CHECK-BASELINE-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r11b, %al +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %al, %r11b +; CHECK-BASELINE-NEXT: movb %r11b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r10b, %al +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %al, %r10b +; CHECK-BASELINE-NEXT: movb %r10b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r9b, %al +; CHECK-BASELINE-NEXT: notb %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: orb %al, %r9b +; CHECK-BASELINE-NEXT: movb %r9b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r8b, %al +; CHECK-BASELINE-NEXT: notb %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: orb %al, %r8b +; CHECK-BASELINE-NEXT: movb %r8b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %al, %bl +; CHECK-BASELINE-NEXT: movb %bl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movl %esi, %ecx +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movl %ebx, %ecx +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movl %edx, %ecx +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bpl, %al +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %al, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %al, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r11b, %al +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %al, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r10b, %al +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %al, %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r9b, %al +; CHECK-BASELINE-NEXT: notb %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: orb %al, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r8b, %al +; CHECK-BASELINE-NEXT: notb %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: orb %al, %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dil, %al +; CHECK-BASELINE-NEXT: notb %dil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: orb %al, %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: orb %al, %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: orb %al, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %r15b, 31(%r14) +; CHECK-BASELINE-NEXT: movb %r12b, 30(%r14) +; CHECK-BASELINE-NEXT: movb %r13b, 29(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 28(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 27(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 26(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 25(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 24(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 23(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 22(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 21(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 20(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 19(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 18(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 17(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 16(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 15(%r14) +; CHECK-BASELINE-NEXT: movb %bpl, 14(%r14) +; CHECK-BASELINE-NEXT: movb %bl, 13(%r14) +; CHECK-BASELINE-NEXT: movb %r11b, 12(%r14) +; CHECK-BASELINE-NEXT: movb %r10b, 11(%r14) +; CHECK-BASELINE-NEXT: movb %r9b, 10(%r14) +; CHECK-BASELINE-NEXT: movb %r8b, 9(%r14) +; CHECK-BASELINE-NEXT: movb %dil, 8(%r14) +; CHECK-BASELINE-NEXT: movb %sil, 7(%r14) +; CHECK-BASELINE-NEXT: movb %dl, 6(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 5(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %cl, %dl +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %dl, %cl +; CHECK-BASELINE-NEXT: movb %al, 4(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 3(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %cl, %dl +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %dl, %cl +; CHECK-BASELINE-NEXT: movb %al, 2(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 1(%r14) +; CHECK-BASELINE-NEXT: movb %al, (%r14) +; CHECK-BASELINE-NEXT: movq %r14, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v32i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, %r14 +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r15b, %al +; CHECK-SSE-NEXT: notb %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: orb %al, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r12b, %al +; CHECK-SSE-NEXT: notb %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: orb %al, %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r13b, %al +; CHECK-SSE-NEXT: notb %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: orb %al, %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: orb %al, %dl +; CHECK-SSE-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: orb %al, %sil +; CHECK-SSE-NEXT: movb %sil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dil, %al +; CHECK-SSE-NEXT: notb %dil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: orb %al, %dil +; CHECK-SSE-NEXT: movb %dil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bpl, %al +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %al, %bpl +; CHECK-SSE-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r11b, %al +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %al, %r11b +; CHECK-SSE-NEXT: movb %r11b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r10b, %al +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %al, %r10b +; CHECK-SSE-NEXT: movb %r10b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r9b, %al +; CHECK-SSE-NEXT: notb %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: orb %al, %r9b +; CHECK-SSE-NEXT: movb %r9b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r8b, %al +; CHECK-SSE-NEXT: notb %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: orb %al, %r8b +; CHECK-SSE-NEXT: movb %r8b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %al, %bl +; CHECK-SSE-NEXT: movb %bl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movl %esi, %ecx +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movl %ebx, %ecx +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movl %edx, %ecx +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bpl, %al +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %al, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %al, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r11b, %al +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %al, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r10b, %al +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %al, %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r9b, %al +; CHECK-SSE-NEXT: notb %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: orb %al, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r8b, %al +; CHECK-SSE-NEXT: notb %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: orb %al, %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dil, %al +; CHECK-SSE-NEXT: notb %dil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: orb %al, %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: orb %al, %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: orb %al, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %r15b, 31(%r14) +; CHECK-SSE-NEXT: movb %r12b, 30(%r14) +; CHECK-SSE-NEXT: movb %r13b, 29(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 28(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 27(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 26(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 25(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 24(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 23(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 22(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 21(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 20(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 19(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 18(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 17(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 16(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 15(%r14) +; CHECK-SSE-NEXT: movb %bpl, 14(%r14) +; CHECK-SSE-NEXT: movb %bl, 13(%r14) +; CHECK-SSE-NEXT: movb %r11b, 12(%r14) +; CHECK-SSE-NEXT: movb %r10b, 11(%r14) +; CHECK-SSE-NEXT: movb %r9b, 10(%r14) +; CHECK-SSE-NEXT: movb %r8b, 9(%r14) +; CHECK-SSE-NEXT: movb %dil, 8(%r14) +; CHECK-SSE-NEXT: movb %sil, 7(%r14) +; CHECK-SSE-NEXT: movb %dl, 6(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 5(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %cl, %dl +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %dl, %cl +; CHECK-SSE-NEXT: movb %al, 4(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 3(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %cl, %dl +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %dl, %cl +; CHECK-SSE-NEXT: movb %al, 2(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 1(%r14) +; CHECK-SSE-NEXT: movb %al, (%r14) +; CHECK-SSE-NEXT: movq %r14, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v32i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE2-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE2-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v32i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE41-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE41-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v32i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v32i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v32i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v32i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512DQ-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v32i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512VL-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <32 x i8> %x, %mask + %notmask = xor <32 x i8> %mask, + %my = and <32 x i8> %y, %notmask + %r = or <32 x i8> %mx, %my + ret <32 x i8> %r +} + +define <16 x i16> @out_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v16i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, %r11 +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: andw %bp, %r13w +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: orl %r13d, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %bx, %ax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: orl %eax, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r14w, %ax +; CHECK-BASELINE-NEXT: notl %r14d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-BASELINE-NEXT: orl %eax, %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r12w, %ax +; CHECK-BASELINE-NEXT: notl %r12d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-BASELINE-NEXT: orl %eax, %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r15w, %ax +; CHECK-BASELINE-NEXT: notl %r15d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-BASELINE-NEXT: orl %eax, %r15d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %si, %ax +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: orl %eax, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %dx, %ax +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: orl %eax, %edx +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r13w, %ax +; CHECK-BASELINE-NEXT: notl %r13d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-BASELINE-NEXT: orl %eax, %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r10w, %ax +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: orl %eax, %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %di, %ax +; CHECK-BASELINE-NEXT: notl %edi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-BASELINE-NEXT: orl %eax, %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: andl %esi, %r9d +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: orl %r9d, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: andl %r9d, %r8d +; CHECK-BASELINE-NEXT: notl %r9d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-BASELINE-NEXT: orl %r8d, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %r8d, %eax +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: orl %eax, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %edx, %eax +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: orl %eax, %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %eax, %ecx +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: orl %ecx, %eax +; CHECK-BASELINE-NEXT: movw %bp, 30(%r11) +; CHECK-BASELINE-NEXT: movw %bx, 28(%r11) +; CHECK-BASELINE-NEXT: movw %r14w, 26(%r11) +; CHECK-BASELINE-NEXT: movw %r12w, 24(%r11) +; CHECK-BASELINE-NEXT: movw %r15w, 22(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %cx, 20(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %cx, 18(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %cx, 16(%r11) +; CHECK-BASELINE-NEXT: movw %r13w, 14(%r11) +; CHECK-BASELINE-NEXT: movw %r10w, 12(%r11) +; CHECK-BASELINE-NEXT: movw %di, 10(%r11) +; CHECK-BASELINE-NEXT: movw %si, 8(%r11) +; CHECK-BASELINE-NEXT: movw %r9w, 6(%r11) +; CHECK-BASELINE-NEXT: movw %r8w, 4(%r11) +; CHECK-BASELINE-NEXT: movw %dx, 2(%r11) +; CHECK-BASELINE-NEXT: movw %ax, (%r11) +; CHECK-BASELINE-NEXT: movq %r11, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v16i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, %r11 +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: andw %bp, %r13w +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: orl %r13d, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %bx, %ax +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: orl %eax, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r14w, %ax +; CHECK-SSE-NEXT: notl %r14d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-SSE-NEXT: orl %eax, %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r12w, %ax +; CHECK-SSE-NEXT: notl %r12d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-SSE-NEXT: orl %eax, %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r15w, %ax +; CHECK-SSE-NEXT: notl %r15d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-SSE-NEXT: orl %eax, %r15d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %si, %ax +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: orl %eax, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %dx, %ax +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: orl %eax, %edx +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r13w, %ax +; CHECK-SSE-NEXT: notl %r13d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-SSE-NEXT: orl %eax, %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r10w, %ax +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: orl %eax, %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %di, %ax +; CHECK-SSE-NEXT: notl %edi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-SSE-NEXT: orl %eax, %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: andl %esi, %r9d +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: orl %r9d, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: andl %r9d, %r8d +; CHECK-SSE-NEXT: notl %r9d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-SSE-NEXT: orl %r8d, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %r8d, %eax +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: orl %eax, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %edx, %eax +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: orl %eax, %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: andl %eax, %ecx +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: orl %ecx, %eax +; CHECK-SSE-NEXT: movw %bp, 30(%r11) +; CHECK-SSE-NEXT: movw %bx, 28(%r11) +; CHECK-SSE-NEXT: movw %r14w, 26(%r11) +; CHECK-SSE-NEXT: movw %r12w, 24(%r11) +; CHECK-SSE-NEXT: movw %r15w, 22(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: movw %cx, 20(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: movw %cx, 18(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: movw %cx, 16(%r11) +; CHECK-SSE-NEXT: movw %r13w, 14(%r11) +; CHECK-SSE-NEXT: movw %r10w, 12(%r11) +; CHECK-SSE-NEXT: movw %di, 10(%r11) +; CHECK-SSE-NEXT: movw %si, 8(%r11) +; CHECK-SSE-NEXT: movw %r9w, 6(%r11) +; CHECK-SSE-NEXT: movw %r8w, 4(%r11) +; CHECK-SSE-NEXT: movw %dx, 2(%r11) +; CHECK-SSE-NEXT: movw %ax, (%r11) +; CHECK-SSE-NEXT: movq %r11, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v16i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE2-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE2-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v16i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE41-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE41-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v16i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v16i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v16i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v16i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512DQ-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v16i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512VL-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <16 x i16> %x, %mask + %notmask = xor <16 x i16> %mask, + %my = and <16 x i16> %y, %notmask + %r = or <16 x i16> %mx, %my + ret <16 x i16> %r +} + +define <8 x i32> @out_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v8i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %r14d, %ebx +; CHECK-BASELINE-NEXT: notl %r14d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: orl %ebx, %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %r11d, %ebx +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: orl %ebx, %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %r10d, %ebx +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: orl %ebx, %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andl %ebx, %r9d +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: orl %r9d, %ebx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %eax, %r8d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: orl %r8d, %eax +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: andl %ebp, %ecx +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: orl %ecx, %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: andl %ecx, %edx +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: orl %edx, %ecx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andl %edx, %esi +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: orl %esi, %edx +; CHECK-BASELINE-NEXT: movl %r14d, 28(%rdi) +; CHECK-BASELINE-NEXT: movl %r11d, 24(%rdi) +; CHECK-BASELINE-NEXT: movl %r10d, 20(%rdi) +; CHECK-BASELINE-NEXT: movl %ebx, 16(%rdi) +; CHECK-BASELINE-NEXT: movl %eax, 12(%rdi) +; CHECK-BASELINE-NEXT: movl %ebp, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %ecx, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %edx, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v8i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %r14d, %ebx +; CHECK-SSE-NEXT: notl %r14d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: orl %ebx, %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %r11d, %ebx +; CHECK-SSE-NEXT: notl %r11d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: orl %ebx, %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %r10d, %ebx +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: orl %ebx, %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andl %ebx, %r9d +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: orl %r9d, %ebx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %eax, %r8d +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: orl %r8d, %eax +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: andl %ebp, %ecx +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: orl %ecx, %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: andl %ecx, %edx +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: orl %edx, %ecx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andl %edx, %esi +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: orl %esi, %edx +; CHECK-SSE-NEXT: movl %r14d, 28(%rdi) +; CHECK-SSE-NEXT: movl %r11d, 24(%rdi) +; CHECK-SSE-NEXT: movl %r10d, 20(%rdi) +; CHECK-SSE-NEXT: movl %ebx, 16(%rdi) +; CHECK-SSE-NEXT: movl %eax, 12(%rdi) +; CHECK-SSE-NEXT: movl %ebp, 8(%rdi) +; CHECK-SSE-NEXT: movl %ecx, 4(%rdi) +; CHECK-SSE-NEXT: movl %edx, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v8i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE2-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE2-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v8i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE41-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE41-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v8i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v8i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v8i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v8i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512DQ-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v8i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512VL-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <8 x i32> %x, %mask + %notmask = xor <8 x i32> %mask, + %my = and <8 x i32> %y, %notmask + %r = or <8 x i32> %mx, %my + ret <8 x i32> %r +} + +define <4 x i64> @out_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %rbx, %r8 +; CHECK-BASELINE-NEXT: andq %rax, %rcx +; CHECK-BASELINE-NEXT: andq %r11, %rdx +; CHECK-BASELINE-NEXT: andq %r10, %rsi +; CHECK-BASELINE-NEXT: notq %r11 +; CHECK-BASELINE-NEXT: notq %rax +; CHECK-BASELINE-NEXT: notq %rbx +; CHECK-BASELINE-NEXT: notq %r10 +; CHECK-BASELINE-NEXT: andq %r9, %r10 +; CHECK-BASELINE-NEXT: orq %rsi, %r10 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: orq %r8, %rbx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: orq %rcx, %rax +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: orq %rdx, %r11 +; CHECK-BASELINE-NEXT: movq %rbx, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %rax, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %r11, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %r10, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %rbx, %r8 +; CHECK-SSE-NEXT: andq %rax, %rcx +; CHECK-SSE-NEXT: andq %r11, %rdx +; CHECK-SSE-NEXT: andq %r10, %rsi +; CHECK-SSE-NEXT: notq %r11 +; CHECK-SSE-NEXT: notq %rax +; CHECK-SSE-NEXT: notq %rbx +; CHECK-SSE-NEXT: notq %r10 +; CHECK-SSE-NEXT: andq %r9, %r10 +; CHECK-SSE-NEXT: orq %rsi, %r10 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: orq %r8, %rbx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: orq %rcx, %rax +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: orq %rdx, %r11 +; CHECK-SSE-NEXT: movq %rbx, 24(%rdi) +; CHECK-SSE-NEXT: movq %rax, 16(%rdi) +; CHECK-SSE-NEXT: movq %r11, 8(%rdi) +; CHECK-SSE-NEXT: movq %r10, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE2-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE2-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE41-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE41-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512DQ-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512VL-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i64> %x, %mask + %notmask = xor <4 x i64> %mask, + %my = and <4 x i64> %y, %notmask + %r = or <4 x i64> %mx, %my + ret <4 x i64> %r +} + +define <4 x i64> @out_v4i64_undef(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v4i64_undef: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: andq %rax, %r8 +; CHECK-BASELINE-NEXT: andq %r11, %rdx +; CHECK-BASELINE-NEXT: andq %r10, %rsi +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: notq %r11 +; CHECK-BASELINE-NEXT: notq %rax +; CHECK-BASELINE-NEXT: notq %r10 +; CHECK-BASELINE-NEXT: andq %r9, %r10 +; CHECK-BASELINE-NEXT: orq %rsi, %r10 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: orq %r8, %rax +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: orq %rdx, %r11 +; CHECK-BASELINE-NEXT: movq %rcx, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %rax, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %r11, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %r10, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v4i64_undef: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: andq %rax, %r8 +; CHECK-SSE-NEXT: andq %r11, %rdx +; CHECK-SSE-NEXT: andq %r10, %rsi +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: notq %r11 +; CHECK-SSE-NEXT: notq %rax +; CHECK-SSE-NEXT: notq %r10 +; CHECK-SSE-NEXT: andq %r9, %r10 +; CHECK-SSE-NEXT: orq %rsi, %r10 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: orq %r8, %rax +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: orq %rdx, %r11 +; CHECK-SSE-NEXT: movq %rcx, 16(%rdi) +; CHECK-SSE-NEXT: movq %rax, 24(%rdi) +; CHECK-SSE-NEXT: movq %r11, 8(%rdi) +; CHECK-SSE-NEXT: movq %r10, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v4i64_undef: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE2-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE2-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v4i64_undef: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm3, %xmm5 +; CHECK-SSE41-NEXT: orps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm2, %xmm4 +; CHECK-SSE41-NEXT: orps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v4i64_undef: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v4i64_undef: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v4i64_undef: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v4i64_undef: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512DQ-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v4i64_undef: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm1, %ymm2, %ymm1 +; CHECK-AVX512VL-NEXT: vorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <4 x i64> %x, %mask + %notmask = xor <4 x i64> %mask, + %my = and <4 x i64> %y, %notmask + %r = or <4 x i64> %mx, %my + ret <4 x i64> %r +} + +; ============================================================================ ; +; 512-bit vector width +; ============================================================================ ; + +define <64 x i8> @out_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v64i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb %al, %cl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %cl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: orb %al, %dl +; CHECK-BASELINE-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: orb %al, %sil +; CHECK-BASELINE-NEXT: movb %sil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r8b, %al +; CHECK-BASELINE-NEXT: notb %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: orb %al, %r8b +; CHECK-BASELINE-NEXT: movb %r8b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r13b, %al +; CHECK-BASELINE-NEXT: notb %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: orb %al, %r13b +; CHECK-BASELINE-NEXT: movb %r13b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r12b, %al +; CHECK-BASELINE-NEXT: notb %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: orb %al, %r12b +; CHECK-BASELINE-NEXT: movb %r12b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r15b, %al +; CHECK-BASELINE-NEXT: notb %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: orb %al, %r15b +; CHECK-BASELINE-NEXT: movb %r15b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r14b, %al +; CHECK-BASELINE-NEXT: notb %r14b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: orb %al, %r14b +; CHECK-BASELINE-NEXT: movb %r14b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bpl, %al +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %al, %bpl +; CHECK-BASELINE-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r11b, %al +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %al, %r11b +; CHECK-BASELINE-NEXT: movb %r11b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r10b, %al +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %al, %r10b +; CHECK-BASELINE-NEXT: movb %r10b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r9b, %al +; CHECK-BASELINE-NEXT: notb %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: orb %al, %r9b +; CHECK-BASELINE-NEXT: movb %r9b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %al, %bl +; CHECK-BASELINE-NEXT: movb %bl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movl %esi, %ecx +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movl %ebx, %ecx +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movl %edx, %ecx +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r13b, %al +; CHECK-BASELINE-NEXT: notb %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: orb %al, %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r12b, %al +; CHECK-BASELINE-NEXT: notb %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: orb %al, %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r15b, %al +; CHECK-BASELINE-NEXT: notb %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: orb %al, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r14b, %al +; CHECK-BASELINE-NEXT: notb %r14b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: orb %al, %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bpl, %al +; CHECK-BASELINE-NEXT: notb %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: orb %al, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %bl, %al +; CHECK-BASELINE-NEXT: notb %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: orb %al, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r11b, %al +; CHECK-BASELINE-NEXT: notb %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: orb %al, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r10b, %al +; CHECK-BASELINE-NEXT: notb %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: orb %al, %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r9b, %al +; CHECK-BASELINE-NEXT: notb %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: orb %al, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %r8b, %al +; CHECK-BASELINE-NEXT: notb %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: orb %al, %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %sil, %al +; CHECK-BASELINE-NEXT: notb %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: orb %al, %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %dl, %al +; CHECK-BASELINE-NEXT: notb %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: orb %al, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb %cl, %al +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %al, %cl +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 63(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 62(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 61(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 60(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 59(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 58(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 57(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 56(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 55(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 54(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 53(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 52(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 51(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 50(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 49(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 48(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 47(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 46(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 45(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 44(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 43(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 42(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 41(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 40(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 39(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 38(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 37(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 36(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 35(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 34(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 33(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 32(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 31(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 30(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 29(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 28(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 27(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 26(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 25(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 24(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 23(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 22(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 21(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 20(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 19(%rdi) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 18(%rdi) +; CHECK-BASELINE-NEXT: movb %r13b, 17(%rdi) +; CHECK-BASELINE-NEXT: movb %r12b, 16(%rdi) +; CHECK-BASELINE-NEXT: movb %r15b, 15(%rdi) +; CHECK-BASELINE-NEXT: movb %r14b, 14(%rdi) +; CHECK-BASELINE-NEXT: movb %bpl, 13(%rdi) +; CHECK-BASELINE-NEXT: movb %bl, 12(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 11(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, 10(%rdi) +; CHECK-BASELINE-NEXT: movb %r9b, 9(%rdi) +; CHECK-BASELINE-NEXT: movb %r8b, 8(%rdi) +; CHECK-BASELINE-NEXT: movb %sil, 7(%rdi) +; CHECK-BASELINE-NEXT: movb %dl, 6(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 5(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %cl, %dl +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %dl, %cl +; CHECK-BASELINE-NEXT: movb %al, 4(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 3(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %cl, %dl +; CHECK-BASELINE-NEXT: notb %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: orb %dl, %cl +; CHECK-BASELINE-NEXT: movb %al, 2(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: andb %al, %dl +; CHECK-BASELINE-NEXT: notb %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: orb %dl, %al +; CHECK-BASELINE-NEXT: movb %cl, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %al, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v64i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb %al, %cl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %cl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: orb %al, %dl +; CHECK-SSE-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: orb %al, %sil +; CHECK-SSE-NEXT: movb %sil, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r8b, %al +; CHECK-SSE-NEXT: notb %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: orb %al, %r8b +; CHECK-SSE-NEXT: movb %r8b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r13b, %al +; CHECK-SSE-NEXT: notb %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: orb %al, %r13b +; CHECK-SSE-NEXT: movb %r13b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r12b, %al +; CHECK-SSE-NEXT: notb %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: orb %al, %r12b +; CHECK-SSE-NEXT: movb %r12b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r15b, %al +; CHECK-SSE-NEXT: notb %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: orb %al, %r15b +; CHECK-SSE-NEXT: movb %r15b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r14b, %al +; CHECK-SSE-NEXT: notb %r14b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: orb %al, %r14b +; CHECK-SSE-NEXT: movb %r14b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bpl, %al +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %al, %bpl +; CHECK-SSE-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r11b, %al +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %al, %r11b +; CHECK-SSE-NEXT: movb %r11b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r10b, %al +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %al, %r10b +; CHECK-SSE-NEXT: movb %r10b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r9b, %al +; CHECK-SSE-NEXT: notb %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: orb %al, %r9b +; CHECK-SSE-NEXT: movb %r9b, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %al, %bl +; CHECK-SSE-NEXT: movb %bl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movl %esi, %ecx +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movl %ebx, %ecx +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movl %edx, %ecx +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r13b, %al +; CHECK-SSE-NEXT: notb %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: orb %al, %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r12b, %al +; CHECK-SSE-NEXT: notb %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: orb %al, %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r15b, %al +; CHECK-SSE-NEXT: notb %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: orb %al, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r14b, %al +; CHECK-SSE-NEXT: notb %r14b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: orb %al, %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bpl, %al +; CHECK-SSE-NEXT: notb %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: orb %al, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %bl, %al +; CHECK-SSE-NEXT: notb %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: orb %al, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r11b, %al +; CHECK-SSE-NEXT: notb %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: orb %al, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r10b, %al +; CHECK-SSE-NEXT: notb %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: orb %al, %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r9b, %al +; CHECK-SSE-NEXT: notb %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: orb %al, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %r8b, %al +; CHECK-SSE-NEXT: notb %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: orb %al, %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %sil, %al +; CHECK-SSE-NEXT: notb %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: orb %al, %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %dl, %al +; CHECK-SSE-NEXT: notb %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: orb %al, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb %cl, %al +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %al, %cl +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 63(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 62(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 61(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 60(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 59(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 58(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 57(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 56(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 55(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 54(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 53(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 52(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 51(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 50(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 49(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 48(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 47(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 46(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 45(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 44(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 43(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 42(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 41(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 40(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 39(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 38(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 37(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 36(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 35(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 34(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 33(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 32(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 31(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 30(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 29(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 28(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 27(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 26(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 25(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 24(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 23(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 22(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 21(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 20(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 19(%rdi) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 18(%rdi) +; CHECK-SSE-NEXT: movb %r13b, 17(%rdi) +; CHECK-SSE-NEXT: movb %r12b, 16(%rdi) +; CHECK-SSE-NEXT: movb %r15b, 15(%rdi) +; CHECK-SSE-NEXT: movb %r14b, 14(%rdi) +; CHECK-SSE-NEXT: movb %bpl, 13(%rdi) +; CHECK-SSE-NEXT: movb %bl, 12(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 11(%rdi) +; CHECK-SSE-NEXT: movb %r10b, 10(%rdi) +; CHECK-SSE-NEXT: movb %r9b, 9(%rdi) +; CHECK-SSE-NEXT: movb %r8b, 8(%rdi) +; CHECK-SSE-NEXT: movb %sil, 7(%rdi) +; CHECK-SSE-NEXT: movb %dl, 6(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 5(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %cl, %dl +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %dl, %cl +; CHECK-SSE-NEXT: movb %al, 4(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 3(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %cl, %dl +; CHECK-SSE-NEXT: notb %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: orb %dl, %cl +; CHECK-SSE-NEXT: movb %al, 2(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: andb %al, %dl +; CHECK-SSE-NEXT: notb %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: orb %dl, %al +; CHECK-SSE-NEXT: movb %cl, 1(%rdi) +; CHECK-SSE-NEXT: movb %al, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v64i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE2-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE2-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE2-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE2-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE2-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v64i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE41-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE41-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE41-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE41-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE41-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v64i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v64i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v64i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512F-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512F-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v64i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512DQ-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512DQ-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v64i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512VL-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512VL-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <64 x i8> %x, %mask + %notmask = xor <64 x i8> %mask, + %my = and <64 x i8> %y, %notmask + %r = or <64 x i8> %mx, %my + ret <64 x i8> %r +} + +define <32 x i16> @out_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v32i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, %r15 +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: andw %ax, %r13w +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: orl %r13d, %eax +; CHECK-BASELINE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r8w, %ax +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: orl %eax, %r8d +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %bx, %ax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: orl %eax, %ebx +; CHECK-BASELINE-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %bp, %ax +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: orl %eax, %ebp +; CHECK-BASELINE-NEXT: movl %ebp, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %di, %ax +; CHECK-BASELINE-NEXT: notl %edi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-BASELINE-NEXT: orl %eax, %edi +; CHECK-BASELINE-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %si, %ax +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: orl %eax, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %dx, %ax +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: orl %eax, %edx +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %cx, %ax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r13w, %ax +; CHECK-BASELINE-NEXT: notl %r13d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-BASELINE-NEXT: orl %eax, %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r12w, %ax +; CHECK-BASELINE-NEXT: notl %r12d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-BASELINE-NEXT: orl %eax, %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r14w, %ax +; CHECK-BASELINE-NEXT: notl %r14d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-BASELINE-NEXT: orl %eax, %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %bp, %ax +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: orl %eax, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %bx, %ax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: orl %eax, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r11w, %ax +; CHECK-BASELINE-NEXT: notl %r11d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: orl %eax, %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r10w, %ax +; CHECK-BASELINE-NEXT: notl %r10d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: orl %eax, %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw %r9w, %ax +; CHECK-BASELINE-NEXT: notl %r9d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-BASELINE-NEXT: orl %eax, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %r8d, %eax +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: orl %eax, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %edi, %eax +; CHECK-BASELINE-NEXT: notl %edi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-BASELINE-NEXT: orl %eax, %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %esi, %eax +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: orl %eax, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %edx, %eax +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: orl %eax, %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %ecx, %eax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 62(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 60(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 58(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 56(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 54(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 52(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 50(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 48(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 46(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 44(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 42(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 40(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 38(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 36(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 34(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 32(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 30(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 28(%r15) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 26(%r15) +; CHECK-BASELINE-NEXT: movw %r13w, 24(%r15) +; CHECK-BASELINE-NEXT: movw %r12w, 22(%r15) +; CHECK-BASELINE-NEXT: movw %r14w, 20(%r15) +; CHECK-BASELINE-NEXT: movw %bp, 18(%r15) +; CHECK-BASELINE-NEXT: movw %bx, 16(%r15) +; CHECK-BASELINE-NEXT: movw %r11w, 14(%r15) +; CHECK-BASELINE-NEXT: movw %r10w, 12(%r15) +; CHECK-BASELINE-NEXT: movw %r9w, 10(%r15) +; CHECK-BASELINE-NEXT: movw %r8w, 8(%r15) +; CHECK-BASELINE-NEXT: movw %di, 6(%r15) +; CHECK-BASELINE-NEXT: movw %si, 4(%r15) +; CHECK-BASELINE-NEXT: movw %dx, 2(%r15) +; CHECK-BASELINE-NEXT: movw %cx, (%r15) +; CHECK-BASELINE-NEXT: movq %r15, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v32i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, %r15 +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: andw %ax, %r13w +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: orl %r13d, %eax +; CHECK-SSE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r8w, %ax +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: orl %eax, %r8d +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %bx, %ax +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: orl %eax, %ebx +; CHECK-SSE-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %bp, %ax +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: orl %eax, %ebp +; CHECK-SSE-NEXT: movl %ebp, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %di, %ax +; CHECK-SSE-NEXT: notl %edi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-SSE-NEXT: orl %eax, %edi +; CHECK-SSE-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %si, %ax +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: orl %eax, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %dx, %ax +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: orl %eax, %edx +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %cx, %ax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r13w, %ax +; CHECK-SSE-NEXT: notl %r13d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-SSE-NEXT: orl %eax, %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r12w, %ax +; CHECK-SSE-NEXT: notl %r12d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-SSE-NEXT: orl %eax, %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r14w, %ax +; CHECK-SSE-NEXT: notl %r14d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-SSE-NEXT: orl %eax, %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %bp, %ax +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: orl %eax, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %bx, %ax +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: orl %eax, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r11w, %ax +; CHECK-SSE-NEXT: notl %r11d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: orl %eax, %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r10w, %ax +; CHECK-SSE-NEXT: notl %r10d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: orl %eax, %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw %r9w, %ax +; CHECK-SSE-NEXT: notl %r9d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-SSE-NEXT: orl %eax, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %r8d, %eax +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: orl %eax, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %edi, %eax +; CHECK-SSE-NEXT: notl %edi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-SSE-NEXT: orl %eax, %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %esi, %eax +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: orl %eax, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %edx, %eax +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: orl %eax, %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %ecx, %eax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 62(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 60(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 58(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 56(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 54(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 52(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 50(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 48(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 46(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 44(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 42(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 40(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 38(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 36(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 34(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 32(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 30(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 28(%r15) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 26(%r15) +; CHECK-SSE-NEXT: movw %r13w, 24(%r15) +; CHECK-SSE-NEXT: movw %r12w, 22(%r15) +; CHECK-SSE-NEXT: movw %r14w, 20(%r15) +; CHECK-SSE-NEXT: movw %bp, 18(%r15) +; CHECK-SSE-NEXT: movw %bx, 16(%r15) +; CHECK-SSE-NEXT: movw %r11w, 14(%r15) +; CHECK-SSE-NEXT: movw %r10w, 12(%r15) +; CHECK-SSE-NEXT: movw %r9w, 10(%r15) +; CHECK-SSE-NEXT: movw %r8w, 8(%r15) +; CHECK-SSE-NEXT: movw %di, 6(%r15) +; CHECK-SSE-NEXT: movw %si, 4(%r15) +; CHECK-SSE-NEXT: movw %dx, 2(%r15) +; CHECK-SSE-NEXT: movw %cx, (%r15) +; CHECK-SSE-NEXT: movq %r15, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v32i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE2-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE2-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE2-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE2-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE2-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v32i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE41-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE41-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE41-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE41-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE41-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v32i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v32i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v32i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512F-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512F-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v32i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512DQ-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512DQ-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v32i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX512VL-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX512VL-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <32 x i16> %x, %mask + %notmask = xor <32 x i16> %mask, + %my = and <32 x i16> %y, %notmask + %r = or <32 x i16> %mx, %my + ret <32 x i16> %r +} + +define <16 x i32> @out_v16i32(<16 x i32> %x, <16 x i32> %y, <16 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v16i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, %r10d +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, %r11 +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: andl %ebp, %r13d +; CHECK-BASELINE-NEXT: notl %ebp +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: orl %r13d, %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %ebx, %eax +; CHECK-BASELINE-NEXT: notl %ebx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: orl %eax, %ebx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %r14d, %eax +; CHECK-BASELINE-NEXT: notl %r14d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: orl %eax, %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %r12d, %eax +; CHECK-BASELINE-NEXT: notl %r12d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: orl %eax, %r12d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %r15d, %eax +; CHECK-BASELINE-NEXT: notl %r15d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: orl %eax, %r15d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %esi, %eax +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: orl %eax, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %edx, %eax +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: orl %eax, %edx +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %ecx, %eax +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: orl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %r13d, %eax +; CHECK-BASELINE-NEXT: notl %r13d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: orl %eax, %r13d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andl %edi, %eax +; CHECK-BASELINE-NEXT: notl %edi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: orl %eax, %edi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andl %esi, %edx +; CHECK-BASELINE-NEXT: notl %esi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: orl %edx, %esi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andl %edx, %r9d +; CHECK-BASELINE-NEXT: notl %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: orl %r9d, %edx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: andl %r9d, %r8d +; CHECK-BASELINE-NEXT: notl %r9d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: orl %r8d, %r9d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %r8d, %eax +; CHECK-BASELINE-NEXT: notl %r8d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: orl %eax, %r8d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: andl %ecx, %r10d +; CHECK-BASELINE-NEXT: notl %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: orl %r10d, %ecx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %r10d # 4-byte Reload +; CHECK-BASELINE-NEXT: andl %eax, %r10d +; CHECK-BASELINE-NEXT: notl %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: orl %r10d, %eax +; CHECK-BASELINE-NEXT: movl %ebp, 60(%r11) +; CHECK-BASELINE-NEXT: movl %ebx, 56(%r11) +; CHECK-BASELINE-NEXT: movl %r14d, 52(%r11) +; CHECK-BASELINE-NEXT: movl %r12d, 48(%r11) +; CHECK-BASELINE-NEXT: movl %r15d, 44(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %ebp, 40(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %ebp, 36(%r11) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %ebp, 32(%r11) +; CHECK-BASELINE-NEXT: movl %r13d, 28(%r11) +; CHECK-BASELINE-NEXT: movl %edi, 24(%r11) +; CHECK-BASELINE-NEXT: movl %esi, 20(%r11) +; CHECK-BASELINE-NEXT: movl %edx, 16(%r11) +; CHECK-BASELINE-NEXT: movl %r9d, 12(%r11) +; CHECK-BASELINE-NEXT: movl %r8d, 8(%r11) +; CHECK-BASELINE-NEXT: movl %ecx, 4(%r11) +; CHECK-BASELINE-NEXT: movl %eax, (%r11) +; CHECK-BASELINE-NEXT: movq %r11, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v16i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, %r10d +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, %r11 +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: andl %ebp, %r13d +; CHECK-SSE-NEXT: notl %ebp +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: orl %r13d, %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %ebx, %eax +; CHECK-SSE-NEXT: notl %ebx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: orl %eax, %ebx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %r14d, %eax +; CHECK-SSE-NEXT: notl %r14d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: orl %eax, %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %r12d, %eax +; CHECK-SSE-NEXT: notl %r12d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: orl %eax, %r12d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %r15d, %eax +; CHECK-SSE-NEXT: notl %r15d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: orl %eax, %r15d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %esi, %eax +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: orl %eax, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %edx, %eax +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: orl %eax, %edx +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %ecx, %eax +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: orl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %r13d, %eax +; CHECK-SSE-NEXT: notl %r13d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: orl %eax, %r13d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andl %edi, %eax +; CHECK-SSE-NEXT: notl %edi +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: orl %eax, %edi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andl %esi, %edx +; CHECK-SSE-NEXT: notl %esi +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: orl %edx, %esi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andl %edx, %r9d +; CHECK-SSE-NEXT: notl %edx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: orl %r9d, %edx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: andl %r9d, %r8d +; CHECK-SSE-NEXT: notl %r9d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: orl %r8d, %r9d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: andl %r8d, %eax +; CHECK-SSE-NEXT: notl %r8d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: orl %eax, %r8d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: andl %ecx, %r10d +; CHECK-SSE-NEXT: notl %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: orl %r10d, %ecx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %r10d # 4-byte Reload +; CHECK-SSE-NEXT: andl %eax, %r10d +; CHECK-SSE-NEXT: notl %eax +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: orl %r10d, %eax +; CHECK-SSE-NEXT: movl %ebp, 60(%r11) +; CHECK-SSE-NEXT: movl %ebx, 56(%r11) +; CHECK-SSE-NEXT: movl %r14d, 52(%r11) +; CHECK-SSE-NEXT: movl %r12d, 48(%r11) +; CHECK-SSE-NEXT: movl %r15d, 44(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-SSE-NEXT: movl %ebp, 40(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-SSE-NEXT: movl %ebp, 36(%r11) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Reload +; CHECK-SSE-NEXT: movl %ebp, 32(%r11) +; CHECK-SSE-NEXT: movl %r13d, 28(%r11) +; CHECK-SSE-NEXT: movl %edi, 24(%r11) +; CHECK-SSE-NEXT: movl %esi, 20(%r11) +; CHECK-SSE-NEXT: movl %edx, 16(%r11) +; CHECK-SSE-NEXT: movl %r9d, 12(%r11) +; CHECK-SSE-NEXT: movl %r8d, 8(%r11) +; CHECK-SSE-NEXT: movl %ecx, 4(%r11) +; CHECK-SSE-NEXT: movl %eax, (%r11) +; CHECK-SSE-NEXT: movq %r11, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v16i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE2-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE2-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE2-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE2-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE2-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v16i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE41-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE41-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE41-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE41-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE41-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v16i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v16i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v16i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vpandq %zmm2, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpandnq %zmm1, %zmm2, %zmm1 +; CHECK-AVX512F-NEXT: vporq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v16i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512DQ-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v16i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512VL-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <16 x i32> %x, %mask + %notmask = xor <16 x i32> %mask, + %my = and <16 x i32> %y, %notmask + %r = or <16 x i32> %mx, %my + ret <16 x i32> %r +} + +define <8 x i64> @out_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v8i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %r14, %rbx +; CHECK-BASELINE-NEXT: notq %r14 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: orq %rbx, %r14 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %r11, %rbx +; CHECK-BASELINE-NEXT: notq %r11 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: orq %rbx, %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %r10, %rbx +; CHECK-BASELINE-NEXT: notq %r10 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: orq %rbx, %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; CHECK-BASELINE-NEXT: andq %r15, %r9 +; CHECK-BASELINE-NEXT: notq %r15 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r15 +; CHECK-BASELINE-NEXT: orq %r9, %r15 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: andq %rax, %r8 +; CHECK-BASELINE-NEXT: notq %rax +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: orq %r8, %rax +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %rbx, %rcx +; CHECK-BASELINE-NEXT: notq %rbx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: orq %rcx, %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: andq %rcx, %rdx +; CHECK-BASELINE-NEXT: notq %rcx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: orq %rdx, %rcx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: andq %rdx, %rsi +; CHECK-BASELINE-NEXT: notq %rdx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: orq %rsi, %rdx +; CHECK-BASELINE-NEXT: movq %r14, 56(%rdi) +; CHECK-BASELINE-NEXT: movq %r11, 48(%rdi) +; CHECK-BASELINE-NEXT: movq %r10, 40(%rdi) +; CHECK-BASELINE-NEXT: movq %r15, 32(%rdi) +; CHECK-BASELINE-NEXT: movq %rax, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %rbx, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %rcx, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %rdx, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v8i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %r14, %rbx +; CHECK-SSE-NEXT: notq %r14 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: orq %rbx, %r14 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %r11, %rbx +; CHECK-SSE-NEXT: notq %r11 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: orq %rbx, %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %r10, %rbx +; CHECK-SSE-NEXT: notq %r10 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: orq %rbx, %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; CHECK-SSE-NEXT: andq %r15, %r9 +; CHECK-SSE-NEXT: notq %r15 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r15 +; CHECK-SSE-NEXT: orq %r9, %r15 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: andq %rax, %r8 +; CHECK-SSE-NEXT: notq %rax +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: orq %r8, %rax +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %rbx, %rcx +; CHECK-SSE-NEXT: notq %rbx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: orq %rcx, %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: andq %rcx, %rdx +; CHECK-SSE-NEXT: notq %rcx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: orq %rdx, %rcx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: andq %rdx, %rsi +; CHECK-SSE-NEXT: notq %rdx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: orq %rsi, %rdx +; CHECK-SSE-NEXT: movq %r14, 56(%rdi) +; CHECK-SSE-NEXT: movq %r11, 48(%rdi) +; CHECK-SSE-NEXT: movq %r10, 40(%rdi) +; CHECK-SSE-NEXT: movq %r15, 32(%rdi) +; CHECK-SSE-NEXT: movq %rax, 24(%rdi) +; CHECK-SSE-NEXT: movq %rbx, 16(%rdi) +; CHECK-SSE-NEXT: movq %rcx, 8(%rdi) +; CHECK-SSE-NEXT: movq %rdx, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v8i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE2-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE2-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE2-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE2-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE2-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v8i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE41-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE41-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE41-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE41-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE41-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v8i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v8i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v8i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vpandq %zmm2, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpandnq %zmm1, %zmm2, %zmm1 +; CHECK-AVX512F-NEXT: vporq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v8i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512DQ-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v8i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512VL-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <8 x i64> %x, %mask + %notmask = xor <8 x i64> %mask, + %my = and <8 x i64> %y, %notmask + %r = or <8 x i64> %mx, %my + ret <8 x i64> %r +} + +define <8 x i64> @out_v8i64_undef(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: out_v8i64_undef: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: andq %r14, %r11 +; CHECK-BASELINE-NEXT: notq %r14 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: orq %r11, %r14 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: andq %r10, %rax +; CHECK-BASELINE-NEXT: notq %r10 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: orq %rax, %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: andq %r11, %r9 +; CHECK-BASELINE-NEXT: notq %r11 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: orq %r9, %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: andq %rbx, %r8 +; CHECK-BASELINE-NEXT: notq %rbx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: orq %r8, %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: andq %rax, %rcx +; CHECK-BASELINE-NEXT: notq %rax +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: orq %rcx, %rax +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: andq %rcx, %rdx +; CHECK-BASELINE-NEXT: notq %rcx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: orq %rdx, %rcx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: andq %rdx, %rsi +; CHECK-BASELINE-NEXT: notq %rdx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: orq %rsi, %rdx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rsi +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-BASELINE-NEXT: movq %rsi, 48(%rdi) +; CHECK-BASELINE-NEXT: movq %r14, 56(%rdi) +; CHECK-BASELINE-NEXT: movq %r10, 40(%rdi) +; CHECK-BASELINE-NEXT: movq %r11, 32(%rdi) +; CHECK-BASELINE-NEXT: movq %rbx, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %rax, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %rcx, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %rdx, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: out_v8i64_undef: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: andq %r14, %r11 +; CHECK-SSE-NEXT: notq %r14 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: orq %r11, %r14 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: andq %r10, %rax +; CHECK-SSE-NEXT: notq %r10 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: orq %rax, %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: andq %r11, %r9 +; CHECK-SSE-NEXT: notq %r11 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: orq %r9, %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: andq %rbx, %r8 +; CHECK-SSE-NEXT: notq %rbx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: orq %r8, %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: andq %rax, %rcx +; CHECK-SSE-NEXT: notq %rax +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: orq %rcx, %rax +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: andq %rcx, %rdx +; CHECK-SSE-NEXT: notq %rcx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: orq %rdx, %rcx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: andq %rdx, %rsi +; CHECK-SSE-NEXT: notq %rdx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: orq %rsi, %rdx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rsi +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-SSE-NEXT: movq %rsi, 48(%rdi) +; CHECK-SSE-NEXT: movq %r14, 56(%rdi) +; CHECK-SSE-NEXT: movq %r10, 40(%rdi) +; CHECK-SSE-NEXT: movq %r11, 32(%rdi) +; CHECK-SSE-NEXT: movq %rbx, 24(%rdi) +; CHECK-SSE-NEXT: movq %rax, 16(%rdi) +; CHECK-SSE-NEXT: movq %rcx, 8(%rdi) +; CHECK-SSE-NEXT: movq %rdx, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: out_v8i64_undef: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE2-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE2-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE2-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE2-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE2-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE2-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE2-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE2-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE2-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: out_v8i64_undef: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm8 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm9 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm10 +; CHECK-SSE41-NEXT: movaps {{[0-9]+}}(%rsp), %xmm11 +; CHECK-SSE41-NEXT: andps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: andnps %xmm7, %xmm11 +; CHECK-SSE41-NEXT: orps %xmm11, %xmm3 +; CHECK-SSE41-NEXT: andnps %xmm6, %xmm10 +; CHECK-SSE41-NEXT: orps %xmm10, %xmm2 +; CHECK-SSE41-NEXT: andnps %xmm5, %xmm9 +; CHECK-SSE41-NEXT: orps %xmm9, %xmm1 +; CHECK-SSE41-NEXT: andnps %xmm4, %xmm8 +; CHECK-SSE41-NEXT: orps %xmm8, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: out_v8i64_undef: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: out_v8i64_undef: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandnps %ymm3, %ymm5, %ymm3 +; CHECK-AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2 +; CHECK-AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: out_v8i64_undef: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vpandq %zmm2, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpandnq %zmm1, %zmm2, %zmm1 +; CHECK-AVX512F-NEXT: vporq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: out_v8i64_undef: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512DQ-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: out_v8i64_undef: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vandnps %zmm1, %zmm2, %zmm1 +; CHECK-AVX512VL-NEXT: vorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: retq + %mx = and <8 x i64> %x, %mask + %notmask = xor <8 x i64> %mask, + %my = and <8 x i64> %y, %notmask + %r = or <8 x i64> %mx, %my + ret <8 x i64> %r +} + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Should be the same as the previous one. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; ============================================================================ ; +; 8-bit vector width +; ============================================================================ ; + +define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v1i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v1i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v1i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: movl %edi, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v1i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: movl %edi, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v1i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: movl %edi, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v1i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: movl %edi, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v1i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: movl %edi, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v1i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: movl %edi, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v1i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: movl %edi, %eax +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <1 x i8> %x, %y + %n1 = and <1 x i8> %n0, %mask + %r = xor <1 x i8> %n1, %y + ret <1 x i8> %r +} + +; ============================================================================ ; +; 16-bit vector width +; ============================================================================ ; + +define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v2i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: movl %esi, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v2i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: movl %esi, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v2i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v2i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v2i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v2i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v2i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v2i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v2i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <2 x i8> %x, %y + %n1 = and <2 x i8> %n0, %mask + %r = xor <2 x i8> %n1, %y + ret <2 x i8> %r +} + +define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v1i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v1i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v1i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: movl %edi, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v1i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: movl %edi, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v1i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: movl %edi, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v1i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: movl %edi, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v1i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: movl %edi, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v1i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: movl %edi, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v1i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: movl %edi, %eax +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <1 x i16> %x, %y + %n1 = and <1 x i16> %n0, %mask + %r = xor <1 x i16> %n1, %y + ret <1 x i16> %r +} + +; ============================================================================ ; +; 32-bit vector width +; ============================================================================ ; + +define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v4i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %r9d, %esi +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: xorb %r11b, %cl +; CHECK-BASELINE-NEXT: xorb %r10b, %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %r9b, %sil +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: xorb %r11b, %cl +; CHECK-BASELINE-NEXT: xorb %r10b, %r8b +; CHECK-BASELINE-NEXT: movb %r8b, 3(%rdi) +; CHECK-BASELINE-NEXT: movb %cl, 2(%rdi) +; CHECK-BASELINE-NEXT: movb %dl, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %sil, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v4i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %r9d, %esi +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: xorb %r11b, %cl +; CHECK-SSE-NEXT: xorb %r10b, %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %r9b, %sil +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: xorb %r11b, %cl +; CHECK-SSE-NEXT: xorb %r10b, %r8b +; CHECK-SSE-NEXT: movb %r8b, 3(%rdi) +; CHECK-SSE-NEXT: movb %cl, 2(%rdi) +; CHECK-SSE-NEXT: movb %dl, 1(%rdi) +; CHECK-SSE-NEXT: movb %sil, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v4i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v4i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v4i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v4i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v4i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v4i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v4i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <4 x i8> %x, %y + %n1 = and <4 x i8> %n0, %mask + %r = xor <4 x i8> %n1, %y + ret <4 x i8> %r +} + +define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v2i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: movl %esi, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v2i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: movl %esi, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v2i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v2i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v2i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v2i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v2i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v2i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v2i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <2 x i16> %x, %y + %n1 = and <2 x i16> %n0, %mask + %r = xor <2 x i16> %n1, %y + ret <2 x i16> %r +} + +define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v1i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: andl %edx, %edi +; CHECK-BASELINE-NEXT: xorl %esi, %edi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v1i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: andl %edx, %edi +; CHECK-SSE-NEXT: xorl %esi, %edi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v1i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: andl %edx, %edi +; CHECK-SSE2-NEXT: xorl %esi, %edi +; CHECK-SSE2-NEXT: movl %edi, %eax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v1i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: andl %edx, %edi +; CHECK-SSE41-NEXT: xorl %esi, %edi +; CHECK-SSE41-NEXT: movl %edi, %eax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v1i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: andl %edx, %edi +; CHECK-AVX-NEXT: xorl %esi, %edi +; CHECK-AVX-NEXT: movl %edi, %eax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v1i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: andl %edx, %edi +; CHECK-AVX2-NEXT: xorl %esi, %edi +; CHECK-AVX2-NEXT: movl %edi, %eax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v1i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: andl %edx, %edi +; CHECK-AVX512F-NEXT: xorl %esi, %edi +; CHECK-AVX512F-NEXT: movl %edi, %eax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v1i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: andl %edx, %edi +; CHECK-AVX512DQ-NEXT: xorl %esi, %edi +; CHECK-AVX512DQ-NEXT: movl %edi, %eax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v1i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: andl %edx, %edi +; CHECK-AVX512VL-NEXT: xorl %esi, %edi +; CHECK-AVX512VL-NEXT: movl %edi, %eax +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <1 x i32> %x, %y + %n1 = and <1 x i32> %n0, %mask + %r = xor <1 x i32> %n1, %y + ret <1 x i32> %r +} + +; ============================================================================ ; +; 64-bit vector width +; ============================================================================ ; + +define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v8i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %ecx, %r10d +; CHECK-BASELINE-NEXT: movl %edx, %r11d +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %bpl, %sil +; CHECK-BASELINE-NEXT: xorb %r13b, %r11b +; CHECK-BASELINE-NEXT: xorb %r12b, %r10b +; CHECK-BASELINE-NEXT: xorb %r15b, %r8b +; CHECK-BASELINE-NEXT: xorb %r14b, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %bpl, %sil +; CHECK-BASELINE-NEXT: xorb %r13b, %r11b +; CHECK-BASELINE-NEXT: xorb %r12b, %r10b +; CHECK-BASELINE-NEXT: xorb %r15b, %r8b +; CHECK-BASELINE-NEXT: xorb %r14b, %r9b +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: movb %al, 7(%rdi) +; CHECK-BASELINE-NEXT: movb %cl, 6(%rdi) +; CHECK-BASELINE-NEXT: movb %dl, 5(%rdi) +; CHECK-BASELINE-NEXT: movb %r9b, 4(%rdi) +; CHECK-BASELINE-NEXT: movb %r8b, 3(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, 2(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 1(%rdi) +; CHECK-BASELINE-NEXT: movb %sil, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v8i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %ecx, %r10d +; CHECK-SSE-NEXT: movl %edx, %r11d +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %bpl, %sil +; CHECK-SSE-NEXT: xorb %r13b, %r11b +; CHECK-SSE-NEXT: xorb %r12b, %r10b +; CHECK-SSE-NEXT: xorb %r15b, %r8b +; CHECK-SSE-NEXT: xorb %r14b, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %bpl, %sil +; CHECK-SSE-NEXT: xorb %r13b, %r11b +; CHECK-SSE-NEXT: xorb %r12b, %r10b +; CHECK-SSE-NEXT: xorb %r15b, %r8b +; CHECK-SSE-NEXT: xorb %r14b, %r9b +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: movb %al, 7(%rdi) +; CHECK-SSE-NEXT: movb %cl, 6(%rdi) +; CHECK-SSE-NEXT: movb %dl, 5(%rdi) +; CHECK-SSE-NEXT: movb %r9b, 4(%rdi) +; CHECK-SSE-NEXT: movb %r8b, 3(%rdi) +; CHECK-SSE-NEXT: movb %r10b, 2(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 1(%rdi) +; CHECK-SSE-NEXT: movb %sil, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v8i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v8i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v8i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v8i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v8i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v8i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v8i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <8 x i8> %x, %y + %n1 = and <8 x i8> %n0, %mask + %r = xor <8 x i8> %n1, %y + ret <8 x i8> %r +} + +define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v4i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: xorl %r10d, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorl %r11d, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: xorl %r9d, %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %r9d, %esi +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: xorl %r11d, %ecx +; CHECK-BASELINE-NEXT: xorl %r10d, %r8d +; CHECK-BASELINE-NEXT: movw %r8w, 6(%rdi) +; CHECK-BASELINE-NEXT: movw %cx, 4(%rdi) +; CHECK-BASELINE-NEXT: movw %dx, 2(%rdi) +; CHECK-BASELINE-NEXT: movw %si, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v4i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: xorl %r10d, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorl %r11d, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %edx +; CHECK-SSE-NEXT: xorl %r9d, %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %r9d, %esi +; CHECK-SSE-NEXT: xorl %eax, %edx +; CHECK-SSE-NEXT: xorl %r11d, %ecx +; CHECK-SSE-NEXT: xorl %r10d, %r8d +; CHECK-SSE-NEXT: movw %r8w, 6(%rdi) +; CHECK-SSE-NEXT: movw %cx, 4(%rdi) +; CHECK-SSE-NEXT: movw %dx, 2(%rdi) +; CHECK-SSE-NEXT: movw %si, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v4i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v4i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v4i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v4i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v4i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v4i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v4i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <4 x i16> %x, %y + %n1 = and <4 x i16> %n0, %mask + %r = xor <4 x i16> %n1, %y + ret <4 x i16> %r +} + +define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v2i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: andl %r9d, %esi +; CHECK-BASELINE-NEXT: andl %r8d, %edi +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: xorl %ecx, %esi +; CHECK-BASELINE-NEXT: movl %edi, %eax +; CHECK-BASELINE-NEXT: movl %esi, %edx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v2i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: andl %r9d, %esi +; CHECK-SSE-NEXT: andl %r8d, %edi +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: xorl %ecx, %esi +; CHECK-SSE-NEXT: movl %edi, %eax +; CHECK-SSE-NEXT: movl %esi, %edx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v2i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v2i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v2i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v2i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v2i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v2i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v2i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <2 x i32> %x, %y + %n1 = and <2 x i32> %n0, %mask + %r = xor <2 x i32> %n1, %y + ret <2 x i32> %r +} + +define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v1i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorq %rsi, %rdi +; CHECK-BASELINE-NEXT: andq %rdx, %rdi +; CHECK-BASELINE-NEXT: xorq %rsi, %rdi +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v1i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorq %rsi, %rdi +; CHECK-SSE-NEXT: andq %rdx, %rdi +; CHECK-SSE-NEXT: xorq %rsi, %rdi +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v1i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorq %rsi, %rdi +; CHECK-SSE2-NEXT: andq %rdx, %rdi +; CHECK-SSE2-NEXT: xorq %rsi, %rdi +; CHECK-SSE2-NEXT: movq %rdi, %rax +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v1i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorq %rsi, %rdi +; CHECK-SSE41-NEXT: andq %rdx, %rdi +; CHECK-SSE41-NEXT: xorq %rsi, %rdi +; CHECK-SSE41-NEXT: movq %rdi, %rax +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v1i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: xorq %rsi, %rdi +; CHECK-AVX-NEXT: andq %rdx, %rdi +; CHECK-AVX-NEXT: xorq %rsi, %rdi +; CHECK-AVX-NEXT: movq %rdi, %rax +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v1i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: xorq %rsi, %rdi +; CHECK-AVX2-NEXT: andq %rdx, %rdi +; CHECK-AVX2-NEXT: xorq %rsi, %rdi +; CHECK-AVX2-NEXT: movq %rdi, %rax +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v1i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: xorq %rsi, %rdi +; CHECK-AVX512F-NEXT: andq %rdx, %rdi +; CHECK-AVX512F-NEXT: xorq %rsi, %rdi +; CHECK-AVX512F-NEXT: movq %rdi, %rax +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v1i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: xorq %rsi, %rdi +; CHECK-AVX512DQ-NEXT: andq %rdx, %rdi +; CHECK-AVX512DQ-NEXT: xorq %rsi, %rdi +; CHECK-AVX512DQ-NEXT: movq %rdi, %rax +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v1i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: xorq %rsi, %rdi +; CHECK-AVX512VL-NEXT: andq %rdx, %rdi +; CHECK-AVX512VL-NEXT: xorq %rsi, %rdi +; CHECK-AVX512VL-NEXT: movq %rdi, %rax +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <1 x i64> %x, %y + %n1 = and <1 x i64> %n0, %mask + %r = xor <1 x i64> %n1, %y + ret <1 x i64> %r +} + +; ============================================================================ ; +; 128-bit vector width +; ============================================================================ ; + +define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v16i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %r10b, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %r10b, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %r11b, %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %r11b, %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %bl, %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %bl, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %bpl, %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %bpl, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %r13b, %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %r13b, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb %r12b, %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb %r12b, %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: xorb %r15b, %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: xorb %r15b, %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: xorb %r14b, %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: xorb %r14b, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: xorb %sil, %r14b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: xorb %sil, %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %sil, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %sil, %cl +; CHECK-BASELINE-NEXT: movb %cl, 15(%rdi) +; CHECK-BASELINE-NEXT: movb %al, 14(%rdi) +; CHECK-BASELINE-NEXT: movb %r14b, 13(%rdi) +; CHECK-BASELINE-NEXT: movb %r15b, 12(%rdi) +; CHECK-BASELINE-NEXT: movb %r12b, 11(%rdi) +; CHECK-BASELINE-NEXT: movb %r13b, 10(%rdi) +; CHECK-BASELINE-NEXT: movb %bpl, 9(%rdi) +; CHECK-BASELINE-NEXT: movb %bl, 8(%rdi) +; CHECK-BASELINE-NEXT: movb %r11b, 7(%rdi) +; CHECK-BASELINE-NEXT: movb %r10b, 6(%rdi) +; CHECK-BASELINE-NEXT: movb %dl, 5(%rdi) +; CHECK-BASELINE-NEXT: movb %r9b, 4(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: movb %r8b, 3(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, 2(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, 1(%rdi) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v16i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %r10b, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %r10b, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %r11b, %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %r11b, %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %bl, %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %bl, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %bpl, %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %bpl, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %r13b, %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %r13b, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb %r12b, %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb %r12b, %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: xorb %r15b, %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: xorb %r15b, %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: xorb %r14b, %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: xorb %r14b, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: xorb %sil, %r14b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: xorb %sil, %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %sil, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %sil, %cl +; CHECK-SSE-NEXT: movb %cl, 15(%rdi) +; CHECK-SSE-NEXT: movb %al, 14(%rdi) +; CHECK-SSE-NEXT: movb %r14b, 13(%rdi) +; CHECK-SSE-NEXT: movb %r15b, 12(%rdi) +; CHECK-SSE-NEXT: movb %r12b, 11(%rdi) +; CHECK-SSE-NEXT: movb %r13b, 10(%rdi) +; CHECK-SSE-NEXT: movb %bpl, 9(%rdi) +; CHECK-SSE-NEXT: movb %bl, 8(%rdi) +; CHECK-SSE-NEXT: movb %r11b, 7(%rdi) +; CHECK-SSE-NEXT: movb %r10b, 6(%rdi) +; CHECK-SSE-NEXT: movb %dl, 5(%rdi) +; CHECK-SSE-NEXT: movb %r9b, 4(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: movb %r8b, 3(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, 2(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, 1(%rdi) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v16i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v16i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v16i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v16i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v16i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v16i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v16i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <16 x i8> %x, %y + %n1 = and <16 x i8> %n0, %mask + %r = xor <16 x i8> %n1, %y + ret <16 x i8> %r +} + +define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v8i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: xorl %r10d, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorl %r11d, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %ebx, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: xorl %ebx, %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: xorl %r11d, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-BASELINE-NEXT: xorl %r10d, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorw %bx, %bp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: xorl %ebx, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorw %ax, %bx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: xorl %eax, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %r14w, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %r14d, %eax +; CHECK-BASELINE-NEXT: movw %ax, 14(%rdi) +; CHECK-BASELINE-NEXT: movw %bx, 12(%rdi) +; CHECK-BASELINE-NEXT: movw %bp, 10(%rdi) +; CHECK-BASELINE-NEXT: movw %r9w, 8(%rdi) +; CHECK-BASELINE-NEXT: movw %r8w, 6(%rdi) +; CHECK-BASELINE-NEXT: movw %cx, 4(%rdi) +; CHECK-BASELINE-NEXT: movw %dx, 2(%rdi) +; CHECK-BASELINE-NEXT: movw %si, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v8i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: xorl %r10d, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorl %r11d, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %ebx, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: xorl %ebx, %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: xorl %r11d, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-SSE-NEXT: xorl %r10d, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorw %bx, %bp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: xorl %ebx, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorw %ax, %bx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: xorl %eax, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %r14w, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %r14d, %eax +; CHECK-SSE-NEXT: movw %ax, 14(%rdi) +; CHECK-SSE-NEXT: movw %bx, 12(%rdi) +; CHECK-SSE-NEXT: movw %bp, 10(%rdi) +; CHECK-SSE-NEXT: movw %r9w, 8(%rdi) +; CHECK-SSE-NEXT: movw %r8w, 6(%rdi) +; CHECK-SSE-NEXT: movw %cx, 4(%rdi) +; CHECK-SSE-NEXT: movw %dx, 2(%rdi) +; CHECK-SSE-NEXT: movw %si, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v8i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v8i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v8i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v8i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v8i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v8i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v8i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <8 x i16> %x, %y + %n1 = and <8 x i16> %n0, %mask + %r = xor <8 x i16> %n1, %y + ret <8 x i16> %r +} + +define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v4i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %r9d, %esi +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: xorl %r11d, %ecx +; CHECK-BASELINE-NEXT: xorl %r10d, %r8d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorl %r9d, %esi +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: xorl %r11d, %ecx +; CHECK-BASELINE-NEXT: xorl %r10d, %r8d +; CHECK-BASELINE-NEXT: movl %r8d, 12(%rdi) +; CHECK-BASELINE-NEXT: movl %ecx, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %edx, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %esi, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v4i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r9d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %r8d, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %edx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movl %esi, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero +; CHECK-SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1] +; CHECK-SSE-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm1[0] +; CHECK-SSE-NEXT: xorps %xmm3, %xmm4 +; CHECK-SSE-NEXT: andps %xmm2, %xmm4 +; CHECK-SSE-NEXT: xorps %xmm3, %xmm4 +; CHECK-SSE-NEXT: movaps %xmm4, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v4i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v4i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v4i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v4i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v4i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v4i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v4i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <4 x i32> %x, %y + %n1 = and <4 x i32> %n0, %mask + %r = xor <4 x i32> %n1, %y + ret <4 x i32> %r +} + +define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v2i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: xorq %rdx, %rdi +; CHECK-BASELINE-NEXT: xorq %rcx, %rsi +; CHECK-BASELINE-NEXT: andq %r9, %rsi +; CHECK-BASELINE-NEXT: andq %r8, %rdi +; CHECK-BASELINE-NEXT: xorq %rdx, %rdi +; CHECK-BASELINE-NEXT: xorq %rcx, %rsi +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: movq %rsi, %rdx +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v2i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: xorq %rdx, %rdi +; CHECK-SSE-NEXT: xorq %rcx, %rsi +; CHECK-SSE-NEXT: andq %r9, %rsi +; CHECK-SSE-NEXT: andq %r8, %rdi +; CHECK-SSE-NEXT: xorq %rdx, %rdi +; CHECK-SSE-NEXT: xorq %rcx, %rsi +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: movq %rsi, %rdx +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v2i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v2i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm1, %xmm0 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v2i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v2i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v2i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v2i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v2i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vandps %xmm2, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vxorps %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <2 x i64> %x, %y + %n1 = and <2 x i64> %n0, %mask + %r = xor <2 x i64> %n1, %y + ret <2 x i64> %r +} + +; ============================================================================ ; +; 256-bit vector width +; ============================================================================ ; + +define <32 x i8> @in_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v32i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %sil, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %sil, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bpl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bpl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dil, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dil, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r8b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r8b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r10b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r10b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r12b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r12b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: xorb %r15b, %r12b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-BASELINE-NEXT: xorb %r15b, %r12b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: xorb %al, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %r13b, %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %r13b, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %r11b, %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %r11b, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %al, %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %al, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %al, %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %al, %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: xorb %al, %dil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: xorb %al, %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %al, %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %al, %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r14b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r14b, %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb %r14b, %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb %r14b, %r13b +; CHECK-BASELINE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload +; CHECK-BASELINE-NEXT: movb %r13b, 31(%r14) +; CHECK-BASELINE-NEXT: movb %al, 30(%r14) +; CHECK-BASELINE-NEXT: movb %cl, 29(%r14) +; CHECK-BASELINE-NEXT: movb %dl, 28(%r14) +; CHECK-BASELINE-NEXT: movb %sil, 27(%r14) +; CHECK-BASELINE-NEXT: movb %dil, 26(%r14) +; CHECK-BASELINE-NEXT: movb %r8b, 25(%r14) +; CHECK-BASELINE-NEXT: movb %r9b, 24(%r14) +; CHECK-BASELINE-NEXT: movb %r10b, 23(%r14) +; CHECK-BASELINE-NEXT: movb %r11b, 22(%r14) +; CHECK-BASELINE-NEXT: movb %bl, 21(%r14) +; CHECK-BASELINE-NEXT: movb %bpl, 20(%r14) +; CHECK-BASELINE-NEXT: movb %r15b, 19(%r14) +; CHECK-BASELINE-NEXT: movb %r12b, 18(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 17(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 16(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 15(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 14(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 13(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 12(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 11(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 10(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 9(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 8(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 7(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 6(%r14) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 5(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 4(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: movb %dl, 3(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: movb %dl, 2(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %cl, %dl +; CHECK-BASELINE-NEXT: movb %dl, 1(%r14) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %dl, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %dl, %cl +; CHECK-BASELINE-NEXT: movb %cl, (%r14) +; CHECK-BASELINE-NEXT: movq %r14, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v32i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %sil, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %sil, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bpl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bpl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dil, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dil, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r8b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r8b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r10b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r10b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r12b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r12b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: xorb %r15b, %r12b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r12b +; CHECK-SSE-NEXT: xorb %r15b, %r12b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: xorb %al, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %r13b, %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %r13b, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %r11b, %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %r11b, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %al, %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %al, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %al, %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %al, %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: xorb %al, %dil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: xorb %al, %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %al, %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %al, %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r14b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r14b, %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb %r14b, %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb %r14b, %r13b +; CHECK-SSE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload +; CHECK-SSE-NEXT: movb %r13b, 31(%r14) +; CHECK-SSE-NEXT: movb %al, 30(%r14) +; CHECK-SSE-NEXT: movb %cl, 29(%r14) +; CHECK-SSE-NEXT: movb %dl, 28(%r14) +; CHECK-SSE-NEXT: movb %sil, 27(%r14) +; CHECK-SSE-NEXT: movb %dil, 26(%r14) +; CHECK-SSE-NEXT: movb %r8b, 25(%r14) +; CHECK-SSE-NEXT: movb %r9b, 24(%r14) +; CHECK-SSE-NEXT: movb %r10b, 23(%r14) +; CHECK-SSE-NEXT: movb %r11b, 22(%r14) +; CHECK-SSE-NEXT: movb %bl, 21(%r14) +; CHECK-SSE-NEXT: movb %bpl, 20(%r14) +; CHECK-SSE-NEXT: movb %r15b, 19(%r14) +; CHECK-SSE-NEXT: movb %r12b, 18(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 17(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 16(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 15(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 14(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 13(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 12(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 11(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 10(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 9(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 8(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 7(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 6(%r14) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 5(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movb %al, 4(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: movb %dl, 3(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: movb %dl, 2(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %cl, %dl +; CHECK-SSE-NEXT: movb %dl, 1(%r14) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %dl, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %dl, %cl +; CHECK-SSE-NEXT: movb %cl, (%r14) +; CHECK-SSE-NEXT: movq %r14, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v32i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v32i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v32i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v32i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v32i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v32i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v32i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <32 x i8> %x, %y + %n1 = and <32 x i8> %n0, %mask + %r = xor <32 x i8> %n1, %y + ret <32 x i8> %r +} + +define <16 x i16> @in_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v16i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r8d, %ebp +; CHECK-BASELINE-NEXT: movl %edx, %ebx +; CHECK-BASELINE-NEXT: movq %rdi, %r8 +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorl %r11d, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: xorl %r15d, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: xorl %r13d, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: xorl %edi, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %eax, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: xorl %edi, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %r13d, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: xorl %r15d, %ebp +; CHECK-BASELINE-NEXT: movl %ebp, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-BASELINE-NEXT: xorl %r11d, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorw %bp, %r11w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: xorl %ebp, %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: xorw %ax, %r15w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-BASELINE-NEXT: xorl %eax, %r15d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: xorw %si, %r13w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-BASELINE-NEXT: xorl %esi, %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: xorw %dx, %di +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-BASELINE-NEXT: xorl %edx, %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorw %r14w, %si +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %r14d, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: xorw %r12w, %r14w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-BASELINE-NEXT: xorl %r12d, %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: xorw %ax, %dx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorw %r10w, %bp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: xorl %r10d, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %r12w, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %r12d, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %r12w, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %r12d, %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: xorw %r12w, %r10w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: xorl %r12d, %r10d +; CHECK-BASELINE-NEXT: movw %r10w, 30(%r8) +; CHECK-BASELINE-NEXT: movw %ax, 28(%r8) +; CHECK-BASELINE-NEXT: movw %cx, 26(%r8) +; CHECK-BASELINE-NEXT: movw %bp, 24(%r8) +; CHECK-BASELINE-NEXT: movw %dx, 22(%r8) +; CHECK-BASELINE-NEXT: movw %r14w, 20(%r8) +; CHECK-BASELINE-NEXT: movw %si, 18(%r8) +; CHECK-BASELINE-NEXT: movw %di, 16(%r8) +; CHECK-BASELINE-NEXT: movw %r13w, 14(%r8) +; CHECK-BASELINE-NEXT: movw %r15w, 12(%r8) +; CHECK-BASELINE-NEXT: movw %r11w, 10(%r8) +; CHECK-BASELINE-NEXT: movw %r9w, 8(%r8) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 6(%r8) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 4(%r8) +; CHECK-BASELINE-NEXT: movw %bx, 2(%r8) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, (%r8) +; CHECK-BASELINE-NEXT: movq %r8, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v16i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r8d, %ebp +; CHECK-SSE-NEXT: movl %edx, %ebx +; CHECK-SSE-NEXT: movq %rdi, %r8 +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorl %r11d, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: xorl %r15d, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: xorl %r13d, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: xorl %edi, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %eax, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: xorl %edi, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %r13d, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: xorl %r15d, %ebp +; CHECK-SSE-NEXT: movl %ebp, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-SSE-NEXT: xorl %r11d, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorw %bp, %r11w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: xorl %ebp, %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: xorw %ax, %r15w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-SSE-NEXT: xorl %eax, %r15d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: xorw %si, %r13w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-SSE-NEXT: xorl %esi, %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: xorw %dx, %di +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-SSE-NEXT: xorl %edx, %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: xorw %r14w, %si +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %r14d, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: xorw %r12w, %r14w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-SSE-NEXT: xorl %r12d, %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: xorw %ax, %dx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: xorl %eax, %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorw %r10w, %bp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: xorl %r10d, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %r12w, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %r12d, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %r12w, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %r12d, %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: xorw %r12w, %r10w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: xorl %r12d, %r10d +; CHECK-SSE-NEXT: movw %r10w, 30(%r8) +; CHECK-SSE-NEXT: movw %ax, 28(%r8) +; CHECK-SSE-NEXT: movw %cx, 26(%r8) +; CHECK-SSE-NEXT: movw %bp, 24(%r8) +; CHECK-SSE-NEXT: movw %dx, 22(%r8) +; CHECK-SSE-NEXT: movw %r14w, 20(%r8) +; CHECK-SSE-NEXT: movw %si, 18(%r8) +; CHECK-SSE-NEXT: movw %di, 16(%r8) +; CHECK-SSE-NEXT: movw %r13w, 14(%r8) +; CHECK-SSE-NEXT: movw %r15w, 12(%r8) +; CHECK-SSE-NEXT: movw %r11w, 10(%r8) +; CHECK-SSE-NEXT: movw %r9w, 8(%r8) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 6(%r8) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 4(%r8) +; CHECK-SSE-NEXT: movw %bx, 2(%r8) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, (%r8) +; CHECK-SSE-NEXT: movq %r8, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v16i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v16i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v16i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v16i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v16i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v16i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v16i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <16 x i16> %x, %y + %n1 = and <16 x i16> %n0, %mask + %r = xor <16 x i16> %n1, %y + ret <16 x i16> %r +} + +define <8 x i32> @in_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v8i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %esi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorl %ebx, %esi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorl %ebx, %edx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorl %ebx, %ecx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %r8d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: xorl %ebx, %r8d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %r9d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorl %ebx, %r9d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorl %eax, %ebp +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorl %eax, %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %r11d, %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %r11d, %eax +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %r10d, %ebx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %r10d, %ebx +; CHECK-BASELINE-NEXT: movl %ebx, 28(%rdi) +; CHECK-BASELINE-NEXT: movl %eax, 24(%rdi) +; CHECK-BASELINE-NEXT: movl %ebp, 20(%rdi) +; CHECK-BASELINE-NEXT: movl %r9d, 16(%rdi) +; CHECK-BASELINE-NEXT: movl %r8d, 12(%rdi) +; CHECK-BASELINE-NEXT: movl %ecx, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %edx, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %esi, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v8i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %esi +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: xorl %ebx, %esi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %edx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorl %ebx, %edx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorl %ebx, %ecx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %r8d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: xorl %ebx, %r8d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %r9d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorl %ebx, %r9d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorl %eax, %ebp +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorl %eax, %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %r11d, %eax +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %r11d, %eax +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %r10d, %ebx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %r10d, %ebx +; CHECK-SSE-NEXT: movl %ebx, 28(%rdi) +; CHECK-SSE-NEXT: movl %eax, 24(%rdi) +; CHECK-SSE-NEXT: movl %ebp, 20(%rdi) +; CHECK-SSE-NEXT: movl %r9d, 16(%rdi) +; CHECK-SSE-NEXT: movl %r8d, 12(%rdi) +; CHECK-SSE-NEXT: movl %ecx, 8(%rdi) +; CHECK-SSE-NEXT: movl %edx, 4(%rdi) +; CHECK-SSE-NEXT: movl %esi, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v8i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v8i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v8i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v8i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v8i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v8i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v8i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <8 x i32> %x, %y + %n1 = and <8 x i32> %n0, %mask + %r = xor <8 x i32> %n1, %y + ret <8 x i32> %r +} + +define <4 x i64> @in_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v4i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: xorq %r9, %rsi +; CHECK-BASELINE-NEXT: xorq %rax, %rdx +; CHECK-BASELINE-NEXT: xorq %r11, %rcx +; CHECK-BASELINE-NEXT: xorq %r10, %r8 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r8 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-BASELINE-NEXT: xorq %r9, %rsi +; CHECK-BASELINE-NEXT: xorq %rax, %rdx +; CHECK-BASELINE-NEXT: xorq %r11, %rcx +; CHECK-BASELINE-NEXT: xorq %r10, %r8 +; CHECK-BASELINE-NEXT: movq %r8, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %rcx, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %rdx, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %rsi, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v4i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: xorq %r9, %rsi +; CHECK-SSE-NEXT: xorq %rax, %rdx +; CHECK-SSE-NEXT: xorq %r11, %rcx +; CHECK-SSE-NEXT: xorq %r10, %r8 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r8 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-SSE-NEXT: xorq %r9, %rsi +; CHECK-SSE-NEXT: xorq %rax, %rdx +; CHECK-SSE-NEXT: xorq %r11, %rcx +; CHECK-SSE-NEXT: xorq %r10, %r8 +; CHECK-SSE-NEXT: movq %r8, 24(%rdi) +; CHECK-SSE-NEXT: movq %rcx, 16(%rdi) +; CHECK-SSE-NEXT: movq %rdx, 8(%rdi) +; CHECK-SSE-NEXT: movq %rsi, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v4i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v4i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: andps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm2, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: andps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm3, %xmm1 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v4i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v4i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v4i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v4i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v4i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm1, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <4 x i64> %x, %y + %n1 = and <4 x i64> %n0, %mask + %r = xor <4 x i64> %n1, %y + ret <4 x i64> %r +} + +; ============================================================================ ; +; 512-bit vector width +; ============================================================================ ; + +define <64 x i8> @in_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v64i8: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movq %rdi, %r12 +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %cl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %sil, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %sil, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bpl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bpl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %bl, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dil, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %dil, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r8b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r8b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r13b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r13b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r15b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r15b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r14b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r14b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r11b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r11b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r10b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r10b, %al +; CHECK-BASELINE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: xorb %al, %r15b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-BASELINE-NEXT: xorb %al, %r15b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: xorb %al, %r14b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-BASELINE-NEXT: xorb %al, %r14b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %al, %bpl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-BASELINE-NEXT: xorb %al, %bpl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %al, %bl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-BASELINE-NEXT: xorb %al, %bl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %al, %r11b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-BASELINE-NEXT: xorb %al, %r11b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %al, %r10b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-BASELINE-NEXT: xorb %al, %r10b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-BASELINE-NEXT: xorb %al, %r9b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-BASELINE-NEXT: xorb %al, %r8b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: xorb %al, %dil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-BASELINE-NEXT: xorb %al, %dil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %al, %sil +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-BASELINE-NEXT: xorb %al, %sil +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-BASELINE-NEXT: xorb %al, %dl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r13b, %al +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: xorb %r13b, %al +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: xorb {{[0-9]+}}(%rsp), %r13b +; CHECK-BASELINE-NEXT: movb %r13b, 63(%r12) +; CHECK-BASELINE-NEXT: movb %al, 62(%r12) +; CHECK-BASELINE-NEXT: movb %cl, 61(%r12) +; CHECK-BASELINE-NEXT: movb %dl, 60(%r12) +; CHECK-BASELINE-NEXT: movb %sil, 59(%r12) +; CHECK-BASELINE-NEXT: movb %dil, 58(%r12) +; CHECK-BASELINE-NEXT: movb %r8b, 57(%r12) +; CHECK-BASELINE-NEXT: movb %r9b, 56(%r12) +; CHECK-BASELINE-NEXT: movb %r10b, 55(%r12) +; CHECK-BASELINE-NEXT: movb %r11b, 54(%r12) +; CHECK-BASELINE-NEXT: movb %bl, 53(%r12) +; CHECK-BASELINE-NEXT: movb %bpl, 52(%r12) +; CHECK-BASELINE-NEXT: movb %r14b, 51(%r12) +; CHECK-BASELINE-NEXT: movb %r15b, 50(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 49(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 48(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 47(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 46(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 45(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 44(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 43(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 42(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 41(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 40(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 39(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 38(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 37(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 36(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 35(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 34(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 33(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 32(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 31(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 30(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 29(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 28(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 27(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 26(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 25(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 24(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 23(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 22(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 21(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 20(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 19(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 18(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 17(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 16(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 15(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 14(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 13(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 12(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 11(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 10(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 9(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 8(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 7(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 6(%r12) +; CHECK-BASELINE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 5(%r12) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movb %al, 4(%r12) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, 3(%r12) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, 2(%r12) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, 1(%r12) +; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-BASELINE-NEXT: xorb %al, %cl +; CHECK-BASELINE-NEXT: movb %cl, (%r12) +; CHECK-BASELINE-NEXT: movq %r12, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v64i8: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r8d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movq %rdi, %r12 +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %cl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %sil, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %sil, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bpl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bpl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %bl, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dil, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %dil, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r8b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r8b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r13b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r13b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r15b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r15b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r14b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r14b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r11b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r11b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r10b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r10b, %al +; CHECK-SSE-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: xorb %al, %r15b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r15b +; CHECK-SSE-NEXT: xorb %al, %r15b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: xorb %al, %r14b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r14b +; CHECK-SSE-NEXT: xorb %al, %r14b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %al, %bpl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bpl +; CHECK-SSE-NEXT: xorb %al, %bpl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %al, %bl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %bl +; CHECK-SSE-NEXT: xorb %al, %bl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %al, %r11b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r11b +; CHECK-SSE-NEXT: xorb %al, %r11b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %al, %r10b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r10b +; CHECK-SSE-NEXT: xorb %al, %r10b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r9b +; CHECK-SSE-NEXT: xorb %al, %r9b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r8b +; CHECK-SSE-NEXT: xorb %al, %r8b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: xorb %al, %dil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dil +; CHECK-SSE-NEXT: xorb %al, %dil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %al, %sil +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %sil +; CHECK-SSE-NEXT: xorb %al, %sil +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %dl +; CHECK-SSE-NEXT: xorb %al, %dl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r13b, %al +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: xorb %r13b, %al +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: xorb {{[0-9]+}}(%rsp), %r13b +; CHECK-SSE-NEXT: movb %r13b, 63(%r12) +; CHECK-SSE-NEXT: movb %al, 62(%r12) +; CHECK-SSE-NEXT: movb %cl, 61(%r12) +; CHECK-SSE-NEXT: movb %dl, 60(%r12) +; CHECK-SSE-NEXT: movb %sil, 59(%r12) +; CHECK-SSE-NEXT: movb %dil, 58(%r12) +; CHECK-SSE-NEXT: movb %r8b, 57(%r12) +; CHECK-SSE-NEXT: movb %r9b, 56(%r12) +; CHECK-SSE-NEXT: movb %r10b, 55(%r12) +; CHECK-SSE-NEXT: movb %r11b, 54(%r12) +; CHECK-SSE-NEXT: movb %bl, 53(%r12) +; CHECK-SSE-NEXT: movb %bpl, 52(%r12) +; CHECK-SSE-NEXT: movb %r14b, 51(%r12) +; CHECK-SSE-NEXT: movb %r15b, 50(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 49(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 48(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 47(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 46(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 45(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 44(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 43(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 42(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 41(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 40(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 39(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 38(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 37(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 36(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 35(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 34(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 33(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 32(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 31(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 30(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 29(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 28(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 27(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 26(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 25(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 24(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 23(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 22(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 21(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 20(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 19(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 18(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 17(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 16(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 15(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 14(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 13(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 12(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 11(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 10(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 9(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 8(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 7(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 6(%r12) +; CHECK-SSE-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload +; CHECK-SSE-NEXT: movb %al, 5(%r12) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movb %al, 4(%r12) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, 3(%r12) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, 2(%r12) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, 1(%r12) +; CHECK-SSE-NEXT: movb {{[0-9]+}}(%rsp), %al +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: andb {{[0-9]+}}(%rsp), %cl +; CHECK-SSE-NEXT: xorb %al, %cl +; CHECK-SSE-NEXT: movb %cl, (%r12) +; CHECK-SSE-NEXT: movq %r12, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v64i8: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v64i8: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v64i8: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v64i8: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v64i8: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v64i8: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v64i8: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <64 x i8> %x, %y + %n1 = and <64 x i8> %n0, %mask + %r = xor <64 x i8> %n1, %y + ret <64 x i8> %r +} + +define <32 x i16> @in_v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v32i16: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %ebx, %r9d +; CHECK-BASELINE-NEXT: movl %r9d, %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorl %r9d, %r8d +; CHECK-BASELINE-NEXT: movl %r8d, %r15d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: xorl %r8d, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorl %ecx, %edx +; CHECK-BASELINE-NEXT: movl %edx, %r13d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorl %edx, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %edx, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-BASELINE-NEXT: xorl %ecx, %r13d +; CHECK-BASELINE-NEXT: movl %r13d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-BASELINE-NEXT: xorl %r8d, %r12d +; CHECK-BASELINE-NEXT: movl %r12d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-BASELINE-NEXT: xorl %r9d, %r15d +; CHECK-BASELINE-NEXT: movl %r15d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-BASELINE-NEXT: xorl %ebx, %r14d +; CHECK-BASELINE-NEXT: movl %r14d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorw %si, %bx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: xorl %esi, %ebx +; CHECK-BASELINE-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorw %dx, %si +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %edx, %esi +; CHECK-BASELINE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorw %cx, %dx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: xorl %ecx, %edx +; CHECK-BASELINE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %di, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %edi, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %bp, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %ebp, %eax +; CHECK-BASELINE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %r10w, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %r10d, %eax +; CHECK-BASELINE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %r11w, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %r11d, %eax +; CHECK-BASELINE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: xorw %ax, %r12w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-BASELINE-NEXT: xorl %eax, %r12d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: xorw %ax, %r15w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-BASELINE-NEXT: xorl %eax, %r15d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorw %ax, %bp +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-BASELINE-NEXT: xorl %eax, %ebp +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorw %ax, %bx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-BASELINE-NEXT: xorl %eax, %ebx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorw %ax, %r11w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-BASELINE-NEXT: xorl %eax, %r11d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: xorw %ax, %r10w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-BASELINE-NEXT: xorl %eax, %r10d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorw %ax, %r9w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-BASELINE-NEXT: xorl %eax, %r9d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: xorw %ax, %r8w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-BASELINE-NEXT: xorl %eax, %r8d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-BASELINE-NEXT: xorw %ax, %di +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-BASELINE-NEXT: xorl %eax, %edi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorw %ax, %si +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-BASELINE-NEXT: xorl %eax, %esi +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorw %ax, %dx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-BASELINE-NEXT: xorl %eax, %edx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorw %ax, %cx +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorw %r14w, %ax +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-BASELINE-NEXT: xorl %r14d, %eax +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: xorw %r14w, %r13w +; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-BASELINE-NEXT: xorl %r14d, %r13d +; CHECK-BASELINE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload +; CHECK-BASELINE-NEXT: movw %r13w, 62(%r14) +; CHECK-BASELINE-NEXT: movw %ax, 60(%r14) +; CHECK-BASELINE-NEXT: movw %cx, 58(%r14) +; CHECK-BASELINE-NEXT: movw %dx, 56(%r14) +; CHECK-BASELINE-NEXT: movw %si, 54(%r14) +; CHECK-BASELINE-NEXT: movw %di, 52(%r14) +; CHECK-BASELINE-NEXT: movw %r8w, 50(%r14) +; CHECK-BASELINE-NEXT: movw %r9w, 48(%r14) +; CHECK-BASELINE-NEXT: movw %r10w, 46(%r14) +; CHECK-BASELINE-NEXT: movw %r11w, 44(%r14) +; CHECK-BASELINE-NEXT: movw %bx, 42(%r14) +; CHECK-BASELINE-NEXT: movw %bp, 40(%r14) +; CHECK-BASELINE-NEXT: movw %r15w, 38(%r14) +; CHECK-BASELINE-NEXT: movw %r12w, 36(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 34(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 32(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 30(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 28(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 26(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 24(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 22(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 20(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 18(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 16(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 14(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 12(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 10(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 8(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 6(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 4(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, 2(%r14) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movw %ax, (%r14) +; CHECK-BASELINE-NEXT: movq %r14, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v32i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %ebx, %r9d +; CHECK-SSE-NEXT: movl %r9d, %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorl %r9d, %r8d +; CHECK-SSE-NEXT: movl %r8d, %r15d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: xorl %r8d, %ecx +; CHECK-SSE-NEXT: movl %ecx, %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorl %ecx, %edx +; CHECK-SSE-NEXT: movl %edx, %r13d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorl %edx, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %edx, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-SSE-NEXT: xorl %ecx, %r13d +; CHECK-SSE-NEXT: movl %r13d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-SSE-NEXT: xorl %r8d, %r12d +; CHECK-SSE-NEXT: movl %r12d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-SSE-NEXT: xorl %r9d, %r15d +; CHECK-SSE-NEXT: movl %r15d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r14w +; CHECK-SSE-NEXT: xorl %ebx, %r14d +; CHECK-SSE-NEXT: movl %r14d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorw %si, %bx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: xorl %esi, %ebx +; CHECK-SSE-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: xorw %dx, %si +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %edx, %esi +; CHECK-SSE-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorw %cx, %dx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: xorl %ecx, %edx +; CHECK-SSE-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %di, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %edi, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %bp, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %ebp, %eax +; CHECK-SSE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %r10w, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %r10d, %eax +; CHECK-SSE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %r11w, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %r11d, %eax +; CHECK-SSE-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: xorw %ax, %r12w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r12w +; CHECK-SSE-NEXT: xorl %eax, %r12d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: xorw %ax, %r15w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r15w +; CHECK-SSE-NEXT: xorl %eax, %r15d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorw %ax, %bp +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bp +; CHECK-SSE-NEXT: xorl %eax, %ebp +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorw %ax, %bx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %bx +; CHECK-SSE-NEXT: xorl %eax, %ebx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorw %ax, %r11w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r11w +; CHECK-SSE-NEXT: xorl %eax, %r11d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: xorw %ax, %r10w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r10w +; CHECK-SSE-NEXT: xorl %eax, %r10d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorw %ax, %r9w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r9w +; CHECK-SSE-NEXT: xorl %eax, %r9d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: xorw %ax, %r8w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r8w +; CHECK-SSE-NEXT: xorl %eax, %r8d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi +; CHECK-SSE-NEXT: xorw %ax, %di +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %di +; CHECK-SSE-NEXT: xorl %eax, %edi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: xorw %ax, %si +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %si +; CHECK-SSE-NEXT: xorl %eax, %esi +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorw %ax, %dx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %dx +; CHECK-SSE-NEXT: xorl %eax, %edx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorw %ax, %cx +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %cx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorw %r14w, %ax +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %ax +; CHECK-SSE-NEXT: xorl %r14d, %eax +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: xorw %r14w, %r13w +; CHECK-SSE-NEXT: andw {{[0-9]+}}(%rsp), %r13w +; CHECK-SSE-NEXT: xorl %r14d, %r13d +; CHECK-SSE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload +; CHECK-SSE-NEXT: movw %r13w, 62(%r14) +; CHECK-SSE-NEXT: movw %ax, 60(%r14) +; CHECK-SSE-NEXT: movw %cx, 58(%r14) +; CHECK-SSE-NEXT: movw %dx, 56(%r14) +; CHECK-SSE-NEXT: movw %si, 54(%r14) +; CHECK-SSE-NEXT: movw %di, 52(%r14) +; CHECK-SSE-NEXT: movw %r8w, 50(%r14) +; CHECK-SSE-NEXT: movw %r9w, 48(%r14) +; CHECK-SSE-NEXT: movw %r10w, 46(%r14) +; CHECK-SSE-NEXT: movw %r11w, 44(%r14) +; CHECK-SSE-NEXT: movw %bx, 42(%r14) +; CHECK-SSE-NEXT: movw %bp, 40(%r14) +; CHECK-SSE-NEXT: movw %r15w, 38(%r14) +; CHECK-SSE-NEXT: movw %r12w, 36(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 34(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 32(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 30(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 28(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 26(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 24(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 22(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 20(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 18(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 16(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 14(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 12(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 10(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 8(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 6(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 4(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, 2(%r14) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movw %ax, (%r14) +; CHECK-SSE-NEXT: movq %r14, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v32i16: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v32i16: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v32i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v32i16: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v32i16: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512F-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v32i16: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512DQ-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v32i16: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX512VL-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <32 x i16> %x, %y + %n1 = and <32 x i16> %n0, %mask + %r = xor <32 x i16> %n1, %y + ret <32 x i16> %r +} + +define <16 x i32> @in_v16i32(<16 x i32> %x, <16 x i32> %y, <16 x i32> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v16i32: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %rbp +; CHECK-BASELINE-NEXT: pushq %r15 +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %r13 +; CHECK-BASELINE-NEXT: pushq %r12 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movl %r8d, %r10d +; CHECK-BASELINE-NEXT: movl %edx, %r8d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %esi +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-BASELINE-NEXT: xorl %eax, %esi +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %r8d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-BASELINE-NEXT: xorl %eax, %r8d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorl %eax, %ecx +; CHECK-BASELINE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %r10d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: xorl %eax, %r10d +; CHECK-BASELINE-NEXT: movl %r10d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %r9d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorl %eax, %r9d +; CHECK-BASELINE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorl %ebp, %edx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-BASELINE-NEXT: xorl %ebp, %edx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorl %ebx, %ebp +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-BASELINE-NEXT: xorl %ebx, %ebp +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %r13d, %ebx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-BASELINE-NEXT: xorl %r13d, %ebx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: xorl %r12d, %r13d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r13d +; CHECK-BASELINE-NEXT: xorl %r12d, %r13d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: xorl %r15d, %r12d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r12d +; CHECK-BASELINE-NEXT: xorl %r15d, %r12d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: xorl %r14d, %r15d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r15d +; CHECK-BASELINE-NEXT: xorl %r14d, %r15d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: xorl %r11d, %r14d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-BASELINE-NEXT: xorl %r11d, %r14d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %eax, %r11d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-BASELINE-NEXT: xorl %eax, %r11d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorl %r10d, %ecx +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-BASELINE-NEXT: xorl %r10d, %ecx +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %r10d, %eax +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-BASELINE-NEXT: xorl %r10d, %eax +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorl %r10d, %r9d +; CHECK-BASELINE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-BASELINE-NEXT: xorl %r10d, %r9d +; CHECK-BASELINE-NEXT: movl %r9d, 60(%rdi) +; CHECK-BASELINE-NEXT: movl %eax, 56(%rdi) +; CHECK-BASELINE-NEXT: movl %ecx, 52(%rdi) +; CHECK-BASELINE-NEXT: movl %r11d, 48(%rdi) +; CHECK-BASELINE-NEXT: movl %r14d, 44(%rdi) +; CHECK-BASELINE-NEXT: movl %r15d, 40(%rdi) +; CHECK-BASELINE-NEXT: movl %r12d, 36(%rdi) +; CHECK-BASELINE-NEXT: movl %r13d, 32(%rdi) +; CHECK-BASELINE-NEXT: movl %ebx, 28(%rdi) +; CHECK-BASELINE-NEXT: movl %ebp, 24(%rdi) +; CHECK-BASELINE-NEXT: movl %edx, 20(%rdi) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %eax, 16(%rdi) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %eax, 12(%rdi) +; CHECK-BASELINE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-BASELINE-NEXT: movl %eax, 8(%rdi) +; CHECK-BASELINE-NEXT: movl %r8d, 4(%rdi) +; CHECK-BASELINE-NEXT: movl %esi, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r12 +; CHECK-BASELINE-NEXT: popq %r13 +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: popq %r15 +; CHECK-BASELINE-NEXT: popq %rbp +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v16i32: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %rbp +; CHECK-SSE-NEXT: pushq %r15 +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %r13 +; CHECK-SSE-NEXT: pushq %r12 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movl %r8d, %r10d +; CHECK-SSE-NEXT: movl %edx, %r8d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %esi +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %esi +; CHECK-SSE-NEXT: xorl %eax, %esi +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %r8d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r8d +; CHECK-SSE-NEXT: xorl %eax, %r8d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorl %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %r10d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: xorl %eax, %r10d +; CHECK-SSE-NEXT: movl %r10d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %r9d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorl %eax, %r9d +; CHECK-SSE-NEXT: movl %r9d, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorl %ebp, %edx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %edx +; CHECK-SSE-NEXT: xorl %ebp, %edx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorl %ebx, %ebp +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebp +; CHECK-SSE-NEXT: xorl %ebx, %ebp +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %r13d, %ebx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ebx +; CHECK-SSE-NEXT: xorl %r13d, %ebx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: xorl %r12d, %r13d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r13d +; CHECK-SSE-NEXT: xorl %r12d, %r13d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: xorl %r15d, %r12d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r12d +; CHECK-SSE-NEXT: xorl %r15d, %r12d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: xorl %r14d, %r15d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r15d +; CHECK-SSE-NEXT: xorl %r14d, %r15d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: xorl %r11d, %r14d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r14d +; CHECK-SSE-NEXT: xorl %r11d, %r14d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %eax, %r11d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r11d +; CHECK-SSE-NEXT: xorl %eax, %r11d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorl %r10d, %ecx +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %ecx +; CHECK-SSE-NEXT: xorl %r10d, %ecx +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %r10d, %eax +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %eax +; CHECK-SSE-NEXT: xorl %r10d, %eax +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d +; CHECK-SSE-NEXT: movl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorl %r10d, %r9d +; CHECK-SSE-NEXT: andl {{[0-9]+}}(%rsp), %r9d +; CHECK-SSE-NEXT: xorl %r10d, %r9d +; CHECK-SSE-NEXT: movl %r9d, 60(%rdi) +; CHECK-SSE-NEXT: movl %eax, 56(%rdi) +; CHECK-SSE-NEXT: movl %ecx, 52(%rdi) +; CHECK-SSE-NEXT: movl %r11d, 48(%rdi) +; CHECK-SSE-NEXT: movl %r14d, 44(%rdi) +; CHECK-SSE-NEXT: movl %r15d, 40(%rdi) +; CHECK-SSE-NEXT: movl %r12d, 36(%rdi) +; CHECK-SSE-NEXT: movl %r13d, 32(%rdi) +; CHECK-SSE-NEXT: movl %ebx, 28(%rdi) +; CHECK-SSE-NEXT: movl %ebp, 24(%rdi) +; CHECK-SSE-NEXT: movl %edx, 20(%rdi) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movl %eax, 16(%rdi) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movl %eax, 12(%rdi) +; CHECK-SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; CHECK-SSE-NEXT: movl %eax, 8(%rdi) +; CHECK-SSE-NEXT: movl %r8d, 4(%rdi) +; CHECK-SSE-NEXT: movl %esi, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r12 +; CHECK-SSE-NEXT: popq %r13 +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: popq %r15 +; CHECK-SSE-NEXT: popq %rbp +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v16i32: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v16i32: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v16i32: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v16i32: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v16i32: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vpxorq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpandq %zmm2, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpxorq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v16i32: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v16i32: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <16 x i32> %x, %y + %n1 = and <16 x i32> %n0, %mask + %r = xor <16 x i32> %n1, %y + ret <16 x i32> %r +} + +define <8 x i64> @in_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %mask) nounwind { +; CHECK-BASELINE-LABEL: in_v8i64: +; CHECK-BASELINE: # %bb.0: +; CHECK-BASELINE-NEXT: pushq %r14 +; CHECK-BASELINE-NEXT: pushq %rbx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %rbx, %rsi +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-BASELINE-NEXT: xorq %rbx, %rsi +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %rbx, %rdx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-BASELINE-NEXT: xorq %rbx, %rdx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %rbx, %rcx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-BASELINE-NEXT: xorq %rbx, %rcx +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %rbx, %r8 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r8 +; CHECK-BASELINE-NEXT: xorq %rbx, %r8 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %rbx, %r9 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r9 +; CHECK-BASELINE-NEXT: xorq %rbx, %r9 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: xorq %rax, %r14 +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-BASELINE-NEXT: xorq %rax, %r14 +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: xorq %r11, %rax +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-BASELINE-NEXT: xorq %r11, %rax +; CHECK-BASELINE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %r10, %rbx +; CHECK-BASELINE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-BASELINE-NEXT: xorq %r10, %rbx +; CHECK-BASELINE-NEXT: movq %rbx, 56(%rdi) +; CHECK-BASELINE-NEXT: movq %rax, 48(%rdi) +; CHECK-BASELINE-NEXT: movq %r14, 40(%rdi) +; CHECK-BASELINE-NEXT: movq %r9, 32(%rdi) +; CHECK-BASELINE-NEXT: movq %r8, 24(%rdi) +; CHECK-BASELINE-NEXT: movq %rcx, 16(%rdi) +; CHECK-BASELINE-NEXT: movq %rdx, 8(%rdi) +; CHECK-BASELINE-NEXT: movq %rsi, (%rdi) +; CHECK-BASELINE-NEXT: movq %rdi, %rax +; CHECK-BASELINE-NEXT: popq %rbx +; CHECK-BASELINE-NEXT: popq %r14 +; CHECK-BASELINE-NEXT: retq +; +; CHECK-SSE-LABEL: in_v8i64: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: pushq %r14 +; CHECK-SSE-NEXT: pushq %rbx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %rbx, %rsi +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rsi +; CHECK-SSE-NEXT: xorq %rbx, %rsi +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %rbx, %rdx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx +; CHECK-SSE-NEXT: xorq %rbx, %rdx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %rbx, %rcx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rcx +; CHECK-SSE-NEXT: xorq %rbx, %rcx +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %rbx, %r8 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r8 +; CHECK-SSE-NEXT: xorq %rbx, %r8 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %rbx, %r9 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r9 +; CHECK-SSE-NEXT: xorq %rbx, %r9 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: xorq %rax, %r14 +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %r14 +; CHECK-SSE-NEXT: xorq %rax, %r14 +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: xorq %r11, %rax +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax +; CHECK-SSE-NEXT: xorq %r11, %rax +; CHECK-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %r10, %rbx +; CHECK-SSE-NEXT: andq {{[0-9]+}}(%rsp), %rbx +; CHECK-SSE-NEXT: xorq %r10, %rbx +; CHECK-SSE-NEXT: movq %rbx, 56(%rdi) +; CHECK-SSE-NEXT: movq %rax, 48(%rdi) +; CHECK-SSE-NEXT: movq %r14, 40(%rdi) +; CHECK-SSE-NEXT: movq %r9, 32(%rdi) +; CHECK-SSE-NEXT: movq %r8, 24(%rdi) +; CHECK-SSE-NEXT: movq %rcx, 16(%rdi) +; CHECK-SSE-NEXT: movq %rdx, 8(%rdi) +; CHECK-SSE-NEXT: movq %rsi, (%rdi) +; CHECK-SSE-NEXT: movq %rdi, %rax +; CHECK-SSE-NEXT: popq %rbx +; CHECK-SSE-NEXT: popq %r14 +; CHECK-SSE-NEXT: retq +; +; CHECK-SSE2-LABEL: in_v8i64: +; CHECK-SSE2: # %bb.0: +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE2-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE2-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE2-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE2-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE2-NEXT: retq +; +; CHECK-SSE41-LABEL: in_v8i64: +; CHECK-SSE41: # %bb.0: +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE41-NEXT: andps {{[0-9]+}}(%rsp), %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm4, %xmm0 +; CHECK-SSE41-NEXT: xorps %xmm5, %xmm1 +; CHECK-SSE41-NEXT: xorps %xmm6, %xmm2 +; CHECK-SSE41-NEXT: xorps %xmm7, %xmm3 +; CHECK-SSE41-NEXT: retq +; +; CHECK-AVX-LABEL: in_v8i64: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX-NEXT: retq +; +; CHECK-AVX2-LABEL: in_v8i64: +; CHECK-AVX2: # %bb.0: +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm2, %ymm0, %ymm0 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vandps %ymm5, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: vxorps %ymm3, %ymm1, %ymm1 +; CHECK-AVX2-NEXT: retq +; +; CHECK-AVX512F-LABEL: in_v8i64: +; CHECK-AVX512F: # %bb.0: +; CHECK-AVX512F-NEXT: vpxorq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpandq %zmm2, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: vpxorq %zmm1, %zmm0, %zmm0 +; CHECK-AVX512F-NEXT: retq +; +; CHECK-AVX512DQ-LABEL: in_v8i64: +; CHECK-AVX512DQ: # %bb.0: +; CHECK-AVX512DQ-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512DQ-NEXT: retq +; +; CHECK-AVX512VL-LABEL: in_v8i64: +; CHECK-AVX512VL: # %bb.0: +; CHECK-AVX512VL-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vandps %zmm2, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: vxorps %zmm1, %zmm0, %zmm0 +; CHECK-AVX512VL-NEXT: retq + %n0 = xor <8 x i64> %x, %y + %n1 = and <8 x i64> %n0, %mask + %r = xor <8 x i64> %n1, %y + ret <8 x i64> %r +}