Index: lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -140,6 +140,23 @@
   defm GLD1D      : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d",    ZPR64ExtLSL64>;
   defm GLDFF1D    : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d",  ZPR64ExtLSL64>;
 
+  // Gathers using unscaled 32-bit offsets packed in 64-bits elements, e.g.
+  //    ld1h z32.d, p0/z, [x0, z0.d, uxtw]
+  defm GLD1SB_D   : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1B_D    : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1B_D  : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1SH_D   : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1H_D    : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1H_D  : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1SW_D   : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1W_D    : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1W_D  : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1D      : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLDFF1D    : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
   defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
Index: lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- lib/Target/AArch64/SVEInstrFormats.td
+++ lib/Target/AArch64/SVEInstrFormats.td
@@ -811,6 +811,44 @@
 // SVE Memory - 64-bit Gather Group
 //===----------------------------------------------------------------------===//
 
+class sve_mem_64b_gld_vs<bits<4> opc, bit xs, string asm,
+                         RegisterOperand zprext>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+  asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zm;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1100010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22}    = xs;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
+                                          RegisterOperand sxtw_opnd,
+                                          RegisterOperand uxtw_opnd> {
+  def _UXTW_REAL : sve_mem_64b_gld_vs<opc, 0, asm, uxtw_opnd>;
+  def _SXTW_REAL : sve_mem_64b_gld_vs<opc, 1, asm, sxtw_opnd>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
+
 class sve_mem_64b_gld_sv2<bits<4> opc, string asm, RegisterOperand zprext>
 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
Index: test/MC/AArch64/SVE/ld1b.s
===================================================================
--- test/MC/AArch64/SVE/ld1b.s
+++ test/MC/AArch64/SVE/ld1b.s
@@ -156,3 +156,15 @@
 // CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff df 5f c4 <unknown>
+
+ld1b    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1b    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 15 c4 <unknown>
+
+ld1b    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1b    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 c4 <unknown>
Index: test/MC/AArch64/SVE/ld1d.s
===================================================================
--- test/MC/AArch64/SVE/ld1d.s
+++ test/MC/AArch64/SVE/ld1d.s
@@ -54,3 +54,15 @@
 // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 cd e8 c5 <unknown>
+
+ld1d    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1d    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 95 c5 <unknown>
+
+ld1d    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1d    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 d5 c5 <unknown>
Index: test/MC/AArch64/SVE/ld1h.s
===================================================================
--- test/MC/AArch64/SVE/ld1h.s
+++ test/MC/AArch64/SVE/ld1h.s
@@ -138,3 +138,15 @@
 // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 cd e8 c4 <unknown>
+
+ld1h    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1h    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 95 c4 <unknown>
+
+ld1h    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1h    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 d5 c4 <unknown>
Index: test/MC/AArch64/SVE/ld1sb.s
===================================================================
--- test/MC/AArch64/SVE/ld1sb.s
+++ test/MC/AArch64/SVE/ld1sb.s
@@ -126,3 +126,15 @@
 // CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 9f 5f c4 <unknown>
+
+ld1sb   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 15 c4 <unknown>
+
+ld1sb   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 55 c4 <unknown>
Index: test/MC/AArch64/SVE/ld1sh.s
===================================================================
--- test/MC/AArch64/SVE/ld1sh.s
+++ test/MC/AArch64/SVE/ld1sh.s
@@ -108,3 +108,15 @@
 // CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 8d e8 c4 <unknown>
+
+ld1sh   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 95 c4 <unknown>
+
+ld1sh   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 d5 c4 <unknown>
Index: test/MC/AArch64/SVE/ld1sw.s
===================================================================
--- test/MC/AArch64/SVE/ld1sw.s
+++ test/MC/AArch64/SVE/ld1sw.s
@@ -54,3 +54,15 @@
 // CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 8d 68 c5 <unknown>
+
+ld1sw   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 15 c5 <unknown>
+
+ld1sw   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 55 c5 <unknown>
Index: test/MC/AArch64/SVE/ld1w.s
===================================================================
--- test/MC/AArch64/SVE/ld1w.s
+++ test/MC/AArch64/SVE/ld1w.s
@@ -108,3 +108,15 @@
 // CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 cd 68 c5 <unknown>
+
+ld1w    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1w    { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 15 c5 <unknown>
+
+ld1w    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1w    { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 c5 <unknown>
Index: test/MC/AArch64/SVE/ldff1b.s
===================================================================
--- test/MC/AArch64/SVE/ldff1b.s
+++ test/MC/AArch64/SVE/ldff1b.s
@@ -90,3 +90,15 @@
 // CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff 5f c4 <unknown>
+
+ldff1b  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1b  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 15 c4 <unknown>
+
+ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 55 c4 <unknown>
Index: test/MC/AArch64/SVE/ldff1d.s
===================================================================
--- test/MC/AArch64/SVE/ldff1d.s
+++ test/MC/AArch64/SVE/ldff1d.s
@@ -36,3 +36,15 @@
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
+
+ldff1d  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1d  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
+
+ldff1d  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1d  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>
Index: test/MC/AArch64/SVE/ldff1h.s
===================================================================
--- test/MC/AArch64/SVE/ldff1h.s
+++ test/MC/AArch64/SVE/ldff1h.s
@@ -96,3 +96,15 @@
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
+
+ldff1h  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1h  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
+
+ldff1h  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1h  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>
Index: test/MC/AArch64/SVE/ldff1sb.s
===================================================================
--- test/MC/AArch64/SVE/ldff1sb.s
+++ test/MC/AArch64/SVE/ldff1sb.s
@@ -78,3 +78,15 @@
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 5f c4 <unknown>
+
+ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 15 c4 <unknown>
+
+ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 55 c4 <unknown>
Index: test/MC/AArch64/SVE/ldff1sh.s
===================================================================
--- test/MC/AArch64/SVE/ldff1sh.s
+++ test/MC/AArch64/SVE/ldff1sh.s
@@ -78,3 +78,15 @@
 // CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 ad e8 c4 <unknown>
+
+ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 95 c4 <unknown>
+
+ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 d5 c4 <unknown>
Index: test/MC/AArch64/SVE/ldff1sw.s
===================================================================
--- test/MC/AArch64/SVE/ldff1sw.s
+++ test/MC/AArch64/SVE/ldff1sw.s
@@ -36,3 +36,15 @@
 // CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 ad 68 c5 <unknown>
+
+ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 15 c5 <unknown>
+
+ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 55 c5 <unknown>
Index: test/MC/AArch64/SVE/ldff1w.s
===================================================================
--- test/MC/AArch64/SVE/ldff1w.s
+++ test/MC/AArch64/SVE/ldff1w.s
@@ -78,3 +78,15 @@
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
+
+ldff1w  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1w  { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 15 c5 <unknown>
+
+ldff1w  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1w  { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 55 c5 <unknown>