Index: lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -88,6 +88,19 @@
   defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d,  "ld3d", simm4Scale3MulVl>;
   defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4Scale4MulVl>;
 
+  // Gathers using unscaled 32-bit offsets, e.g.
+  //    ld1h z32.s, p0/z, [z0.s, uxtw]
+  defm GLD1SB_S   : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1B_S    : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1B_S  : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1SH_S   : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1H_S    : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1H_S  : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1W      : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1W    : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
   defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
Index: lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- lib/Target/AArch64/SVEInstrFormats.td
+++ lib/Target/AArch64/SVEInstrFormats.td
@@ -725,3 +725,45 @@
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
                   (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
 }
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - 32-bit Gather and Unsized Contiguous Group
+//===----------------------------------------------------------------------===//
+
+class sve_mem_32b_gld_vs<bits<4> opc, bit xs, string asm,
+                         RegisterOperand zprext>
+: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+  asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zm;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1000010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22}    = xs;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
+                                          RegisterOperand sxtw_opnd,
+                                          RegisterOperand uxtw_opnd> {
+  def _UXTW_REAL : sve_mem_32b_gld_vs<opc, 0, asm, uxtw_opnd>;
+  def _SXTW_REAL : sve_mem_32b_gld_vs<opc, 1, asm, sxtw_opnd>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
Index: test/MC/AArch64/SVE/ld1b.s
===================================================================
--- test/MC/AArch64/SVE/ld1b.s
+++ test/MC/AArch64/SVE/ld1b.s
@@ -138,3 +138,15 @@
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
+
+ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 84 <unknown>
+
+ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 84 <unknown>
Index: test/MC/AArch64/SVE/ld1h.s
===================================================================
--- test/MC/AArch64/SVE/ld1h.s
+++ test/MC/AArch64/SVE/ld1h.s
@@ -102,3 +102,15 @@
 // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
+
+ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 84 <unknown>
+
+ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 84 <unknown>
Index: test/MC/AArch64/SVE/ld1sb.s
===================================================================
--- test/MC/AArch64/SVE/ld1sb.s
+++ test/MC/AArch64/SVE/ld1sb.s
@@ -108,3 +108,15 @@
 // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
+
+ld1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 00 84 <unknown>
+
+ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 40 84 <unknown>
Index: test/MC/AArch64/SVE/ld1sh.s
===================================================================
--- test/MC/AArch64/SVE/ld1sh.s
+++ test/MC/AArch64/SVE/ld1sh.s
@@ -72,3 +72,15 @@
 // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
+
+ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 80 84 <unknown>
+
+ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 c0 84 <unknown>
Index: test/MC/AArch64/SVE/ld1w.s
===================================================================
--- test/MC/AArch64/SVE/ld1w.s
+++ test/MC/AArch64/SVE/ld1w.s
@@ -72,3 +72,15 @@
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
+
+ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 85 <unknown>
+
+ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 85 <unknown>
Index: test/MC/AArch64/SVE/ldff1b.s
===================================================================
--- test/MC/AArch64/SVE/ldff1b.s
+++ test/MC/AArch64/SVE/ldff1b.s
@@ -72,3 +72,15 @@
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 a4 <unknown>
+
+ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 84 <unknown>
+
+ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 84 <unknown>
Index: test/MC/AArch64/SVE/ldff1h.s
===================================================================
--- test/MC/AArch64/SVE/ldff1h.s
+++ test/MC/AArch64/SVE/ldff1h.s
@@ -60,3 +60,15 @@
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
+
+ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 80 84 <unknown>
+
+ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 c0 84 <unknown>
Index: test/MC/AArch64/SVE/ldff1sb.s
===================================================================
--- test/MC/AArch64/SVE/ldff1sb.s
+++ test/MC/AArch64/SVE/ldff1sb.s
@@ -60,3 +60,15 @@
 // CHECK-ENCODING: [0x00,0x60,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 80 a5 <unknown>
+
+ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 00 84 <unknown>
+
+ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 40 84 <unknown>
Index: test/MC/AArch64/SVE/ldff1sh.s
===================================================================
--- test/MC/AArch64/SVE/ldff1sh.s
+++ test/MC/AArch64/SVE/ldff1sh.s
@@ -42,3 +42,15 @@
 // CHECK-ENCODING: [0x00,0x60,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 00 a5 <unknown>
+
+ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 80 84 <unknown>
+
+ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 c0 84 <unknown>
Index: test/MC/AArch64/SVE/ldff1w.s
===================================================================
--- test/MC/AArch64/SVE/ldff1w.s
+++ test/MC/AArch64/SVE/ldff1w.s
@@ -42,3 +42,15 @@
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 a5 <unknown>
+
+ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 85 <unknown>
+
+ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 85 <unknown>