Index: include/llvm-c/TargetMachine.h =================================================================== --- include/llvm-c/TargetMachine.h +++ include/llvm-c/TargetMachine.h @@ -35,6 +35,12 @@ LLVMCodeGenLevelAggressive } LLVMCodeGenOptLevel; +typedef enum { + LLVMCodeGenSizeLevelNone, + LLVMCodeGenSizeLevelOptSize, + LLVMCodeGenSizeLevelMinSize +} LLVMCodeGenSizeOptLevel; + typedef enum { LLVMRelocDefault, LLVMRelocStatic, @@ -89,9 +95,11 @@ /*===-- Target Machine ----------------------------------------------------===*/ /** Creates a new llvm::TargetMachine. See llvm::Target::createTargetMachine */ -LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, - const char *Triple, const char *CPU, const char *Features, - LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel); +LLVMTargetMachineRef +LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, + const char *Features, LLVMCodeGenOptLevel Level, + LLVMCodeGenSizeOptLevel SizeLevel, LLVMRelocMode Reloc, + LLVMCodeModel CodeModel); /** Dispose the LLVMTargetMachineRef instance generated by LLVMCreateTargetMachine. */ Index: include/llvm/CodeGen/TargetPassConfig.h =================================================================== --- include/llvm/CodeGen/TargetPassConfig.h +++ include/llvm/CodeGen/TargetPassConfig.h @@ -144,6 +144,7 @@ void setInitialized() { Initialized = true; } CodeGenOpt::Level getOptLevel() const; + CodeGenSizeOpt::Level getSizeOptLevel() const; /// Describe the status of the codegen /// pipeline set by this target pass config. Index: include/llvm/Support/CodeGen.h =================================================================== --- include/llvm/Support/CodeGen.h +++ include/llvm/Support/CodeGen.h @@ -57,6 +57,15 @@ }; } + // Code generation size optimization level. + namespace CodeGenSizeOpt { + enum Level { + None, // -O0...-O3 + OptSize, // -Os + MinSize // -Oz + }; + } + } // end llvm namespace #endif Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -113,10 +113,12 @@ using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT, StringRef CPU, StringRef Features); - using TargetMachineCtorTy = TargetMachine - *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features, - const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT); + using TargetMachineCtorTy = + TargetMachine *(*)(const Target &T, const Triple &TT, StringRef CPU, + StringRef Features, const TargetOptions &Options, + Optional RM, + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT); // If it weren't for layering issues (this header is in llvm/Support, but // depends on MC?) this should take the Streamer by value rather than rvalue // reference. @@ -367,17 +369,17 @@ /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - TargetMachine *createTargetMachine(StringRef TT, StringRef CPU, - StringRef Features, - const TargetOptions &Options, - Optional RM, - Optional CM = None, - CodeGenOpt::Level OL = CodeGenOpt::Default, - bool JIT = false) const { + TargetMachine * + createTargetMachine(StringRef TT, StringRef CPU, StringRef Features, + const TargetOptions &Options, Optional RM, + Optional CM = None, + CodeGenOpt::Level OL = CodeGenOpt::Default, + CodeGenSizeOpt::Level SL = CodeGenSizeOpt::None, + bool JIT = false) const { if (!TargetMachineCtorFn) return nullptr; return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM, - CM, OL, JIT); + CM, OL, SL, JIT); } /// createMCAsmBackend - Create a target specific assembly parser. @@ -1085,8 +1087,9 @@ static TargetMachine * Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT) { - return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT); + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) { + return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT); } }; Index: include/llvm/Target/TargetMachine.h =================================================================== --- include/llvm/Target/TargetMachine.h +++ include/llvm/Target/TargetMachine.h @@ -82,6 +82,7 @@ Reloc::Model RM = Reloc::Static; CodeModel::Model CMModel = CodeModel::Small; CodeGenOpt::Level OptLevel = CodeGenOpt::Default; + CodeGenSizeOpt::Level SizeOptLevel = CodeGenSizeOpt::None; /// Contains target specific asm information. const MCAsmInfo *AsmInfo; @@ -195,9 +196,16 @@ /// Returns the optimization level: None, Less, Default, or Aggressive. CodeGenOpt::Level getOptLevel() const; + /// Returns the size optimization level: None, OptSize, or MinSize. + /// Default is None. + CodeGenSizeOpt::Level getSizeOptLevel() const; + /// \brief Overrides the optimization level. void setOptLevel(CodeGenOpt::Level Level); + /// Overrides the size optimization level. + void setSizeOptLevel(CodeGenSizeOpt::Level Level); + void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } bool getO0WantsFastISel() { return O0WantsFastISel; } void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; } @@ -301,7 +309,8 @@ LLVMTargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TargetTriple, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, - CodeModel::Model CM, CodeGenOpt::Level OL); + CodeModel::Model CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL); void initAsmInfo(); Index: lib/CodeGen/LLVMTargetMachine.cpp =================================================================== --- lib/CodeGen/LLVMTargetMachine.cpp +++ lib/CodeGen/LLVMTargetMachine.cpp @@ -78,11 +78,13 @@ const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL) : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { this->RM = RM; this->CMModel = CM; this->OptLevel = OL; + this->SizeOptLevel = SL; if (EnableTrapUnreachable) this->Options.TrapUnreachable = true; Index: lib/CodeGen/TargetPassConfig.cpp =================================================================== --- lib/CodeGen/TargetPassConfig.cpp +++ lib/CodeGen/TargetPassConfig.cpp @@ -383,6 +383,10 @@ return TM->getOptLevel(); } +CodeGenSizeOpt::Level TargetPassConfig::getSizeOptLevel() const { + return TM->getSizeOptLevel(); +} + /// Insert InsertedPassID pass after TargetPassID. void TargetPassConfig::insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, Index: lib/ExecutionEngine/TargetSelect.cpp =================================================================== --- lib/ExecutionEngine/TargetSelect.cpp +++ lib/ExecutionEngine/TargetSelect.cpp @@ -92,10 +92,9 @@ } // Allocate a target... - TargetMachine *Target = - TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr, - Options, RelocModel, CMModel, OptLevel, - /*JIT*/ true); + TargetMachine *Target = TheTarget->createTargetMachine( + TheTriple.getTriple(), MCPU, FeaturesStr, Options, RelocModel, CMModel, + OptLevel, CodeGenSizeOpt::None, /*JIT*/ true); Target->Options.EmulatedTLS = EmulatedTLS; Target->Options.ExplicitEmulatedTLS = true; Index: lib/Target/AArch64/AArch64TargetMachine.h =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.h +++ lib/Target/AArch64/AArch64TargetMachine.h @@ -32,7 +32,8 @@ AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT, bool IsLittleEndian); ~AArch64TargetMachine() override; const AArch64Subtarget *getSubtargetImpl(const Function &F) const override; @@ -62,7 +63,8 @@ AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, + Optional CM, + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; @@ -74,7 +76,8 @@ AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, + Optional CM, + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; Index: lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.cpp +++ lib/Target/AArch64/AArch64TargetMachine.cpp @@ -252,12 +252,13 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT, + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT, bool LittleEndian) : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions, LittleEndian), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(TT, CM, JIT), OL), + getEffectiveCodeModel(TT, CM, JIT), OL, SL), TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { initAsmInfo(); @@ -300,16 +301,20 @@ AArch64leTargetMachine::AArch64leTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT) - : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true) + {} void AArch64beTargetMachine::anchor() { } AArch64beTargetMachine::AArch64beTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT) - : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) + {} namespace { Index: lib/Target/AMDGPU/AMDGPUTargetMachine.h =================================================================== --- lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -85,7 +85,7 @@ R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; @@ -108,7 +108,7 @@ GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; Index: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -416,8 +416,9 @@ TargetOptions Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL) { setRequiresStructuredCFG(true); } @@ -450,8 +451,9 @@ TargetOptions Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, SL, OL, SL) {} const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const { StringRef GPU = getGPUName(F); Index: lib/Target/ARC/ARCTargetMachine.h =================================================================== --- lib/Target/ARC/ARCTargetMachine.h +++ lib/Target/ARC/ARCTargetMachine.h @@ -29,7 +29,7 @@ ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~ARCTargetMachine() override; const ARCSubtarget *getSubtargetImpl() const { return &Subtarget; } Index: lib/Target/ARC/ARCTargetMachine.cpp =================================================================== --- lib/Target/ARC/ARCTargetMachine.cpp +++ lib/Target/ARC/ARCTargetMachine.cpp @@ -38,7 +38,8 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" "f32:32:32-i64:32-f64:32-a:0:32-n32", Index: lib/Target/ARM/ARMTargetMachine.h =================================================================== --- lib/Target/ARM/ARMTargetMachine.h +++ lib/Target/ARM/ARMTargetMachine.h @@ -43,7 +43,7 @@ ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool isLittle); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool isLittle); ~ARMBaseTargetMachine() override; const ARMSubtarget *getSubtargetImpl(const Function &F) const override; @@ -70,7 +70,7 @@ ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; /// ARM/Thumb big endian target machine. @@ -80,7 +80,7 @@ ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; } // end namespace llvm Index: lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- lib/Target/ARM/ARMTargetMachine.cpp +++ lib/Target/ARM/ARMTargetMachine.cpp @@ -207,10 +207,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool isLittle) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, + bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM), OL), + getEffectiveCodeModel(CM), OL, SL), TargetABI(computeTargetABI(TT, CPU, Options)), TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { @@ -298,16 +300,18 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, true) {} ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, false) {} namespace { Index: lib/Target/AVR/AVRTargetMachine.h =================================================================== --- lib/Target/AVR/AVRTargetMachine.h +++ lib/Target/AVR/AVRTargetMachine.h @@ -32,7 +32,7 @@ StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); const AVRSubtarget *getSubtargetImpl() const; const AVRSubtarget *getSubtargetImpl(const Function &) const override; Index: lib/Target/AVR/AVRTargetMachine.cpp =================================================================== --- lib/Target/AVR/AVRTargetMachine.cpp +++ lib/Target/AVR/AVRTargetMachine.cpp @@ -51,10 +51,11 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), - OL), + OL, SL), SubTarget(TT, getCPU(CPU), FS, *this) { this->TLOF = make_unique(); initAsmInfo(); Index: lib/Target/BPF/BPFTargetMachine.h =================================================================== --- lib/Target/BPF/BPFTargetMachine.h +++ lib/Target/BPF/BPFTargetMachine.h @@ -26,7 +26,7 @@ BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } const BPFSubtarget *getSubtargetImpl(const Function &) const override { Index: lib/Target/BPF/BPFTargetMachine.cpp =================================================================== --- lib/Target/BPF/BPFTargetMachine.cpp +++ lib/Target/BPF/BPFTargetMachine.cpp @@ -62,10 +62,11 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), - OL), + OL, SL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); Index: lib/Target/Hexagon/HexagonTargetMachine.h =================================================================== --- lib/Target/Hexagon/HexagonTargetMachine.h +++ lib/Target/Hexagon/HexagonTargetMachine.h @@ -31,7 +31,7 @@ HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~HexagonTargetMachine() override; const HexagonSubtarget *getSubtargetImpl(const Function &F) const override; Index: lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- lib/Target/Hexagon/HexagonTargetMachine.cpp +++ lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -207,7 +207,8 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) // Specify the vector alignment explicitly. For v512x1, the calculated // alignment would be 512*alignment(i1), which is 512 bytes, instead of // the required minimum of 64 bytes. @@ -217,7 +218,8 @@ "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", TT, CPU, FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)), + getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL), + (HexagonNoOpt ? CodeGenSizeOpt::None : SL)), TLOF(make_unique()) { initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); initAsmInfo(); Index: lib/Target/MSP430/MSP430TargetMachine.h =================================================================== --- lib/Target/MSP430/MSP430TargetMachine.h +++ lib/Target/MSP430/MSP430TargetMachine.h @@ -31,7 +31,7 @@ MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~MSP430TargetMachine() override; const MSP430Subtarget *getSubtargetImpl(const Function &F) const override { Index: lib/Target/MSP430/MSP430TargetMachine.cpp =================================================================== --- lib/Target/MSP430/MSP430TargetMachine.cpp +++ lib/Target/MSP430/MSP430TargetMachine.cpp @@ -48,10 +48,11 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), OL), + getEffectiveCodeModel(CM), OL, SL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); Index: lib/Target/Mips/MipsTargetMachine.h =================================================================== --- lib/Target/Mips/MipsTargetMachine.h +++ lib/Target/Mips/MipsTargetMachine.h @@ -41,7 +41,7 @@ MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT, bool isLittle); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT, bool isLittle); ~MipsTargetMachine() override; TargetTransformInfo getTargetTransformInfo(const Function &F) override; @@ -81,7 +81,7 @@ MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; /// Mips32/64 little endian target machine. @@ -93,7 +93,7 @@ MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); }; } // end namespace llvm Index: lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- lib/Target/Mips/MipsTargetMachine.cpp +++ lib/Target/Mips/MipsTargetMachine.cpp @@ -114,11 +114,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT, + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), - getEffectiveCodeModel(CM), OL), + getEffectiveCodeModel(CM), OL, SL), isLittle(isLittle), TLOF(llvm::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, @@ -140,8 +141,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {} void MipselTargetMachine::anchor() {} @@ -150,8 +152,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true) {} const MipsSubtarget * MipsTargetMachine::getSubtargetImpl(const Function &F) const { Index: lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.h +++ lib/Target/NVPTX/NVPTXTargetMachine.h @@ -76,7 +76,8 @@ NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); }; class NVPTXTargetMachine64 : public NVPTXTargetMachine { @@ -85,7 +86,8 @@ NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); }; } // end namespace llvm Index: lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -105,11 +105,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool is64bit) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool is64bit) // The pic relocation model is used regardless of what the client has // specified, as it is the only relocation model currently supported. : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, - Reloc::PIC_, getEffectiveCodeModel(CM), OL), + Reloc::PIC_, getEffectiveCodeModel(CM), OL, SL), is64bit(is64bit), TLOF(llvm::make_unique()), Subtarget(TT, CPU, FS, *this) { if (TT.getOS() == Triple::NVCL) @@ -130,8 +131,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, false) {} void NVPTXTargetMachine64::anchor() {} @@ -140,8 +142,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, true) {} namespace { Index: lib/Target/Nios2/Nios2TargetMachine.h =================================================================== --- lib/Target/Nios2/Nios2TargetMachine.h +++ lib/Target/Nios2/Nios2TargetMachine.h @@ -27,7 +27,7 @@ Nios2TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~Nios2TargetMachine() override; const Nios2Subtarget *getSubtargetImpl() const { return &Subtarget; } Index: lib/Target/Nios2/Nios2TargetMachine.cpp =================================================================== --- lib/Target/Nios2/Nios2TargetMachine.cpp +++ lib/Target/Nios2/Nios2TargetMachine.cpp @@ -49,11 +49,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine( T, computeDataLayout(), TT, CPU, FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL), + getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL, SL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); Index: lib/Target/PowerPC/PPCTargetMachine.h =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.h +++ lib/Target/PowerPC/PPCTargetMachine.h @@ -36,7 +36,7 @@ PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~PPCTargetMachine() override; Index: lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.cpp +++ lib/Target/PowerPC/PPCTargetMachine.cpp @@ -238,11 +238,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, computeFSAdditions(FS, OL, TT), Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(TT, CM, JIT), OL), + getEffectiveCodeModel(TT, CM, JIT), OL, SL), TLOF(createTLOF(getTargetTriple())), TargetABI(computeTargetABI(TT, Options)) { initAsmInfo(); Index: lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- lib/Target/RISCV/RISCVTargetMachine.h +++ lib/Target/RISCV/RISCVTargetMachine.h @@ -29,7 +29,7 @@ RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); const RISCVSubtarget *getSubtargetImpl(const Function &) const override { return &Subtarget; Index: lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- lib/Target/RISCV/RISCVTargetMachine.cpp +++ lib/Target/RISCV/RISCVTargetMachine.cpp @@ -56,10 +56,11 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM), OL), + getEffectiveCodeModel(CM), OL, SL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); Index: lib/Target/Sparc/SparcTargetMachine.h =================================================================== --- lib/Target/Sparc/SparcTargetMachine.h +++ lib/Target/Sparc/SparcTargetMachine.h @@ -29,7 +29,8 @@ SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT, bool is64bit); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT, bool is64bit); ~SparcTargetMachine() override; const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -54,7 +55,8 @@ SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); }; /// Sparc 64-bit target machine @@ -65,7 +67,8 @@ SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); }; class SparcelTargetMachine : public SparcTargetMachine { @@ -75,7 +78,8 @@ SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); }; } // end namespace llvm Index: lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- lib/Target/Sparc/SparcTargetMachine.cpp +++ lib/Target/Sparc/SparcTargetMachine.cpp @@ -87,12 +87,13 @@ SparcTargetMachine::SparcTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT, bool is64bit) : LLVMTargetMachine( T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT), - OL), + OL, SL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { initAsmInfo(); @@ -189,8 +190,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {} void SparcV9TargetMachine::anchor() { } @@ -199,8 +201,9 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true) {} void SparcelTargetMachine::anchor() {} @@ -209,5 +212,6 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {} Index: lib/Target/SystemZ/SystemZTargetMachine.h =================================================================== --- lib/Target/SystemZ/SystemZTargetMachine.h +++ lib/Target/SystemZ/SystemZTargetMachine.h @@ -33,7 +33,8 @@ SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, + bool JIT); ~SystemZTargetMachine() override; const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } Index: lib/Target/SystemZ/SystemZTargetMachine.cpp =================================================================== --- lib/Target/SystemZ/SystemZTargetMachine.cpp +++ lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -142,7 +142,8 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine( T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, getEffectiveRelocModel(RM), Index: lib/Target/TargetMachine.cpp =================================================================== --- lib/Target/TargetMachine.cpp +++ lib/Target/TargetMachine.cpp @@ -236,6 +236,16 @@ void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; } +/// Returns the size optimization level: None, OptSize, or MinSize. +/// By default, returns None. +CodeGenSizeOpt::Level TargetMachine::getSizeOptLevel() const { + return SizeOptLevel; +} + +void TargetMachine::setSizeOptLevel(CodeGenSizeOpt::Level Level) { + SizeOptLevel = Level; +} + TargetTransformInfo TargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(F.getParent()->getDataLayout()); } Index: lib/Target/TargetMachineC.cpp =================================================================== --- lib/Target/TargetMachineC.cpp +++ lib/Target/TargetMachineC.cpp @@ -100,10 +100,11 @@ return unwrap(T)->hasMCAsmBackend(); } -LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, - const char *Triple, const char *CPU, const char *Features, - LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, - LLVMCodeModel CodeModel) { +LLVMTargetMachineRef +LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, + const char *Features, LLVMCodeGenOptLevel Level, + LLVMCodeGenSizeOptLevel SizeLevel, LLVMRelocMode Reloc, + LLVMCodeModel CodeModel) { Optional RM; switch (Reloc){ case LLVMRelocStatic: @@ -138,9 +139,22 @@ break; } + CodeGenSizeOpt::Level SL; + switch (SizeLevel) { + case LLVMCodeGenSizeLevelNone: + SL = CodeGenSizeOpt::None; + break; + case LLVMCodeGenSizeLevelOptSize: + SL = CodeGenSizeOpt::OptSize; + break; + case LLVMCodeGenSizeLevelMinSize: + SL = CodeGenSizeOpt::MinSize; + break; + } + TargetOptions opt; return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM, - OL, JIT)); + OL, SL, JIT)); } void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) { delete unwrap(T); } Index: lib/Target/WebAssembly/WebAssemblyTargetMachine.h =================================================================== --- lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -30,7 +30,7 @@ StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, - bool JIT); + CodeGenSizeOpt::Level SL, bool JIT); ~WebAssemblyTargetMachine() override; const WebAssemblySubtarget * Index: lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -88,12 +88,13 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, - Optional CM, CodeGenOpt::Level OL, bool JIT) + Optional CM, CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine(T, TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128", TT, CPU, FS, Options, getEffectiveRelocModel(RM), - CM ? *CM : CodeModel::Large, OL), + CM ? *CM : CodeModel::Large, OL, SL), TLOF(TT.isOSBinFormatELF() ? static_cast( new WebAssemblyTargetObjectFileELF()) : Index: lib/Target/X86/X86TargetMachine.h =================================================================== --- lib/Target/X86/X86TargetMachine.h +++ lib/Target/X86/X86TargetMachine.h @@ -36,7 +36,7 @@ X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~X86TargetMachine() override; const X86Subtarget *getSubtargetImpl(const Function &F) const override; Index: lib/Target/X86/X86TargetMachine.cpp =================================================================== --- lib/Target/X86/X86TargetMachine.cpp +++ lib/Target/X86/X86TargetMachine.cpp @@ -209,11 +209,13 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine( T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL), + getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), + OL, SL), TLOF(createTLOF(getTargetTriple())) { // Windows stack unwinder gets confused when execution flow "falls through" // after a call to 'noreturn' function. Index: lib/Target/XCore/XCoreTargetMachine.h =================================================================== --- lib/Target/XCore/XCoreTargetMachine.h +++ lib/Target/XCore/XCoreTargetMachine.h @@ -32,7 +32,7 @@ XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT); + CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT); ~XCoreTargetMachine() override; const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } Index: lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- lib/Target/XCore/XCoreTargetMachine.cpp +++ lib/Target/XCore/XCoreTargetMachine.cpp @@ -47,11 +47,12 @@ const TargetOptions &Options, Optional RM, Optional CM, - CodeGenOpt::Level OL, bool JIT) + CodeGenOpt::Level OL, + CodeGenSizeOpt::Level SL, bool JIT) : LLVMTargetMachine( T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", TT, CPU, FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), OL), + getEffectiveCodeModel(CM), OL, SL), TLOF(llvm::make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); Index: unittests/CodeGen/MachineInstrTest.cpp =================================================================== --- unittests/CodeGen/MachineInstrTest.cpp +++ unittests/CodeGen/MachineInstrTest.cpp @@ -68,7 +68,8 @@ public: BogusTargetMachine() : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(), - Reloc::Static, CodeModel::Small, CodeGenOpt::Default), + Reloc::Static, CodeModel::Small, CodeGenOpt::Default, + CodeGenSizeOpt::None), ST(*this) {} ~BogusTargetMachine() override {}