Index: lib/Target/AMDGPU/AMDGPUInstructionSelector.h =================================================================== --- lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -51,6 +51,7 @@ bool selectG_CONSTANT(MachineInstr &I) const; bool selectG_ADD(MachineInstr &I) const; bool selectG_GEP(MachineInstr &I) const; + bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; bool hasVgprParts(ArrayRef AddrInfo) const; void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, SmallVectorImpl &AddrInfo) const; Index: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -97,6 +97,10 @@ } } +static int64_t getConstant(const MachineInstr *MI) { + return MI->getOperand(1).getCImm()->getSExtValue(); +} + bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); @@ -144,6 +148,72 @@ return selectG_ADD(I); } +static MachineInstr * +buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, + unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, + unsigned VM, bool Compr, unsigned Enabled, bool Done) { + DebugLoc DL = Insert->getDebugLoc(); + MachineBasicBlock &BB = *Insert->getParent(); + unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP; + return BuildMI(BB, Insert, DL, TII.get(Opcode)) + .addImm(Tgt) + .addReg(Reg0) + .addReg(Reg1) + .addReg(Reg2) + .addReg(Reg3) + .addImm(VM) + .addImm(Compr) + .addImm(Enabled); +} + +bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( + MachineInstr &I) const { + MachineBasicBlock *BB = I.getParent(); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + DebugLoc DL = I.getDebugLoc(); + + unsigned IntrinsicID = I.getOperand(0).getIntrinsicID(); + switch (IntrinsicID) { + case Intrinsic::amdgcn_exp: { + int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); + int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg())); + int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(7).getReg())); + int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(8).getReg())); + + MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(), + I.getOperand(4).getReg(), + I.getOperand(5).getReg(), + I.getOperand(6).getReg(), + VM, false, Enabled, Done); + + // operands to use appropriate classes. + bool Ret = constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); + + I.eraseFromParent(); + return Ret; + } + case Intrinsic::amdgcn_exp_compr: { + int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); + int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg())); + unsigned Reg0 = I.getOperand(3).getReg(); + unsigned Reg1 = I.getOperand(4).getReg(); + unsigned Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(5).getReg())); + int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(6).getReg())); + + BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef); + MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, + true, Enabled, Done); + bool Ret = constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); + + I.eraseFromParent(); + return Ret; + } + } + return false; +} + bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); DebugLoc DL = I.getDebugLoc(); @@ -550,6 +620,8 @@ return selectG_CONSTANT(I); case TargetOpcode::G_GEP: return selectG_GEP(I); + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + return selectG_INTRINSIC_W_SIDE_EFFECTS(I); case TargetOpcode::G_LOAD: return selectG_LOAD(I); case TargetOpcode::G_STORE: Index: test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir @@ -0,0 +1,37 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + define void @exp0() { ret void } +... + +--- +name: exp0 +legalized: true +regBankSelected: true + +# CHECK: name: exp0 +body: | + bb.0: + liveins: $vgpr0 + %0:vgpr(s32) = COPY $vgpr0 + %1:sgpr(s32) = G_CONSTANT i32 1 + %2:sgpr(s32) = G_CONSTANT i32 15 + %3:sgpr(s1) = G_CONSTANT i1 0 + %4:sgpr(s1) = G_CONSTANT i1 1 + + ; CHECK: EXP 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: EXP_DONE 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %4:sgpr(s1), %3:sgpr(s1) + + %5:vgpr(<2 x s16>) = G_BITCAST %0(s32) + + ; CHECK: [[UNDEF0:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP 1, %0, %0, [[UNDEF0]], [[UNDEF0]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: [[UNDEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP_DONE 1, %0, %0, [[UNDEF1]], [[UNDEF1]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %4:sgpr(s1), %3:sgpr(s1) +