Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -506,19 +506,24 @@ template bool isSImm() const { return isSImmScaled(); } - template bool isSImmScaled() const { + template + DiagnosticPredicate isSImmScaled() const { if (!isImm()) - return false; + return DiagnosticPredicateTy::NoMatch; + const MCConstantExpr *MCE = dyn_cast(getImm()); if (!MCE) - return false; + return DiagnosticPredicateTy::NoMatch; int64_t Shift = Bits - 1; int64_t MinVal = (int64_t(1) << Shift) * -Scale; int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale; int64_t Val = MCE->getValue(); - return Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0; + if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; } bool isSVEPattern() const { @@ -859,10 +864,16 @@ template - bool isSVEVectorRegWithShiftExtend() const { - return Kind == k_Register && isSVEVectorRegOfWidth() && - ShiftExtendTy == getShiftExtendType() && - getShiftExtendAmount() == Log2_32(ShiftWidth / 8); + DiagnosticPredicate isSVEVectorRegWithShiftExtend() const { + if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) + return DiagnosticPredicateTy::NoMatch; + + if (isSVEVectorRegOfWidth() && + ShiftExtendTy == getShiftExtendType() && + getShiftExtendAmount() == Log2_32(ShiftWidth / 8)) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; } bool isGPR32as64() const { @@ -899,12 +910,14 @@ } template - bool isGPR64WithShiftExtend() const { - if (!isGPR64()) - return false; - - return getShiftExtendType() == AArch64_AM::LSL && - getShiftExtendAmount() == Log2_32(ExtWidth / 8); + DiagnosticPredicate isGPR64WithShiftExtend() const { + if (Kind != k_Register || Reg.Kind != RegKind::Scalar) + return DiagnosticPredicateTy::NoMatch; + + if (isGPR64() && getShiftExtendType() == AArch64_AM::LSL && + getShiftExtendAmount() == Log2_32(ExtWidth / 8)) + return DiagnosticPredicateTy::Match; + return DiagnosticPredicateTy::NearMatch; } /// Is this a vector list with the type implicit (presumably attached to the Index: llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -91,22 +91,22 @@ // Invalid scalar + scalar addressing modes ld1b z0.b, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -115,41 +115,41 @@ // Invalid scalar + vector addressing modes ld1b z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.s, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.s, p0/z, [x0, z0.s, uxtw #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.s, p0/z, [x0, z0.s, lsl #0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s, lsl #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.d, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.d, sxtw #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, sxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -46,27 +46,27 @@ // Invalid scalar + scalar addressing modes ld1d z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -75,17 +75,17 @@ // Invalid scalar + vector addressing modes ld1d z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -76,27 +76,27 @@ // Invalid scalar + scalar addressing modes ld1h z0.h, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -105,36 +105,36 @@ // Invalid scalar + vector addressing modes ld1h z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.s, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -90,22 +90,22 @@ // Invalid scalar + scalar addressing modes ld1sb z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -113,41 +113,41 @@ // Invalid scalar + vector addressing modes ld1sb z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.s, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.s, p0/z, [x0, z0.s, lsl #0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, lsl #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.d, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -75,27 +75,27 @@ // Invalid scalar + scalar addressing modes ld1sh z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -104,36 +104,36 @@ // Invalid scalar + vector addressing modes ld1sh z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -60,27 +60,27 @@ // Invalid scalar + scalar addressing modes ld1sw z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -89,27 +89,27 @@ // Invalid scalar + vector addressing modes ld1sw z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -119,11 +119,11 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -61,27 +61,27 @@ // Invalid scalar + scalar addressing modes ld1w z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -90,36 +90,36 @@ // Invalid scalar + vector addressing modes ld1w z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, z0.s, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.d, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -30,22 +30,22 @@ // Invalid scalar + scalar addressing modes ldff1d z0.d, p0/z, [x0, sp] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.d, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -25,22 +25,22 @@ // Invalid scalar + scalar addressing modes ldff1sh z0.s, p0/z, [x0, sp] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, sp] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.s, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -20,22 +20,22 @@ // Invalid scalar + scalar addressing modes ldff1sw z0.d, p0/z, [x0, sp] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, sp] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -30,22 +30,22 @@ // Invalid scalar + scalar addressing modes ldff1w z0.s, p0/z, [x0, sp] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, sp] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.s, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: