Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -506,19 +506,28 @@ template bool isSImm() const { return isSImmScaled(); } - template bool isSImmScaled() const { + template bool isMemoryIndexSImm7() const { + return (bool) isSImmScaled<7, 4>(); + } + + template + DiagnosticPredicate isSImmScaled() const { if (!isImm()) - return false; + return DiagnosticPredicateTy::NoMatch; + const MCConstantExpr *MCE = dyn_cast(getImm()); if (!MCE) - return false; + return DiagnosticPredicateTy::NoMatch; int64_t Shift = Bits - 1; int64_t MinVal = (int64_t(1) << Shift) * -Scale; int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale; int64_t Val = MCE->getValue(); - return Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0; + if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; } bool isSVEPattern() const { @@ -891,12 +900,14 @@ } template - bool isGPR64WithShiftExtend() const { - if (!isGPR64()) - return false; - - return getShiftExtendType() == AArch64_AM::LSL && - getShiftExtendAmount() == Log2_32(ExtWidth / 8); + DiagnosticPredicate isGPR64WithShiftExtend() const { + if (Kind != k_Register) + return DiagnosticPredicateTy::NoMatch; + + if (isGPR64() && getShiftExtendType() == AArch64_AM::LSL && + getShiftExtendAmount() == Log2_32(ExtWidth / 8)) + return DiagnosticPredicateTy::Match; + return DiagnosticPredicateTy::NearMatch; } /// Is this a vector list with the type implicit (presumably attached to the Index: test/MC/AArch64/SVE/ld1b-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1b-diagnostics.s +++ test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -91,21 +91,21 @@ // Invalid scalar + scalar addressing modes ld1b z0.b, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1d-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1d-diagnostics.s +++ test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -46,26 +46,26 @@ // Invalid scalar + scalar addressing modes ld1d z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1h-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1h-diagnostics.s +++ test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -76,26 +76,26 @@ // Invalid scalar + scalar addressing modes ld1h z0.h, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1sb-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -90,21 +90,21 @@ // Invalid scalar + scalar addressing modes ld1sb z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1sh-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -75,26 +75,26 @@ // Invalid scalar + scalar addressing modes ld1sh z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1sw-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -60,26 +60,26 @@ // Invalid scalar + scalar addressing modes ld1sw z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/ld1w-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ld1w-diagnostics.s +++ test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -61,26 +61,26 @@ // Invalid scalar + scalar addressing modes ld1w z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: