Index: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -305,6 +305,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSyncI_MM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1649,6 +1654,19 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1127,7 +1127,7 @@ bit HasSideEffects = 1; } -class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> { +class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> { let DecoderMethod = "DecodeSynciR6"; } Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td @@ -600,8 +600,9 @@ } class SYNCI_FM_MM : MMArch { - bits<5> rs; - bits<16> offset; + bits<21> addr; + bits<5> rs = addr{20-16}; + bits<16> offset = addr{15-0}; bits<32> Inst; let Inst{31-26} = 0b010000; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -128,6 +128,7 @@ let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops ptr_rc, simm16); let EncoderMethod = "getMemEncodingMMImm16"; + let DecoderMethod = "DecodeMemMMImm16"; let ParserMatchClass = MipsMemSimm16AsmOperand; let OperandType = "OPERAND_MEMORY"; } @@ -960,11 +961,13 @@ } def B_MM : UncondBranch, IsBranch, ISA_MICROMIPS; let DecoderNamespace = "MicroMips" in { - let Predicates = [InMicroMips] in { /// Control Instructions - def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; - def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM; + def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS; + let DecoderMethod = "DecodeSyncI_MM" in + def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM, + ISA_MICROMIPS32_NOT_MIPS32R6; + let Predicates = [InMicroMips] in { def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM; def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; @@ -1222,6 +1225,8 @@ (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; + def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS; + defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS; defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1657,8 +1657,8 @@ InstSE<(outs), (ins uimm5:$stype), "sync $stype", [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>; -class SYNCI_FT : - InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], +class SYNCI_FT : + InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [], II_SYNCI, FrmOther, opstr> { let hasSideEffects = 1; let DecoderMethod = "DecodeSyncI"; @@ -2050,7 +2050,8 @@ } def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; - def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; + def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM, + ISA_MIPS32R2; } let AdditionalPredicates = [NotInMicroMips] in { @@ -2641,8 +2642,8 @@ ISA_MIPS32R2; } def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; -def : MipsInstAlias<"sync", - (SYNC 0), 1>, ISA_MIPS2; +let AdditionalPredicates = [NotInMicroMips] in + def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; def : MipsInstAlias<"mulo $rs, $rt", (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -224,3 +224,5 @@ 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 +0x07 0x00 0x7c 0x6b # CHECK: sync 7 +0x03 0x42 0x00 0x04 # CHECK: synci 1024($3) Index: llvm/trunk/test/MC/Mips/micromips/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/valid.s +++ llvm/trunk/test/MC/Mips/micromips/valid.s @@ -282,7 +282,12 @@ # CHECK-NEXT: #