This is an archive of the discontinued LLVM Phabricator instance.

Differential D45443

[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
ClosedPublic

Authored by dp on Apr 9 2018, 8:58 AM.

Details

Reviewers
arsenm
artem.tamazov
timcorringham
Commits
rGfc715551a356: [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
rL329801: [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
Summary

See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845

Note that V_MOVRELS_B32 has the same encoding as V_SCREEN_PARTITION_4SE_B32 (but the former is not supported by GFX9).

This patch also corrects V_MOVREL* opcodes which have no SDWA/DPP variants.

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Apr 9 2018, 8:58 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptApr 9 2018, 8:58 AM
artem.tamazov accepted this revision.Apr 9 2018, 12:00 PM

LGTM

This revision is now accepted and ready to land.Apr 9 2018, 12:00 PM
Closed by commit rL329801: [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 (authored by dpreobra). · Explain WhyApr 11 2018, 6:16 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 11 2018, 6:16 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
34 lines
test/
MC/
AMDGPU/
16 lines
8 lines
5 lines
11 lines
Disassembler/
AMDGPU/
4 lines
3 lines
6 lines
3 lines

Diff 141991

llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td

Show First 20 Lines • Show All 376 Lines • ▼ Show 20 Lines
let SubtargetPredicate = isGFX9 in { let SubtargetPredicate = isGFX9 in {
let Constraints = "$vdst = $src1, $vdst1 = $src0", let Constraints = "$vdst = $src1, $vdst1 = $src0",
DisableEncoding="$vdst1,$src1", DisableEncoding="$vdst1,$src1",
SchedRW = [Write64Bit, Write64Bit] in { SchedRW = [Write64Bit, Write64Bit] in {
// Never VOP3. Takes as long as 2 v_mov_b32s // Never VOP3. Takes as long as 2 v_mov_b32s
def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>; def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>;
} }
defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>; defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>; defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>; defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
} // End SubtargetPredicate = isGFX9 } // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target // Target
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
multiclass VOP1Only_Real_vi <bits<10> op> { multiclass VOP1Only_Real_vi <bits<10> op> {
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _vi : def _vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>, VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>; VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
} }
} }
multiclass VOP1_Real_vi <bits<10> op> { multiclass VOP1_Real_e32e64_vi <bits<10> op> {
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _e32_vi : def _e32_vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>; VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
def _e64_vi : def _e64_vi :
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
VOP3e_vi <!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; VOP3e_vi <!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
} }
}
multiclass VOP1_Real_vi <bits<10> op> {
defm NAME : VOP1_Real_e32e64_vi <op>;
def _sdwa_vi : def _sdwa_vi :
VOP_SDWA_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>, VOP_SDWA_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
VOP1_SDWAe <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; VOP1_SDWAe <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
def _sdwa_gfx9 : def _sdwa_gfx9 :
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>, VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
defm V_FFBL_B32 : VOP1_Real_vi <0x2e>; defm V_FFBL_B32 : VOP1_Real_vi <0x2e>;
defm V_FFBH_I32 : VOP1_Real_vi <0x2f>; defm V_FFBH_I32 : VOP1_Real_vi <0x2f>;
defm V_FREXP_EXP_I32_F64 : VOP1_Real_vi <0x30>; defm V_FREXP_EXP_I32_F64 : VOP1_Real_vi <0x30>;
defm V_FREXP_MANT_F64 : VOP1_Real_vi <0x31>; defm V_FREXP_MANT_F64 : VOP1_Real_vi <0x31>;
defm V_FRACT_F64 : VOP1_Real_vi <0x32>; defm V_FRACT_F64 : VOP1_Real_vi <0x32>;
defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>; defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>;
defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>; defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>;
defm V_CLREXCP : VOP1_Real_vi <0x35>; defm V_CLREXCP : VOP1_Real_vi <0x35>;
defm V_MOVRELD_B32 : VOP1_Real_vi <0x36>; defm V_MOVRELD_B32 : VOP1_Real_e32e64_vi <0x36>;
defm V_MOVRELS_B32 : VOP1_Real_vi <0x37>; defm V_MOVRELS_B32 : VOP1_Real_e32e64_vi <0x37>;
defm V_MOVRELSD_B32 : VOP1_Real_vi <0x38>; defm V_MOVRELSD_B32 : VOP1_Real_e32e64_vi <0x38>;
defm V_TRUNC_F64 : VOP1_Real_vi <0x17>; defm V_TRUNC_F64 : VOP1_Real_vi <0x17>;
defm V_CEIL_F64 : VOP1_Real_vi <0x18>; defm V_CEIL_F64 : VOP1_Real_vi <0x18>;
defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>; defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>;
defm V_RNDNE_F64 : VOP1_Real_vi <0x19>; defm V_RNDNE_F64 : VOP1_Real_vi <0x19>;
defm V_LOG_LEGACY_F32 : VOP1_Real_vi <0x4c>; defm V_LOG_LEGACY_F32 : VOP1_Real_vi <0x4c>;
defm V_EXP_LEGACY_F32 : VOP1_Real_vi <0x4b>; defm V_EXP_LEGACY_F32 : VOP1_Real_vi <0x4b>;
defm V_CVT_F16_U16 : VOP1_Real_vi <0x39>; defm V_CVT_F16_U16 : VOP1_Real_vi <0x39>;
defm V_CVT_F16_I16 : VOP1_Real_vi <0x3a>; defm V_CVT_F16_I16 : VOP1_Real_vi <0x3a>;
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
>; >;
def : GCNPat < def : GCNPat <
(i16 (trunc i64:$src)), (i16 (trunc i64:$src)),
(EXTRACT_SUBREG $src, sub0) (EXTRACT_SUBREG $src, sub0)
>; >;
} // End OtherPredicates = [isVI] } // End OtherPredicates = [isVI]
//===----------------------------------------------------------------------===//
// GFX9
//===----------------------------------------------------------------------===//
multiclass VOP1_Real_gfx9 <bits<10> op> {
let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
defm NAME : VOP1_Real_e32e64_vi <op>;
}
def _sdwa_gfx9 :
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
// For now left dpp only for asm/dasm
// TODO: add corresponding pseudo
def _dpp : VOP1_DPP<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>;
}
defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>;

llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s

Show All 33 Lines
v_sat_pk_u8_i16 v5, -1 v_sat_pk_u8_i16 v5, -1
// GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e] // GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
// NOVI: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16 v5, 0x3f717273 v_sat_pk_u8_i16 v5, 0x3f717273
// GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f] // GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
// NOVI: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU
v_screen_partition_4se_b32 v5, v255
// GFX9: v_screen_partition_4se_b32_e32 v5, v255 ; encoding: [0xff,0x6f,0x0a,0x7e]
// NOVI: :1: error: instruction not supported on this GPU
v_screen_partition_4se_b32 v5, s101
// GFX9: v_screen_partition_4se_b32_e32 v5, s101 ; encoding: [0x65,0x6e,0x0a,0x7e]
// NOVI: :1: error: instruction not supported on this GPU
v_screen_partition_4se_b32 v5, -1
// GFX9: v_screen_partition_4se_b32_e32 v5, -1 ; encoding: [0xc1,0x6e,0x0a,0x7e]
// NOVI: :1: error: instruction not supported on this GPU
v_screen_partition_4se_b32 v5, 0x3f717273
// GFX9: v_screen_partition_4se_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
// NOVI: :1: error: instruction not supported on this GPU

llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s

Show First 20 Lines • Show All 439 Lines • ▼ Show 20 Lines
v_sat_pk_u8_i16_e64 v5, -1 v_sat_pk_u8_i16_e64 v5, -1
// GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00] // GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
// NOVI: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16_e64 v5, v255 v_sat_pk_u8_i16_e64 v5, v255
// GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00] // GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
// NOVI: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU
v_screen_partition_4se_b32_e64 v5, v1
// GXF9: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
v_screen_partition_4se_b32_e64 v5, -1
// GXF9: [0x05,0x00,0x77,0xd1,0xc1,0x00,0x00,0x00]
// NOVI: error: instruction not supported on this GPU

llvm/trunk/test/MC/AMDGPU/vop_dpp.s

Show First 20 Lines • Show All 344 Lines • ▼ Show 20 Lines
// NOVI: error // NOVI: error
v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
// GFX9: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00] // GFX9: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
// NOSICI: error // NOSICI: error
// NOVI: error // NOVI: error
v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
// NOSICI: error:
// NOVI: error:
// GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Check VOP2 opcodes // Check VOP2 opcodes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp) // ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp)
// NOSICI: error: // NOSICI: error:
// VI9: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff] // VI9: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff]
v_mac_f32 v0, v0, v0 row_shl:1 v_mac_f32 v0, v0, v0 row_shl:1
▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AMDGPU/vop_sdwa.s

Show First 20 Lines • Show All 1,051 Lines • ▼ Show 20 Lines
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02]
v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02]
v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
No newline at end of file
//---------------------------------------------------------------------------//
// Check Instructions
//---------------------------------------------------------------------------//
// NOSICI: error:
// NOVI: error:
// GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00]
v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0

llvm/trunk/test/MC/Disassembler/AMDGPU/dpp_gfx9.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f

llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Lines
0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00 0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00
# GFX9: v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00] # GFX9: v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00]
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00 0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00
# GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00] # GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00 0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00
# GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00]
0xf9 0x6e 0x0a 0x7e 0x01 0x16 0x00 0x00
#-----------------------------------------------------------------------------# #-----------------------------------------------------------------------------#
# VOP2 # VOP2
#-----------------------------------------------------------------------------# #-----------------------------------------------------------------------------#
# GFX9: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x06] # GFX9: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x06]
0xf9 0x00 0x00 0x02 0x00 0x06 0x05 0x06 0xf9 0x00 0x00 0x02 0x00 0x06 0x05 0x06
# GFX9: v_min_f32_sdwa v0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x36,0x06,0x02] # GFX9: v_min_f32_sdwa v0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x36,0x06,0x02]
▲ Show 20 Lines • Show All 370 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt

Show All 17 Lines
# GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e] # GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e]
0xff,0x9f,0x0a,0x7e 0xff,0x9f,0x0a,0x7e
# GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e] # GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
0xc1,0x9e,0x0a,0x7e 0xc1,0x9e,0x0a,0x7e
# GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f] # GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f 0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f
# GFX9: v_screen_partition_4se_b32_e32 v5, s101 ; encoding: [0x65,0x6e,0x0a,0x7e]
0x65,0x6e,0x0a,0x7e
# GFX9: v_screen_partition_4se_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

Show First 20 Lines • Show All 686 Lines • ▼ Show 20 Lines
# GFX9: v_cvt_norm_u16_f16_e64 v5, v255 ; encoding: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00] # GFX9: v_cvt_norm_u16_f16_e64 v5, v255 ; encoding: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]
0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00 0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00
# GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00] # GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00 0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00
# GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00] # GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00 0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00
# GXF9: v_screen_partition_4se_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00