Index: lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP1Instructions.td +++ lib/Target/AMDGPU/VOP1Instructions.td @@ -382,6 +382,8 @@ def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>; } +defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>; + defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>; defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>; defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>; @@ -515,7 +517,7 @@ } } -multiclass VOP1_Real_vi op> { +multiclass VOP1_Real_e32e64_vi op> { let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { def _e32_vi : VOP1_Real(NAME#"_e32"), SIEncodingFamily.VI>, @@ -524,6 +526,10 @@ VOP3_Real(NAME#"_e64"), SIEncodingFamily.VI>, VOP3e_vi (NAME#"_e64").Pfl>; } +} + +multiclass VOP1_Real_vi op> { + defm NAME : VOP1_Real_e32e64_vi ; def _sdwa_vi : VOP_SDWA_Real (NAME#"_sdwa")>, @@ -587,9 +593,9 @@ defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>; defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>; defm V_CLREXCP : VOP1_Real_vi <0x35>; -defm V_MOVRELD_B32 : VOP1_Real_vi <0x36>; -defm V_MOVRELS_B32 : VOP1_Real_vi <0x37>; -defm V_MOVRELSD_B32 : VOP1_Real_vi <0x38>; +defm V_MOVRELD_B32 : VOP1_Real_e32e64_vi <0x36>; +defm V_MOVRELS_B32 : VOP1_Real_e32e64_vi <0x37>; +defm V_MOVRELSD_B32 : VOP1_Real_e32e64_vi <0x38>; defm V_TRUNC_F64 : VOP1_Real_vi <0x17>; defm V_CEIL_F64 : VOP1_Real_vi <0x18>; defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>; @@ -692,3 +698,23 @@ >; } // End OtherPredicates = [isVI] + +//===----------------------------------------------------------------------===// +// GFX9 +//===----------------------------------------------------------------------===// + +multiclass VOP1_Real_gfx9 op> { + let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in { + defm NAME : VOP1_Real_e32e64_vi ; + } + + def _sdwa_gfx9 : + VOP_SDWA9_Real (NAME#"_sdwa")>, + VOP1_SDWA9Ae (NAME#"_sdwa").Pfl>; + + // For now left dpp only for asm/dasm + // TODO: add corresponding pseudo + def _dpp : VOP1_DPP(NAME#"_e32")>; +} + +defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>; Index: test/MC/AMDGPU/vop1-gfx9.s =================================================================== --- test/MC/AMDGPU/vop1-gfx9.s +++ test/MC/AMDGPU/vop1-gfx9.s @@ -39,3 +39,19 @@ v_sat_pk_u8_i16 v5, 0x3f717273 // GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f] // NOVI: error: instruction not supported on this GPU + +v_screen_partition_4se_b32 v5, v255 +// GFX9: v_screen_partition_4se_b32_e32 v5, v255 ; encoding: [0xff,0x6f,0x0a,0x7e] +// NOVI: :1: error: instruction not supported on this GPU + +v_screen_partition_4se_b32 v5, s101 +// GFX9: v_screen_partition_4se_b32_e32 v5, s101 ; encoding: [0x65,0x6e,0x0a,0x7e] +// NOVI: :1: error: instruction not supported on this GPU + +v_screen_partition_4se_b32 v5, -1 +// GFX9: v_screen_partition_4se_b32_e32 v5, -1 ; encoding: [0xc1,0x6e,0x0a,0x7e] +// NOVI: :1: error: instruction not supported on this GPU + +v_screen_partition_4se_b32 v5, 0x3f717273 +// GFX9: v_screen_partition_4se_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f] +// NOVI: :1: error: instruction not supported on this GPU Index: test/MC/AMDGPU/vop3-gfx9.s =================================================================== --- test/MC/AMDGPU/vop3-gfx9.s +++ test/MC/AMDGPU/vop3-gfx9.s @@ -445,3 +445,11 @@ v_sat_pk_u8_i16_e64 v5, v255 // GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00] // NOVI: error: instruction not supported on this GPU + +v_screen_partition_4se_b32_e64 v5, v1 +// GXF9: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +v_screen_partition_4se_b32_e64 v5, -1 +// GXF9: [0x05,0x00,0x77,0xd1,0xc1,0x00,0x00,0x00] +// NOVI: error: instruction not supported on this GPU Index: test/MC/AMDGPU/vop_dpp.s =================================================================== --- test/MC/AMDGPU/vop_dpp.s +++ test/MC/AMDGPU/vop_dpp.s @@ -350,6 +350,11 @@ // NOVI: error v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 +// NOSICI: error: +// NOVI: error: +// GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00] +v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 + //===----------------------------------------------------------------------===// // Check VOP2 opcodes //===----------------------------------------------------------------------===// Index: test/MC/AMDGPU/vop_sdwa.s =================================================================== --- test/MC/AMDGPU/vop_sdwa.s +++ test/MC/AMDGPU/vop_sdwa.s @@ -1057,4 +1057,13 @@ // NOSICI: error: // NOVI: error: // GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02] -v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 \ No newline at end of file +v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 + +//---------------------------------------------------------------------------// +// Check Instructions +//---------------------------------------------------------------------------// + +// NOSICI: error: +// NOVI: error: +// GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00] +v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0 Index: test/MC/Disassembler/AMDGPU/dpp_gfx9.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/AMDGPU/dpp_gfx9.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9 + +# GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f] +0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f Index: test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt =================================================================== --- test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt +++ test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt @@ -242,6 +242,9 @@ # GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00] 0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00 +# GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00] +0xf9 0x6e 0x0a 0x7e 0x01 0x16 0x00 0x00 + #-----------------------------------------------------------------------------# # VOP2 #-----------------------------------------------------------------------------# Index: test/MC/Disassembler/AMDGPU/vop1_gfx9.txt =================================================================== --- test/MC/Disassembler/AMDGPU/vop1_gfx9.txt +++ test/MC/Disassembler/AMDGPU/vop1_gfx9.txt @@ -23,3 +23,9 @@ # GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f] 0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f + +# GFX9: v_screen_partition_4se_b32_e32 v5, s101 ; encoding: [0x65,0x6e,0x0a,0x7e] +0x65,0x6e,0x0a,0x7e + +# GFX9: v_screen_partition_4se_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f] +0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f Index: test/MC/Disassembler/AMDGPU/vop3_gfx9.txt =================================================================== --- test/MC/Disassembler/AMDGPU/vop3_gfx9.txt +++ test/MC/Disassembler/AMDGPU/vop3_gfx9.txt @@ -692,3 +692,6 @@ # GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00] 0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00 + +# GXF9: v_screen_partition_4se_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00] +0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00