Index: lib/Target/X86/X86InstrCMovSetCC.td =================================================================== --- lib/Target/X86/X86InstrCMovSetCC.td +++ lib/Target/X86/X86InstrCMovSetCC.td @@ -16,7 +16,7 @@ // CMOV instructions. multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> { let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - isCommutable = 1, SchedRW = [WriteALU] in { + isCommutable = 1, SchedRW = [WriteCMOV] in { def NAME#16rr : I, TB, Sched<[WriteALU]>; + IIC_SET_R>, TB, Sched<[WriteSETCC]>; def m : I, TB, Sched<[WriteALU, WriteStore]>; + IIC_SET_M>, TB, Sched<[WriteSETCCStore]>; } // Uses = [EFLAGS] } Index: lib/Target/X86/X86SchedBroadwell.td =================================================================== --- lib/Target/X86/X86SchedBroadwell.td +++ lib/Target/X86/X86SchedBroadwell.td @@ -113,6 +113,9 @@ def : WriteRes; // LEA instructions can't fold loads. +defm : BWWriteResPair; // Conditional move. +def : WriteRes; // Setcc. + // Bit counts. defm : BWWriteResPair; defm : BWWriteResPair; @@ -469,7 +472,6 @@ "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -481,7 +483,6 @@ "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -791,13 +792,6 @@ } def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>; -def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1398,7 +1392,6 @@ let ResourceCycles = [1,1]; } def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", Index: lib/Target/X86/X86SchedHaswell.td =================================================================== --- lib/Target/X86/X86SchedHaswell.td +++ lib/Target/X86/X86SchedHaswell.td @@ -119,6 +119,9 @@ defm : HWWriteResPair; defm : HWWriteResPair; +defm : HWWriteResPair; // Conditional move. +def : WriteRes; // Setcc. + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. @@ -830,7 +833,6 @@ "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", "SARX(32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -1405,13 +1407,6 @@ } def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>; -def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[HWWriteResGroup22], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1568,7 +1563,6 @@ def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri", "ADC(8|16|32|64)rr", "ADC(8|16|32|64)i", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "SBB(8|16|32|64)ri", "SBB(8|16|32|64)rr", "SBB(8|16|32|64)i", @@ -1663,7 +1657,6 @@ let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>; def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, SBB8rm, SBB16rm, SBB32rm, SBB64rm)>; Index: lib/Target/X86/X86SchedSandyBridge.td =================================================================== --- lib/Target/X86/X86SchedSandyBridge.td +++ lib/Target/X86/X86SchedSandyBridge.td @@ -110,6 +110,9 @@ defm : SBWriteResPair; defm : SBWriteResPair; +defm : SBWriteResPair; // Conditional move. +def : WriteRes; // Setcc. + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. @@ -382,7 +385,6 @@ "SAHF", "SAR(8|16|32|64)ri", "SAR(8|16|32|64)r1", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)ri", "SHL(8|16|32|64)r1", "SHR(8|16|32|64)ri", @@ -624,7 +626,6 @@ def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri", "ADC(8|16|32|64)rr", "ADC(8|16|32|64)i", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "SBB(8|16|32|64)ri", "SBB(8|16|32|64)rr", "SBB(8|16|32|64)i", @@ -949,13 +950,6 @@ def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPD(Y?)mr", "VMASKMOVPS(Y?)mr")>; -def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup38], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> { let Latency = 5; let NumMicroOps = 3; @@ -1297,7 +1291,6 @@ let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>; def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, SBB8rm, SBB16rm, SBB32rm, SBB64rm)>; Index: lib/Target/X86/X86SchedSkylakeClient.td =================================================================== --- lib/Target/X86/X86SchedSkylakeClient.td +++ lib/Target/X86/X86SchedSkylakeClient.td @@ -113,6 +113,9 @@ def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. +defm : SKLWriteResPair; // Conditional move. +def : WriteRes; // Setcc. + // Bit counts. defm : SKLWriteResPair; defm : SKLWriteResPair; @@ -534,7 +537,6 @@ "BTS(16|32|64)ri8", "BTS(16|32|64)rr", "CLAC", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -546,7 +548,6 @@ "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -812,13 +813,6 @@ } def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>; -def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1421,7 +1415,6 @@ let ResourceCycles = [1,1]; } def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", Index: lib/Target/X86/X86SchedSkylakeServer.td =================================================================== --- lib/Target/X86/X86SchedSkylakeServer.td +++ lib/Target/X86/X86SchedSkylakeServer.td @@ -113,6 +113,9 @@ def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. +defm : SKXWriteResPair; // Conditional move. +def : WriteRes; // Setcc. + // Integer shifts and rotates. defm : SKXWriteResPair; @@ -1010,7 +1013,6 @@ "BTS(16|32|64)ri8", "BTS(16|32|64)rr", "CLAC", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -1022,7 +1024,6 @@ "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -1617,13 +1618,6 @@ } def: InstRW<[SKXWriteResGroup25], (instregex "FNSTCW16m")>; -def SKXWriteResGroup26 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SKXWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -3050,7 +3044,6 @@ let ResourceCycles = [1,1]; } def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", Index: lib/Target/X86/X86Schedule.td =================================================================== --- lib/Target/X86/X86Schedule.td +++ lib/Target/X86/X86Schedule.td @@ -39,9 +39,14 @@ } } +// Loads, stores, and moves, not folded with other operations. +def WriteLoad : SchedWrite; +def WriteStore : SchedWrite; +def WriteMove : SchedWrite; + // Arithmetic. defm WriteALU : X86SchedWritePair; // Simple integer ALU op. -def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>; +def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>; defm WriteIMul : X86SchedWritePair; // Integer multiplication. def WriteIMulH : SchedWrite; // Integer multiplication, high part. defm WriteIDiv : X86SchedWritePair; // Integer division. @@ -51,6 +56,9 @@ defm WritePOPCNT : X86SchedWritePair; // Bit population count. defm WriteLZCNT : X86SchedWritePair; // Leading zero count. defm WriteTZCNT : X86SchedWritePair; // Trailing zero count. +defm WriteCMOV : X86SchedWritePair; // Conditional move. +def WriteSETCC : SchedWrite; // Set register based on condition code. +def WriteSETCCStore : WriteSequence<[WriteSETCC, WriteStore]>; // Integer shifts and rotates. defm WriteShift : X86SchedWritePair; @@ -59,11 +67,6 @@ defm WriteBEXTR : X86SchedWritePair; defm WriteBZHI : X86SchedWritePair; -// Loads, stores, and moves, not folded with other operations. -def WriteLoad : SchedWrite; -def WriteStore : SchedWrite; -def WriteMove : SchedWrite; - // Idioms that clear a register, like xorps %xmm0, %xmm0. // These can often bypass execution ports completely. def WriteZero : SchedWrite; Index: lib/Target/X86/X86ScheduleBtVer2.td =================================================================== --- lib/Target/X86/X86ScheduleBtVer2.td +++ lib/Target/X86/X86ScheduleBtVer2.td @@ -141,6 +141,9 @@ defm : JWriteResIntPair; // Worst case (i64 division) defm : JWriteResIntPair; +defm : JWriteResIntPair; // Conditional move. +def : WriteRes; // Setcc. + def : WriteRes { let Latency = 6; let ResourceCycles = [4]; Index: lib/Target/X86/X86ScheduleSLM.td =================================================================== --- lib/Target/X86/X86ScheduleSLM.td +++ lib/Target/X86/X86ScheduleSLM.td @@ -93,6 +93,9 @@ defm : SLMWriteResPair; defm : SLMWriteResPair; +defm : SLMWriteResPair; +def : WriteRes; + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. Index: lib/Target/X86/X86ScheduleZnver1.td =================================================================== --- lib/Target/X86/X86ScheduleZnver1.td +++ lib/Target/X86/X86ScheduleZnver1.td @@ -153,6 +153,9 @@ defm : ZnWriteResPair; defm : ZnWriteResFpuPair; +defm : ZnWriteResPair; +def : WriteRes; + // Bit counts. defm : ZnWriteResPair; defm : ZnWriteResPair; @@ -277,14 +280,6 @@ // r,m. def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; -// CMOVcc. -// r,r. -def : InstRW<[WriteALU], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>; -// r,m. -def : InstRW<[WriteALULd, ReadAfterLd], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>; - // XCHG. // r,r. def ZnWriteXCHG : SchedWriteRes<[ZnALU]> { Index: test/CodeGen/X86/pr31045.ll =================================================================== --- test/CodeGen/X86/pr31045.ll +++ test/CodeGen/X86/pr31045.ll @@ -21,24 +21,24 @@ ; CHECK-NEXT: movl struct_obj_3+{{.*}}(%rip), %eax ; CHECK-NEXT: movsbl {{.*}}(%rip), %ecx ; CHECK-NEXT: movzbl {{.*}}(%rip), %edx +; CHECK-NEXT: movzbl {{.*}}(%rip), %esi ; CHECK-NEXT: andl $1, %eax -; CHECK-NEXT: leal (%rax,%rax), %esi -; CHECK-NEXT: subl %ecx, %esi -; CHECK-NEXT: subl %edx, %esi +; CHECK-NEXT: leal (%rax,%rax), %edi +; CHECK-NEXT: subl %ecx, %edi +; CHECK-NEXT: subl %edx, %edi ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: cmovel %eax, %ecx -; CHECK-NEXT: movzbl {{.*}}(%rip), %edx ; CHECK-NEXT: andl struct_obj_8+{{.*}}(%rip), %ecx ; CHECK-NEXT: andl $1, %ecx ; CHECK-NEXT: negl %ecx -; CHECK-NEXT: andl %edx, %ecx +; CHECK-NEXT: andl %esi, %ecx ; CHECK-NEXT: negl %ecx ; CHECK-NEXT: andl %eax, %ecx ; CHECK-NEXT: negl %ecx -; CHECK-NEXT: testl %ecx, %esi -; CHECK-NEXT: notl %esi -; CHECK-NEXT: movzbl %sil, %eax +; CHECK-NEXT: testl %ecx, %edi +; CHECK-NEXT: notl %edi +; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: movw %ax, struct_obj_12+{{.*}}(%rip) ; CHECK-NEXT: setne {{.*}}(%rip) ; CHECK-NEXT: retq Index: test/CodeGen/X86/schedule-x86_64.ll =================================================================== --- test/CodeGen/X86/schedule-x86_64.ll +++ test/CodeGen/X86/schedule-x86_64.ll @@ -13616,22 +13616,22 @@ ; SLM-NEXT: setge %dil # sched: [1:0.50] ; SLM-NEXT: setle %dil # sched: [1:0.50] ; SLM-NEXT: setg %dil # sched: [1:0.50] -; SLM-NEXT: seto (%rsi) # sched: [1:1.00] -; SLM-NEXT: setno (%rsi) # sched: [1:1.00] -; SLM-NEXT: setb (%rsi) # sched: [1:1.00] -; SLM-NEXT: setae (%rsi) # sched: [1:1.00] -; SLM-NEXT: sete (%rsi) # sched: [1:1.00] -; SLM-NEXT: setne (%rsi) # sched: [1:1.00] -; SLM-NEXT: setbe (%rsi) # sched: [1:1.00] -; SLM-NEXT: seta (%rsi) # sched: [1:1.00] -; SLM-NEXT: sets (%rsi) # sched: [1:1.00] -; SLM-NEXT: setns (%rsi) # sched: [1:1.00] -; SLM-NEXT: setp (%rsi) # sched: [1:1.00] -; SLM-NEXT: setnp (%rsi) # sched: [1:1.00] -; SLM-NEXT: setl (%rsi) # sched: [1:1.00] -; SLM-NEXT: setge (%rsi) # sched: [1:1.00] -; SLM-NEXT: setle (%rsi) # sched: [1:1.00] -; SLM-NEXT: setg (%rsi) # sched: [1:1.00] +; SLM-NEXT: seto (%rsi) # sched: [2:1.00] +; SLM-NEXT: setno (%rsi) # sched: [2:1.00] +; SLM-NEXT: setb (%rsi) # sched: [2:1.00] +; SLM-NEXT: setae (%rsi) # sched: [2:1.00] +; SLM-NEXT: sete (%rsi) # sched: [2:1.00] +; SLM-NEXT: setne (%rsi) # sched: [2:1.00] +; SLM-NEXT: setbe (%rsi) # sched: [2:1.00] +; SLM-NEXT: seta (%rsi) # sched: [2:1.00] +; SLM-NEXT: sets (%rsi) # sched: [2:1.00] +; SLM-NEXT: setns (%rsi) # sched: [2:1.00] +; SLM-NEXT: setp (%rsi) # sched: [2:1.00] +; SLM-NEXT: setnp (%rsi) # sched: [2:1.00] +; SLM-NEXT: setl (%rsi) # sched: [2:1.00] +; SLM-NEXT: setge (%rsi) # sched: [2:1.00] +; SLM-NEXT: setle (%rsi) # sched: [2:1.00] +; SLM-NEXT: setg (%rsi) # sched: [2:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -13844,22 +13844,22 @@ ; BTVER2-NEXT: setge %dil # sched: [1:0.50] ; BTVER2-NEXT: setle %dil # sched: [1:0.50] ; BTVER2-NEXT: setg %dil # sched: [1:0.50] -; BTVER2-NEXT: seto (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setno (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setb (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setae (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: sete (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setne (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setbe (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: seta (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: sets (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setns (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setp (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setnp (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setl (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setge (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setle (%rsi) # sched: [1:1.00] -; BTVER2-NEXT: setg (%rsi) # sched: [1:1.00] +; BTVER2-NEXT: seto (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setno (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setb (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setae (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: sete (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setne (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setbe (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: seta (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: sets (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setns (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setp (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setnp (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setl (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setge (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setle (%rsi) # sched: [2:1.00] +; BTVER2-NEXT: setg (%rsi) # sched: [2:1.00] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: retq # sched: [4:1.00] ;