Index: lib/Target/AArch64/AArch64InstrFormats.td =================================================================== --- lib/Target/AArch64/AArch64InstrFormats.td +++ lib/Target/AArch64/AArch64InstrFormats.td @@ -247,6 +247,17 @@ let DecoderMethod = "DecodeSImm<6>"; } +def SImm5Operand : SImmOperand<5>; +def simm5_64b : Operand, ImmLeaf= -16 && Imm < 16; }]> { + let ParserMatchClass = SImm5Operand; + let DecoderMethod = "DecodeSImm<5>"; +} + +def simm5_32b : Operand, ImmLeaf= -16 && Imm < 16; }]> { + let ParserMatchClass = SImm5Operand; + let DecoderMethod = "DecodeSImm<5>"; +} + // simm7sN predicate - True if the immediate is a multiple of N in the range // [-64 * N, 63 * N]. class SImm7Scaled : AsmOperandClass { Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -31,4 +31,9 @@ def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">; + + defm INDEX_RR : sve_int_index_rr<"index">; + defm INDEX_IR : sve_int_index_ir<"index">; + defm INDEX_RI : sve_int_index_ri<"index">; + defm INDEX_II : sve_int_index_ii<"index">; } Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3537,6 +3537,8 @@ "expected compatible register or floating-point constant"); case Match_InvalidMemoryIndexedSImm6: return Error(Loc, "index must be an integer in range [-32, 31]."); + case Match_InvalidMemoryIndexedSImm5: + return Error(Loc, "index must be an integer in range [-16, 15]."); case Match_InvalidMemoryIndexedSImm9: return Error(Loc, "index must be an integer in range [-256, 255]."); case Match_InvalidMemoryIndexedSImm10: @@ -4055,6 +4057,7 @@ case Match_InvalidMemoryIndexed4SImm7: case Match_InvalidMemoryIndexed8SImm7: case Match_InvalidMemoryIndexed16SImm7: + case Match_InvalidMemoryIndexedSImm5: case Match_InvalidMemoryIndexedSImm9: case Match_InvalidMemoryIndexedSImm10: case Match_InvalidImm0_1: Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -338,6 +338,107 @@ def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; } + +//===----------------------------------------------------------------------===// +//SVE Index Generation Group +//===----------------------------------------------------------------------===// + +class sve_int_index_ii sz8_64, string asm, ZPRRegOp zprty, + Operand imm_ty> +: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b), + asm, "\t$Zd, $imm5, $imm5b", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> imm5; + bits<5> imm5b; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = imm5b; + let Inst{15-10} = 0b010000; + let Inst{9-5} = imm5; + let Inst{4-0} = Zd; +} + +multiclass sve_int_index_ii { + def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>; + def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>; + def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>; + def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>; +} + +class sve_int_index_ir sz8_64, string asm, ZPRRegOp zprty, + RegisterClass srcRegType, Operand imm_ty> +: I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm), + asm, "\t$Zd, $imm5, $Rm", + "", []>, Sched<[]> { + bits<5> Rm; + bits<5> Zd; + bits<5> imm5; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Rm; + let Inst{15-10} = 0b010010; + let Inst{9-5} = imm5; + let Inst{4-0} = Zd; +} + +multiclass sve_int_index_ir { + def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>; + def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>; + def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>; + def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>; +} + +class sve_int_index_ri sz8_64, string asm, ZPRRegOp zprty, + RegisterClass srcRegType, Operand imm_ty> +: I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5), + asm, "\t$Zd, $Rn, $imm5", + "", []>, Sched<[]> { + bits<5> Rn; + bits<5> Zd; + bits<5> imm5; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = imm5; + let Inst{15-10} = 0b010001; + let Inst{9-5} = Rn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_index_ri { + def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>; + def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>; + def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>; + def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>; +} + +class sve_int_index_rr sz8_64, string asm, ZPRRegOp zprty, + RegisterClass srcRegType> +: I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm), + asm, "\t$Zd, $Rn, $Rm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Rm; + bits<5> Rn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Rm; + let Inst{15-10} = 0b010011; + let Inst{9-5} = Rn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_index_rr { + def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>; + def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; + def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>; + def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>; +} + //===----------------------------------------------------------------------===// // SVE Permute - Predicates Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE/index-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE/index-diagnostics.s @@ -0,0 +1,58 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate out of lower bound [-16, 15]. + +index z27.b, #-17, #-16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z27.b, #-17, #-16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z11.h, #-16, #-17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z11.h, #-16, #-17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z2.s, #16, #-16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z2.s, #16, #-16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z2.d, #-16, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z2.d, #-16, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z4.b, #-17, w28 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z4.b, #-17, w28 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z9.h, #16, w23 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z9.h, #16, w23 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z3.s, w10, #-17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z3.s, w10, #-17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z17.d, x9, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z17.d, x9, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid register + +index z17.s, x9, w7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z17.s, x9, w7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +index z17.d, w9, w7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. +// CHECK-NEXT: index z17.d, w9, w7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/index.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE/index.s @@ -0,0 +1,214 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +// --------------------------------------------------------------------------// +// Index (immediate, immediate) + +index z0.b, #0, #0 +// CHECK-INST: index z0.b, #0, #0 +// CHECK-ENCODING: [0x00,0x40,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 20 04 + +index z31.b, #-1, #-1 +// CHECK-INST: index z31.b, #-1, #-1 +// CHECK-ENCODING: [0xff,0x43,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 43 3f 04 + +index z0.h, #0, #0 +// CHECK-INST: index z0.h, #0, #0 +// CHECK-ENCODING: [0x00,0x40,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 60 04 + +index z31.h, #-1, #-1 +// CHECK-INST: index z31.h, #-1, #-1 +// CHECK-ENCODING: [0xff,0x43,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 43 7f 04 + +index z0.s, #0, #0 +// CHECK-INST: index z0.s, #0, #0 +// CHECK-ENCODING: [0x00,0x40,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 a0 04 + +index z31.s, #-1, #-1 +// CHECK-INST: index z31.s, #-1, #-1 +// CHECK-ENCODING: [0xff,0x43,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 43 bf 04 + +index z0.d, #0, #0 +// CHECK-INST: index z0.d, #0, #0 +// CHECK-ENCODING: [0x00,0x40,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 e0 04 + +index z31.d, #-1, #-1 +// CHECK-INST: index z31.d, #-1, #-1 +// CHECK-ENCODING: [0xff,0x43,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 43 ff 04 + +// --------------------------------------------------------------------------// +// Index (immediate, scalar) + +index z31.b, #-1, wzr +// CHECK-INST: index z31.b, #-1, wzr +// CHECK-ENCODING: [0xff,0x4b,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4b 3f 04 + +index z23.b, #13, w8 +// CHECK-INST: index z23.b, #13, w8 +// CHECK-ENCODING: [0xb7,0x49,0x28,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 49 28 04 + +index z31.h, #-1, wzr +// CHECK-INST: index z31.h, #-1, wzr +// CHECK-ENCODING: [0xff,0x4b,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4b 7f 04 + +index z23.h, #13, w8 +// CHECK-INST: index z23.h, #13, w8 +// CHECK-ENCODING: [0xb7,0x49,0x68,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 49 68 04 + +index z31.s, #-1, wzr +// CHECK-INST: index z31.s, #-1, wzr +// CHECK-ENCODING: [0xff,0x4b,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4b bf 04 + +index z23.s, #13, w8 +// CHECK-INST: index z23.s, #13, w8 +// CHECK-ENCODING: [0xb7,0x49,0xa8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 49 a8 04 + +index z31.d, #-1, xzr +// CHECK-INST: index z31.d, #-1, xzr +// CHECK-ENCODING: [0xff,0x4b,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4b ff 04 + +index z23.d, #13, x8 +// CHECK-INST: index z23.d, #13, x8 +// CHECK-ENCODING: [0xb7,0x49,0xe8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 49 e8 04 + + +// --------------------------------------------------------------------------// +// Index (scalar, immediate) + +index z31.b, wzr, #-1 +// CHECK-INST: index z31.b, wzr, #-1 +// CHECK-ENCODING: [0xff,0x47,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 47 3f 04 + +index z23.b, w13, #8 +// CHECK-INST: index z23.b, w13, #8 +// CHECK-ENCODING: [0xb7,0x45,0x28,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 45 28 04 + +index z31.h, wzr, #-1 +// CHECK-INST: index z31.h, wzr, #-1 +// CHECK-ENCODING: [0xff,0x47,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 47 7f 04 + +index z23.h, w13, #8 +// CHECK-INST: index z23.h, w13, #8 +// CHECK-ENCODING: [0xb7,0x45,0x68,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 45 68 04 + +index z31.s, wzr, #-1 +// CHECK-INST: index z31.s, wzr, #-1 +// CHECK-ENCODING: [0xff,0x47,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 47 bf 04 + +index z23.s, w13, #8 +// CHECK-INST: index z23.s, w13, #8 +// CHECK-ENCODING: [0xb7,0x45,0xa8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 45 a8 04 + +index z31.d, xzr, #-1 +// CHECK-INST: index z31.d, xzr, #-1 +// CHECK-ENCODING: [0xff,0x47,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 47 ff 04 + +index z23.d, x13, #8 +// CHECK-INST: index z23.d, x13, #8 +// CHECK-ENCODING: [0xb7,0x45,0xe8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 45 e8 04 + + +// --------------------------------------------------------------------------// +// Index (scalar, scalar) + +index z31.b, wzr, wzr +// CHECK-INST: index z31.b, wzr, wzr +// CHECK-ENCODING: [0xff,0x4f,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4f 3f 04 + +index z21.b, w10, w21 +// CHECK-INST: index z21.b, w10, w21 +// CHECK-ENCODING: [0x55,0x4d,0x35,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 4d 35 04 + +index z31.h, wzr, wzr +// check-inst: index z31.h, wzr, wzr +// check-encoding: [0xff,0x4f,0x7f,0x04] +// check-error: instruction requires: sve +// check-unknown: ff 4f 7f 04 + +index z0.h, w0, w0 +// check-inst: index z0.h, w0, w0 +// check-encoding: [0x00,0x4c,0x60,0x04] +// check-error: instruction requires: sve +// check-unknown: 00 4c 60 04 + +index z31.s, wzr, wzr +// CHECK-INST: index z31.s, wzr, wzr +// CHECK-ENCODING: [0xff,0x4f,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4f bf 04 + +index z21.s, w10, w21 +// CHECK-INST: index z21.s, w10, w21 +// CHECK-ENCODING: [0x55,0x4d,0xb5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 4d b5 04 + +index z31.d, xzr, xzr +// CHECK-INST: index z31.d, xzr, xzr +// CHECK-ENCODING: [0xff,0x4f,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 4f ff 04 + +index z21.d, x10, x21 +// CHECK-INST: index z21.d, x10, x21 +// CHECK-ENCODING: [0x55,0x4d,0xf5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 4d f5 04