Index: lib/Target/Mips/MipsScheduleGeneric.td =================================================================== --- lib/Target/Mips/MipsScheduleGeneric.td +++ lib/Target/Mips/MipsScheduleGeneric.td @@ -25,11 +25,11 @@ int HighLatency = 37; list UnsupportedFeatures = []; - let CompleteModel = 1; let PostRAScheduler = 1; - // FIXME: Remove when all errors have been fixed. - let FullInstRWOverlapCheck = 0; + let CompleteModel = 1; + + let FullInstRWOverlapCheck = 1; } let SchedModel = MipsGenericModel in { @@ -42,35 +42,115 @@ def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>; -// and, lui, nor, or, slti, sltiu, sub, subu, xor -// add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, -// xori -def : ItinRW<[GenericWriteALU], [II_ADD, II_ADDU, II_ADDI, II_ADDIU, II_ANDI, - II_AND, II_ANDI, II_CLO, II_CLZ, II_EXT, - II_INS, II_LUI, II_MULT, II_MULTU, II_NOR, - II_ORI, II_OR, II_ROTR, II_ROTRV, II_SEB, - II_SEH, II_SLTI_SLTIU, II_SLT_SLTU, II_SLL, - II_SRA, II_SRL, II_SLLV, II_SRAV, II_SRLV, - II_SSNOP, II_SUB, II_SUBU, II_WSBH, II_XOR, - II_XORI]>; +// add, addi, addiu, addu, and, andi, clo, clz, ext, ins, lui, nor, or, ori, +// rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, +// srlv, ssnop, sub, subu, wsbh, xor, xori +def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi, + CLO, CLZ, EXT, INS, LEA_ADDiu, LUi, + NOR, OR, ORi, ROTR, ROTRV, SEB, SEH, SLL, + SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL, + SRLV, SSNOP, SUB, SUBu, WSBH, XOR, XORi)>; def : InstRW<[GenericWriteALU], (instrs COPY)>; +// MIPSR6 +// ====== + +// addiupc, align, aluipc, aui, auipc, bitswap, clo, clz, lsa, seleqz, selnez +def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI, + AUIPC, BITSWAP, CLO_R6, CLZ_R6, LSA_R6, + SELEQZ, SELNEZ)>; + +// MIPS16e +// ======= + +def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16, + AddiuRxRxImmX16, AddiuRxRyOffMemX16, + AddiuRxPcImmX16, AddiuSpImm16, AddiuSpImmX16, + AdduRxRyRz16, AndRxRxRy16, CmpRxRy16, + CmpiRxImm16, CmpiRxImmX16, LiRxImm16, + LiRxImmX16, LiRxImmAlignX16, Move32R16, + MoveR3216, Mfhi16, Mflo16, NegRxRy16, + NotRxRy16, OrRxRxRy16, SebRx16, SehRx16, + SllX16, SllvRxRy16, SltiRxImm16, + SltiRxImmX16, SltiCCRxImmX16, + SltiuRxImm16, SltiuRxImmX16, SltiuCCRxImmX16, + SltRxRy16, SltCCRxRy16, SltuRxRy16, + SltuRxRyRz16, SltuCCRxRy16, SravRxRy16, + SraX16, SrlvRxRy16, SrlX16, SubuRxRyRz16, + XorRxRxRy16)>; + +// microMIPS +// ========= + +def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM, + ADDIUS5_MM, ADDIUSP_MM, ADDU16_MM, ADD_MM, + ADDi_MM, ADDiu_MM, ADDu_MM, AND16_MM, + ANDI16_MM, AND_MM, ANDi_MM, CLO_MM, CLZ_MM, + EXT_MM, INS_MM, LEA_ADDiu_MM, LI16_MM, + LUi_MM, MOVE16_MM, MOVEP_MM, NOR_MM, + NOT16_MM, OR16_MM, OR_MM, ORi_MM, ROTRV_MM, + ROTR_MM, SEB_MM, SEH_MM, SLL16_MM, SLLV_MM, + SLL_MM, SLT_MM, SLTi_MM, SLTiu_MM, SLTu_MM, + SRAV_MM, SRA_MM, SRL16_MM, SRLV_MM, SRL_MM, + SSNOP_MM, SUBU16_MM, SUB_MM, SUBu_MM, + WSBH_MM, XOR16_MM, XOR_MM, XORi_MM)>; + +// microMIPS32r6 +// ============= + +def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MMR6, ADDIU_MMR6, ADDU16_MMR6, + ADDU_MMR6, ADD_MMR6, ALIGN_MMR6, ALUIPC_MMR6, + AND16_MMR6, ANDI16_MMR6, ANDI_MMR6, AND_MMR6, + AUIPC_MMR6, AUI_MMR6, BITSWAP_MMR6, CLO_MMR6, + CLZ_MMR6, EXT_MMR6, INS_MMR6, LI16_MMR6, + LSA_MMR6, LUI_MMR6, MOVE16_MMR6, NOR_MMR6, + NOT16_MMR6, OR16_MMR6, ORI_MMR6, OR_MMR6, + SEB_MMR6, SEH_MMR6, SELEQZ_MMR6, SELNEZ_MMR6, + SLL16_MMR6, SLL_MMR6, SRL16_MMR6, SSNOP_MMR6, + SUBU16_MMR6, SUBU_MMR6, SUB_MMR6, WSBH_MMR6, + XOR16_MMR6, XORI_MMR6, XOR_MMR6)>; + +// MIPS64 +// ====== + +def : InstRW<[GenericWriteALU], (instrs AND64, ANDi64, DEXT64_32, DSLL64_32, + ORi64, SEB64, SEH64, SLL64_32, SLL64_64, + SLT64, SLTi64, SLTiu64, SLTu64, XOR64, + XORi64)>; + +def : InstRW<[GenericWriteALU], (instrs DADD, DADDi, DADDiu, DADDu, DCLO, + DCLZ, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, + DROTR, DROTR32, DROTRV, DSBH, DSHD, DSLL, + DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, + DSRL32, DSRLV, DSUB, DSUBu, LEA_ADDiu64, + LUi64, NOR64, OR64)>; + +// MIPS64R6 +// ======== + +def : InstRW<[GenericWriteALU], (instrs DALIGN, DAHI, DATI, DAUI, DCLO_R6, + DCLZ_R6, DBITSWAP, DLSA, DLSA_R6, SELEQZ64, + SELNEZ64)>; + + def GenericMDU : ProcResource<1> { let BufferSize = 1; } def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; } def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; } def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>; def GenericWriteALULong : SchedWriteRes<[GenericIssueALU]> { let Latency = 5; } def GenericWriteMove : SchedWriteRes<[GenericIssueALU]> { let Latency = 2; } +def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; } + +def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>; -def : ItinRW<[GenericWriteHILO], [II_MADD, II_MADDU, II_MSUB, II_MSUBU]>; +def : InstRW<[GenericWriteHILO], (instrs PseudoMADD, PseudoMADDU, PseudoMSUB, + PseudoMSUBU, PseudoMULT, PseudoMULTu)>; def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> { let Latency = 5; } -def : ItinRW<[GenericWriteMDUtoGPR], [II_MUL]>; - def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> { // Estimated worst case let Latency = 33; @@ -82,63 +162,102 @@ let ResourceCycles = [1, 31]; } -def : ItinRW<[GenericWriteDIV], [II_DIV]>; +// mul +def : InstRW<[GenericWriteMDUtoGPR], (instrs MUL)>; -def : ItinRW<[GenericWriteDIVU], [II_DIVU]>; +// mult, multu +def : InstRW<[GenericWriteMul], (instrs MULT, MULTu)>; -// MIPS64 -// ====== +// div, sdiv +def : InstRW<[GenericWriteDIV], (instrs PseudoSDIV, SDIV)>; + +def : InstRW<[GenericWriteDIVU], (instrs PseudoUDIV, UDIV)>; -def : ItinRW<[GenericWriteALU], [II_DADDIU, II_DADDU, II_DADDI, II_DADD, - II_DCLO, II_DCLZ, II_DROTR, II_DROTR32, - II_DROTRV, II_DSBH, II_DSHD, II_DSLL, - II_DSLL32, II_DSLLV, II_DSRA, II_DSRA32, - II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, - II_DSUBU, II_DSUB]>; +// mfhi, mflo, movn, mthi, mtlo, rdwhr +def : InstRW<[GenericWriteALULong], (instrs MFHI, MFLO, PseudoMFHI, + PseudoMFLO)>; -def : ItinRW<[GenericWriteDIV], [II_DDIV]>; +def : InstRW<[GenericWriteMove], (instrs MTHI, MTLO, RDHWR, PseudoMTLOHI)>; + +def : InstRW<[GenericWriteALU], (instrs MOVN_I_I, MOVZ_I_I)>; + +// MIPSR6 +// ====== -def : ItinRW<[GenericWriteDIVU], [II_DDIVU]>; +// muh, muhu, mulu, mul +def : InstRW<[GenericWriteMul], (instrs MUH, MUHU, MULU, MUL_R6)>; -def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUL]>; +// divu, udiv +def : InstRW<[GenericWriteDIV], (instrs MOD, MODU, DIV, DIVU)>; -def : ItinRW<[GenericWriteHILO], [II_DMULU, II_DMULT, II_DMULTU]>; // MIPS16e // ======= -def : ItinRW<[GenericWriteALU], [IIM16Alu, IIPseudo]>; +def : InstRW<[GenericWriteHILO], (instrs MultRxRy16, MultuRxRy16, + MultRxRyRz16, MultuRxRyRz16)>; + +def : InstRW<[GenericWriteDIV], (instrs DivRxRy16)>; + +def : InstRW<[GenericWriteDIVU], (instrs DivuRxRy16)>; // microMIPS // ========= -def : ItinRW<[GenericWriteALU], [II_MOVE, II_LI, II_NOT]>; +def : InstRW<[GenericWriteMul], (instrs MULT_MM, MULTu_MM, MADD_MM, MADDU_MM, + MSUB_MM, MSUBU_MM)>; -// MIPSR6 +def : InstRW<[GenericWriteALULong], (instrs MUL_MM)>; + +def : InstRW<[GenericWriteDIV], (instrs SDIV_MM, SDIV_MM_Pseudo)>; + +def : InstRW<[GenericWriteDIVU], (instrs UDIV_MM, UDIV_MM_Pseudo)>; + +def : InstRW<[GenericWriteMove], (instrs MFHI16_MM, MFLO16_MM, MOVF_I_MM, + MOVT_I_MM, MFHI_MM, MFLO_MM, MTHI_MM, + MTLO_MM)>; + +def : InstRW<[GenericWriteMove], (instrs RDHWR_MM)>; + +// microMIPS32r6 +// ============= + +def : InstRW<[GenericWriteMul], (instrs MUHU_MMR6, MUH_MMR6, MULU_MMR6, + MUL_MMR6)>; + +def : InstRW<[GenericWriteDIV], (instrs MODU_MMR6, MOD_MMR6, DIVU_MMR6, + DIV_MMR6)>; + +def : InstRW<[GenericWriteMove], (instrs RDHWR_MMR6)>; + +// MIPS64 // ====== -def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; } -def : ItinRW<[GenericWriteMul], [II_MUH, II_MUHU, II_MULU]>; +def : InstRW<[GenericWriteHILO], (instrs DMULU, DMULT, DMULTu, PseudoDMULT, + PseudoDMULTu)>; + +def : InstRW<[GenericWriteDIV], (instrs DSDIV, PseudoDSDIV)>; + +def : InstRW<[GenericWriteDIVU], (instrs DUDIV, PseudoDUDIV)>; + +def : InstRW<[GenericWriteALULong], (instrs MFHI64, MFLO64, PseudoMFHI64, + PseudoMFLO64, PseudoMTLOHI64)>; -def : ItinRW<[GenericWriteDIV], [II_MOD, II_MODU]>; +def : InstRW<[GenericWriteMove], (instrs MTHI64, MTLO64, RDHWR64)>; + +// mov[zn] +def : InstRW<[GenericWriteALU], (instrs MOVN_I_I64, MOVN_I64_I, MOVN_I64_I64, + MOVZ_I_I64, MOVZ_I64_I, MOVZ_I64_I64)>; -def : ItinRW<[GenericWriteALU], [II_ADDIUPC, II_ALIGN, II_ALUIPC, II_AUI, - II_AUIPC, II_BITSWAP, II_LSA, II_SELCCZ]>; // MIPS64R6 // ======== -def : ItinRW<[GenericWriteALU], [II_DALIGN, II_DAHI, II_DATI, II_DAUI, - II_DBITSWAP, II_DLSA]>; - -def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUH, II_DMUHU]>; -def : ItinRW<[GenericWriteDIV], [II_DMOD, II_DMODU]>; +def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>; -// clo, clz, di, mfhi, mflo -def : ItinRW<[GenericWriteALULong], [II_MFHI_MFLO]>; -def : ItinRW<[GenericWriteALU], [II_MOVN, II_MOVZ]>; -def : ItinRW<[GenericWriteMove], [II_MTHI_MTLO, II_RDHWR]>; +def : InstRW<[GenericWriteDIV], (instrs DDIV, DMOD)>; +def : InstRW<[GenericWriteDIVU], (instrs DDIVU, DMODU)>; // CTISTD Pipeline // --------------- @@ -155,31 +274,148 @@ // b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx, // jalr, jr.hb, jr, jalr.hb, jarlc, jialc -def : ItinRW<[GenericWriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, - II_JR, II_JR_HB, II_ERET, II_ERETNC, - II_DERET]>; +def : InstRW<[GenericWriteJump], (instrs B, BAL, BAL_BR, BEQ, BNE, BGTZ, BGEZ, + BLEZ, BLTZ, BLTZAL, J, JALX, JR, JR_HB, ERET, + ERETNC, DERET)>; + +def : InstRW<[GenericWriteJump], (instrs BEQL, BNEL, BGEZL, BGTZL, BLEZL, + BLTZL)>; -def : ItinRW<[GenericWriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB, - II_BC2CCZ]>; +def : InstRW<[GenericWriteJump], (instrs TAILCALL, TAILCALLREG, + TAILCALLREGHB, PseudoIndirectBranch, + PseudoIndirectHazardBranch, PseudoReturn)>; -def : ItinRW<[GenericWriteJump], [II_JRC, II_JRADDIUSP]>; +def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZAL, JAL, JALR, JALR_HB, + JALRHBPseudo, JALRPseudo)>; -def : ItinRW<[GenericWriteJumpAndLink], [II_BCCZALS, II_JALS, II_JALRS]>; +def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALL, BLTZALL)>; + + +def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; + +def : InstRW<[GenericWriteTrap], (instrs BREAK, SYSCALL, TEQ, TEQI, + TGE, TGEI, TGEIU, TGEU, TNE, + TNEI, TLT, TLTI, TLTU, TTLTIU, + TRAP, SDBBP)>; // MIPSR6 // ====== -def : ItinRW<[GenericWriteJumpAndLink], [II_BALC, II_JALRC, II_JIALC]>; +def : InstRW<[GenericWriteJumpAndLink], (instrs BALC, BEQZALC, BGEZALC, + BGTZALC, BLEZALC, BLTZALC, + BNEZALC, + JIALC)>; -def : ItinRW<[GenericWriteJump], [II_JIC, II_BC, II_BCCC, II_BCCZC]>; +def : InstRW<[GenericWriteJump], (instrs BC, BC2EQZ, BC2NEZ, BEQC, BEQZC, BGEC, + BGEUC, BGEZC, BGTZC, BLEZC, BLTC, BLTUC, + BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6, + PseudoIndirectBranchR6, + PseudoIndrectHazardBranchR6)>; +def : InstRW<[GenericWriteJump], (instrs TAILCALLR6REG, TAILCALLHBR6REG)>; -def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; +def : InstRW<[GenericWriteTrap], (instrs SDBBP_R6)>; + +// MIPS16e +// ======= + +def : InstRW<[GenericWriteJump], (instrs Bimm16, BimmX16, BeqzRxImm16, + BeqzRxImmX16, BnezRxImm16, BnezRxImmX16, + Bteqz16, BteqzX16, BteqzT8CmpX16, + BteqzT8CmpiX16, BteqzT8SltX16, + BteqzT8SltuX16, BteqzT8SltiX16, + BteqzT8SltiuX16, Btnez16, BtnezX16, + BtnezT8CmpX16, BtnezT8CmpiX16, + BtnezT8SltX16, BtnezT8SltuX16, + BtnezT8SltiX16, BtnezT8SltiuX16, JrRa16, + JrcRa16, JrcRx16)>; + +def : InstRW<[GenericWriteJumpAndLink], (instrs Jal16, JalB16, JumpLinkReg16)>; + +def : InstRW<[GenericWriteTrap], (instrs Break16)>; + +def : InstRW<[GenericWriteALULong], (instrs SelBeqZ, SelTBteqZCmp, + SelTBteqZCmpi, SelTBteqZSlt, + SelTBteqZSlti, SelTBteqZSltu, + SelTBteqZSltiu, SelBneZ, SelTBtneZCmp, + SelTBtneZCmpi, SelTBtneZSlt, + SelTBtneZSlti, SelTBtneZSltu, + SelTBtneZSltiu)>; + +// microMIPS +// ========= + +def : InstRW<[GenericWriteJump], (instrs B16_MM, BC1F_MM, BC1T_MM, BEQZ16_MM, + BEQZC_MM, BEQ_MM, BGEZ_MM, BGTZ_MM, BLEZ_MM, + BLTZ_MM, BNEZ16_MM, BNEZC_MM, BNE_MM, B_MM, + DERET_MM, ERET_MM, JR16_MM, JR_MM, J_MM)>; + +def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALS_MM, BGEZAL_MM, + BLTZALS_MM, BLTZAL_MM, JALR16_MM, + JALRS16_MM, JALRS_MM, JALR_MM, + JALS_MM, JALX_MM, JAL_MM)>; + +def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MM, TAILCALL_MM, + PseudoIndirectBranch_MM)>; + +def : InstRW<[GenericWriteTrap], (instrs BREAK16_MM, BREAK_MM, SDBBP16_MM, + SDBBP_MM, SYSCALL_MM, TEQI_MM, TEQ_MM, + TGEIU_MM, TGEI_MM, TGEU_MM, TGE_MM, TLTIU_MM, + TLTI_MM, TLTU_MM, TLT_MM, TNEI_MM, TNE_MM)>; + +// microMIPS32r6 +// ============= + +def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6, + BC2EQZC_MMR6, BC2NEZC_MMR6, BC_MMR6, + BEQC_MMR6, BEQZC16_MMR6, BEQZC_MMR6, + BGEC_MMR6, BGEUC_MMR6, BGEZC_MMR6, + BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6, + BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6, + BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, + BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, + ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, + JRC16_MMR6, JRCADDIUSP_MMR6, + PseudoIndirectBranch_MMR6)>; + +def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6, + BGEZALC_MMR6, BGTZALC_MMR6, + BLEZALC_MMR6, BLTZALC_MMR6, + BNEZALC_MMR6, JALRC16_MMR6, + JALRC_HB_MMR6, JALRC_MMR6, + JIALC_MMR6)>; + +def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MMR6, TAILCALL_MMR6)>; + +def : InstRW<[GenericWriteTrap], (instrs BREAK16_MMR6, BREAK_MMR6, SDBBP_MMR6, + SDBBP16_MMR6)>; + +// MIPS64 +// ====== + +def : InstRW<[GenericWriteJump], (instrs BEQ64, BGEZ64, BGTZ64, BLEZ64, + BLTZ64, BNE64, JR64)>; + +def : InstRW<[GenericWriteJumpAndLink], (instrs JALR64, JALR64Pseudo, + JALRHB64Pseudo, JALR_HB64)>; + +def : InstRW<[GenericWriteJump], (instrs JR_HB64, TAILCALLREG64, + TAILCALLREGHB64, PseudoReturn64)>; + +// MIPS64R6 +// ======== + +def : InstRW<[GenericWriteJump], (instrs BEQC64, BEQZC64, BGEC64, BGEUC64, + BGEZC64, BGTZC64, BLEZC64, BLTC64, BLTUC64, + BLTZC64, BNEC64, BNEZC64, JIC64, + PseudoIndirectBranch64, + PseudoIndirectHazardBranch64)>; -def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI, - II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE, - II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU, - II_TRAP, II_SDBBP]>; +def : InstRW<[GenericWriteJumpAndLink], (instrs JIALC64)>; + +def : InstRW<[GenericWriteJump], (instrs JR_HB64_R6, TAILCALL64R6REG, + TAILCALLHB64R6REG, PseudoIndirectBranch64R6, + PseudoIndrectHazardBranch64R6)>; // COP0 Pipeline // ============= @@ -196,35 +432,80 @@ } def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>; -def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>; -def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>; +def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP, TLBR, TLBWI, TLBWR)>; +def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV, TLBINVF)>; -def : ItinRW<[GenericReadCOP0], [II_MFC0]>; -def : ItinRW<[GenericWriteCOP0], [II_MTC0]>; +def : InstRW<[GenericReadCOP0], (instrs MFC0)>; +def : InstRW<[GenericWriteCOP0], (instrs MTC0)>; -def : ItinRW<[GenericWriteCOP0], [II_EVP, II_DVP]>; +def : InstRW<[GenericWriteCOP0], (instrs EVP, DVP)>; -// MIPSR5 -// ====== -def : ItinRW<[GenericReadCOP0], [II_MFHC0]>; -def : ItinRW<[GenericWriteCOP0], [II_MTHC0]>; +def : InstRW<[GenericWriteCOP0], (instrs DI, EI)>; + +def : InstRW<[GenericWriteCOP0], (instrs EHB, PAUSE, WAIT)>; + +// microMIPS +// ========= + +def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP_MM, TLBR_MM, TLBWI_MM, + TLBWR_MM)>; + +def : InstRW<[GenericWriteCOP0], (instrs DI_MM, EI_MM)>; + +def : InstRW<[GenericWriteCOP0], (instrs EHB_MM, PAUSE_MM, WAIT_MM)>; + + +// microMIPS32R6 +// ============= + +def : InstRW<[GenericWriteCOP0], (instrs RDPGPR_MMR6, WRPGPR_MMR6)>; + +def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV_MMR6, TLBINVF_MMR6)>; + +def : InstRW<[GenericReadCOP0], (instrs MFHC0_MMR6, MFC0_MMR6, MFHC2_MMR6, + MFC2_MMR6)>; + +def : InstRW<[GenericWriteCOP0], (instrs MTHC0_MMR6, MTC0_MMR6, MTHC2_MMR6, + MTC2_MMR6)>; + +def : InstRW<[GenericWriteCOP0], (instrs EVP_MMR6, DVP_MMR6)>; + +def : InstRW<[GenericWriteCOP0], (instrs DI_MMR6, EI_MMR6)>; + +def : InstRW<[GenericWriteCOP0], (instrs EHB_MMR6, PAUSE_MMR6, WAIT_MMR6)>; // MIPS64 // ====== -def : ItinRW<[GenericReadCOP0], [II_DMFC0]>; -def : ItinRW<[GenericWriteCOP0], [II_DMTC0]>; +def : InstRW<[GenericReadCOP0], (instrs DMFC0)>; -def : ItinRW<[GenericWriteCOP0], [II_RDPGPR, II_WRPGPR]>; +def : InstRW<[GenericWriteCOP0], (instrs DMTC0)>; -def : ItinRW<[GenericWriteCOP0], [II_DI, II_EI]>; - -def : ItinRW<[GenericWriteCOP0], [II_EHB, II_PAUSE, II_WAIT]>; def GenericCOP2 : ProcResource<1> { let BufferSize = 1; } def GenericWriteCOPOther : SchedWriteRes<[GenericCOP2]>; -def : ItinRW<[GenericWriteCOPOther], [II_MFC2, II_MTC2, II_DMFC2, II_DMTC2]>; +def : InstRW<[GenericWriteCOPOther], (instrs MFC2, MTC2)>; + +def : InstRW<[GenericWriteCOPOther], (instrs DMFC2, DMTC2)>; + +// microMIPS32R6 +// ============= + +// The latency and repeat rate of these instructions are implementation +// dependant. +def : InstRW<[GenericWriteMove], (instrs CFC2_MM, CTC2_MM)>; + + +// MIPS MT ASE - hasMT +// ==================== + +def : InstRW<[GenericWriteMove], (instrs DMT, DVPE, EMT, EVPE, MFTR, + MTTR)>; + +def : InstRW<[GenericReadWriteCOP0Long], (instrs YIELD)>; + +def : InstRW<[GenericWriteCOP0Short], (instrs FORK)>; // LDST Pipeline // ------------- @@ -250,97 +531,166 @@ } // l[bhw], l[bh]u, ll -def : ItinRW<[GenericWriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LL, - II_LWC2, II_LWC3, II_LDC2, II_LDC3]>; +def : InstRW<[GenericWriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, + LWC2, LWC3, LDC2, LDC3)>; // lw[lr] -def : ItinRW<[GenericWriteLoad], [II_LWL, II_LWR]>; +def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>; -// MIPS64 loads -def : ItinRW<[GenericWriteLoad], [II_LD, II_LLD, II_LWU]>; +// s[bhw], sc, s[dw]c[23] +def : InstRW<[GenericWriteStore], (instrs SB, SH, SW, SWC2, SWC3, + SDC2, SDC3)>; -// ld[lr] -def : ItinRW<[GenericWriteLoad], [II_LDL, II_LDR]>; +// PreMIPSR6 sw[lr] +def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>; -// MIPS32 EVA -def : ItinRW<[GenericWriteLoad], [II_LBE, II_LBUE, II_LHE, II_LHUE, II_LWE, - II_LLE]>; +def : InstRW<[GenericWriteStoreSC], (instrs SC)>; -def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>; +// pref +def : InstRW<[GenericWritePref], (instrs PREF)>; +// cache +def : InstRW<[GenericWriteCache], (instrs CACHE)>; -// MIPS MT instructions -// ==================== +// sync +def : InstRW<[GenericWriteSync], (instrs SYNC, SYNCI)>; -def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE, II_MFTR, - II_MTTR]>; +// MIPSR6 +// ====== -def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>; +def : InstRW<[GenericWriteLoad], (instrs LDC2_R6, LL_R6, LWC2_R6, LWPC)>; -def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>; +def : InstRW<[GenericWriteStore], (instrs SWC2_R6, SDC2_R6)>; -// MIPS32R6 and MIPS16e -// ==================== +def : InstRW<[GenericWriteStoreSC], (instrs SC_R6)>; -def : ItinRW<[GenericWriteLoad], [II_LWPC]>; +def : InstRW<[GenericWritePref], (instrs PREF_R6)>; -// MIPS64R6 -// ==================== +def : InstRW<[GenericWriteCache], (instrs CACHE_R6)>; -def : ItinRW<[GenericWriteLoad], [II_LWUPC, II_LDPC]>; +// MIPS32 EVA +// ========== +def : InstRW<[GenericWriteLoad], (instrs LBE, LBuE, LHE, LHuE, LWE, + LLE)>; -// s[bhw], sc, s[dw]c[23] -def : ItinRW<[GenericWriteStore], [II_SB, II_SH, II_SW, II_SWC2, II_SWC3, - II_SDC2, II_SDC3]>; +def : InstRW<[GenericWriteStore], (instrs SBE, SHE, SWE, SCE)>; -def : ItinRW<[GenericWriteStoreSC], [II_SC]>; +def : InstRW<[GenericWriteLoad], (instrs LWLE, LWRE)>; -// PreMIPSR6 sw[lr] -def : ItinRW<[GenericWriteStore], [II_SWL, II_SWR]>; +def : InstRW<[GenericWriteStore], (instrs SWLE, SWRE)>; -// EVA ASE stores -def : ItinRW<[GenericWriteStore], [II_SBE, II_SHE, II_SWE, II_SCE]>; +def : InstRW<[GenericWritePref], (instrs PREFE)>; -def : ItinRW<[GenericWriteStore], [II_SWLE, II_SWRE]>; +def : InstRW<[GenericWriteCache], (instrs CACHEE)>; -// MIPS64 -// ====== +// microMIPS EVA ASE - InMicroMipsMode, hasEVA +// =========================================== -def : ItinRW<[GenericWriteStore], [II_SD, II_SCD]>; +def : InstRW<[GenericWriteLoad], (instrs LBE_MM, LBuE_MM, LHE_MM, LHuE_MM, + LWE_MM, LWLE_MM, LWRE_MM, LLE_MM)>; -// PreMIPSR6 stores -// ================ +def : InstRW<[GenericWriteStore], (instrs SBE_MM, SB_MM, SHE_MM, SWE_MM, + SWLE_MM, SWRE_MM, SCE_MM)>; + +def : InstRW<[GenericWritePref], (instrs PREFE_MM)>; +def : InstRW<[GenericWriteCache], (instrs CACHEE_MM)>; -def : ItinRW<[GenericWriteStore], [II_SDL, II_SDR]>; // MIPS16e // ======= -def : ItinRW<[GenericWriteLoad], [II_RESTORE]>; +def : InstRW<[GenericWriteLoad], (instrs Restore16, RestoreX16, + LbRxRyOffMemX16, + LbuRxRyOffMemX16, LhRxRyOffMemX16, + LhuRxRyOffMemX16, LwRxRyOffMemX16, + LwRxSpImmX16, LwRxPcTcp16, LwRxPcTcpX16)>; -def : ItinRW<[GenericWriteStore], [II_SAVE]>; +def : InstRW<[GenericWriteStore], (instrs Save16, SaveX16, SbRxRyOffMemX16, + ShRxRyOffMemX16, SwRxRyOffMemX16, + SwRxSpImmX16)>; // microMIPS // ========= -def : ItinRW<[GenericWriteLoad], [II_LWM, II_LWP, II_LWXS]>; +def : InstRW<[GenericWriteLoad], (instrs LBU16_MM, LB_MM, LBu_MM, LHU16_MM, + LH_MM, LHu_MM, LL_MM, LW16_MM, LWGP_MM, + LWL_MM, LWM16_MM, LWM32_MM, LWP_MM, + LWP_MMR6, LWR_MM, LWSP_MM, LWU_MM, LWXS_MM, + LW_MM)>; -def : ItinRW<[GenericWriteStore], [II_SWM, II_SWP]>; +def : InstRW<[GenericWriteStore], (instrs SB16_MM, SC_MM, SH16_MM, SH_MM, + SW16_MM, SWL_MM, SWM16_MM, SWM32_MM, + SWP_MM, SWP_MMR6, SWR_MM, SWSP_MM, SW_MM)>; -// pref -def : ItinRW<[GenericWritePref], [II_PREF]>; -def : ItinRW<[GenericWritePref], [II_PREFE]>; +def : InstRW<[GenericWritePref], (instrs PREF_MM, PREFX_MM)>; -// cache -def : ItinRW<[GenericWriteCache], [II_CACHE]>; +def : InstRW<[GenericWriteCache], (instrs CACHE_MM)>; -def : ItinRW<[GenericWriteCache], [II_CACHEE]>; +def : InstRW<[GenericWriteSync], (instrs SYNC_MM, SYNCI_MM)>; -// sync -def : ItinRW<[GenericWriteSync], [II_SYNC]>; +// microMIPS32r6 +// ============= + +def : InstRW<[GenericWriteLoad], (instrs LBU_MMR6, LB_MMR6, LDC2_MMR6, + LWM16_MMR6, LWC2_MMR6, LWPC_MMR6, LW_MMR6)>; + +def : InstRW<[GenericWriteStore], (instrs SB16_MMR6, SB_MMR6, SDC2_MMR6, + SH16_MMR6, SH_MMR6, SW16_MMR6, SWC2_MMR6, + SWM16_MMR6, SWSP_MMR6, SW_MMR6)>; + +def : InstRW<[GenericWriteSync], (instrs SYNC_MMR6, SYNCI_MMR6)>; + +def : InstRW<[GenericWritePref], (instrs PREF_MMR6)>; + +def : InstRW<[GenericWriteCache], (instrs CACHE_MMR6)>; -def : ItinRW<[GenericWriteSync], [II_SYNCI]>; +// MIPS64 +// ====== + +def : InstRW<[GenericWriteLoad], (instrs LD, LL64, LLD, LWu, LB64, LBu64, + LH64, LHu64, LW64)>; + +// l[dw][lr] +def : InstRW<[GenericWriteLoad], (instrs LWL64, LWR64, LDL, LDR)>; + +def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64, + SWL64, SWR64)>; + +def : InstRW<[GenericWriteStore], (instrs SDL, SDR)>; + +// MIPS64R6 +// ======== + +def : InstRW<[GenericWriteLoad], (instrs LWUPC, LDPC)>; + +def : InstRW<[GenericWriteLoad], (instrs LLD_R6, LL64_R6)>; + +def : InstRW<[GenericWriteStoreSC], (instrs SC64_R6, SCD_R6)>; + +// MIPSR6 CRC ASE - hasCRC +// ======================= + +def : InstRW<[GenericWriteALU], (instrs CRC32B, CRC32H, CRC32W, CRC32CB, + CRC32CH, CRC32CW)>; + +// MIPS64R6 CRC ASE - hasCRC +// ------------------------- + +def : InstRW<[GenericWriteALU], (instrs CRC32D, CRC32CD)>; + + +// Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips +// ================================================= + +def : InstRW<[GenericWriteALU], (instrs BADDu, BBIT0, BBIT032, BBIT1, BBIT132, + CINS, CINS32, CINS64_32, CINS_i32, + DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS, + EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2, + POP, SEQ, SEQi, SNE, SNEi, V3MULU, VMM0, + VMULU)>; + +def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>; // FPU Pipelines // ============= @@ -408,10 +758,10 @@ // --------------------------------- // // c..[ds], bc1[tf], bc1[tf]l -def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC1F, II_BC1T, - II_BC1FL, II_BC1TL]>; +def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC1F, + BC1T, BC1FL, BC1TL)>; -def : ItinRW<[GenericWriteFPUCmp], [II_CMP_CC_D, II_CMP_CC_S]>; +def : InstRW<[GenericWriteFPUCmp], (instregex "C_[A-Z]+_(S|D32|D64)$")>; // Short Pipe // ---------- @@ -419,21 +769,10 @@ // abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s // nmsub.s, sub.[ds], mul.s -def : ItinRW<[GenericWriteFPUS], [II_ABS, II_ADD_D, II_ADD_S, II_MADD_S, - II_MSUB_S, II_MUL_S, II_NEG, II_NMADD_S, - II_NMSUB_S, II_SUB_S, II_SUB_D]>; -// mov[tf].[ds] - -def : ItinRW<[GenericWriteFPUS], [II_MOVF_S, II_MOVF_D, II_MOVT_S, II_MOVT_D]>; - -// MIPSR6 -// ------ -// -// sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds] -def : ItinRW<[GenericWriteFPUS], [II_SELCCZ_S, II_SELCCZ_D, II_MAX_S, - II_MAX_D, II_MAXA_S, II_MAXA_D, II_MIN_S, - II_MIN_D, II_MINA_S, II_MINA_D, II_CLASS_S, - II_CLASS_D]>; +def : InstRW<[GenericWriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, FADD_D32, + FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S, + FNEG_S, FNEG_D32, FNEG_D64, NMADD_S, NMSUB_S, + FSUB_S, FSUB_D32, FSUB_D64)>; // Long Pipe // ---------- @@ -445,71 +784,207 @@ // madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw], // cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds, // trunc.w.[ds], trunc.w.ps, -def : ItinRW<[GenericWriteFPUL], [II_MADD_D, II_MSUB_D, II_MUL_D, II_NMADD_D, - II_NMSUB_D, II_CEIL, II_CVT, - II_FLOOR, II_ROUND, II_TRUNC]>; +def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32, + CEIL_W_D64, CEIL_W_S, CVT_D32_S, CVT_D32_W, + CVT_D64_L, CVT_D64_S, CVT_D64_W, CVT_L_D64, + CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L, + CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S, + FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32, + FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64, + MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, + NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64, + ROUND_L_D64, ROUND_L_S, ROUND_W_D32, + ROUND_W_D64, ROUND_W_S, TRUNC_L_D64, + TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64, + TRUNC_W_S)>; + +// Pseudo convert instruction +def : InstRW<[GenericWriteFPUL], (instrs PseudoCVT_D32_W, PseudoCVT_D64_L, + PseudoCVT_D64_W, PseudoCVT_S_L, + PseudoCVT_S_W)>; // div.[ds], div.ps -def : ItinRW<[GenericWriteFPUDivS], [II_DIV_S]>; -def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>; +def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S)>; +def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>; // sqrt.[ds], sqrt.ps -def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>; -def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>; +def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S)>; +def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>; // rsqrt.[ds], recip.[ds] -def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>; -def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>; +def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S, RSQRT_S)>; +def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32, RECIP_D64, + RSQRT_D32, RSQRT_D64)>; -// MIPSR6 -// ====== -// -// rint.[ds] -def : ItinRW<[GenericWriteFPUL], [II_RINT_S, II_RINT_D]>; // Load Pipe // --------- // ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1 -def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_CFC1, II_CTC1, II_MFC1, II_MFHC1, - II_MTC1, II_MTHC1]>; +def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs BuildPairF64, + BuildPairF64_64, ExtractElementF64, + ExtractElementF64_64, CFC1, CTC1, + MFC1, MFC1_D64, MFHC1_D32, + MFHC1_D64, MTC1, MTC1_D64, + MTHC1_D32, MTHC1_D64)>; // swc1, swxc1 -def : ItinRW<[GenericWriteFPUStore], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1, - II_SWXC1]>; +def : InstRW<[GenericWriteFPUStore], (instrs SDC1, SDC164, SDXC1, SDXC164, + SUXC1, SUXC164, SWC1, SWXC1)>; + +def : InstRW<[GenericWriteFPUMoveFP], (instrs FMOV_D32, FMOV_D64, FMOV_S)>; + // movn.[ds], movz.[ds] -def : ItinRW<[GenericWriteFPUMoveFP], [II_MOV_D, II_MOV_S, II_MOVF, II_MOVT, - II_MOVN_D, II_MOVN_S, II_MOVZ_D, - II_MOVZ_S]>; +def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_I, MOVF_D32, MOVF_D64, + MOVF_S, MOVT_I, MOVT_D32, MOVT_D64, + MOVT_S, MOVN_I_D32, MOVN_I_D64, + MOVN_I_S, MOVZ_I_D32, MOVZ_I_D64, + MOVZ_I_S)>; + +def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVT_I64, MOVF_I64, MOVZ_I64_S, + MOVN_I64_D64, MOVN_I64_S, + MOVZ_I64_D64)>; // l[dw]x?c1 -def : ItinRW<[GenericWriteFPULoad], [II_LDC1, II_LDXC1, II_LUXC1, II_LWC1, - II_LWXC1]>; +def : InstRW<[GenericWriteFPULoad], (instrs LDC1, LDC164, LDXC1, LDXC164, + LUXC1, LUXC164, LWC1, LWXC1)>; -// MIPS64 +// MIPSR6 // ====== -def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_DMFC1, II_DMTC1]>; +// sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds] +def : InstRW<[GenericWriteFPUS], (instrs SELEQZ_S, SELNEZ_S, SELEQZ_D, SELNEZ_D, + MAX_S, MAX_D, MAXA_S, MAXA_D, MIN_S, MIN_D, + MINA_S, MINA_D, CLASS_S, CLASS_D)>; -// MIPSR6 -// ====== +def : InstRW<[GenericWriteFPUL], (instrs RINT_S, RINT_D)>; -def : ItinRW<[GenericWriteFPUS], [II_MADDF_S, II_MSUBF_S]>; +def : InstRW<[GenericWriteFPUCmp], (instrs BC1EQZ, BC1NEZ, SEL_D, SEL_S)>; -def : ItinRW<[GenericWriteFPUS], [II_MADDF_D, II_MSUBF_D]>; +def : InstRW<[GenericWriteFPUS], (instrs MADDF_S, MSUBF_S, MADDF_D, MSUBF_D)>; -def : ItinRW<[GenericWriteFPUCmp], [II_BC1CCZ, II_SEL_D, II_SEL_S]>; -// Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips -// ================================================= +// microMIPS +// ========= + +def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_D32_MM, MOVF_S_MM, + MOVN_I_D32_MM, MOVN_I_S_MM, + MOVT_D32_MM, MOVT_S_MM, MOVZ_I_D32_MM, + MOVZ_I_S_MM)>; + + +// cvt.?.?, ceil.?, floor.?, round.?, trunc.? (n)madd.? (n)msub.? +def : InstRW<[GenericWriteFPUL], (instrs CVT_D32_S_MM, CVT_D32_W_MM, + CVT_D64_S_MM, CVT_D64_W_MM, CVT_L_D64_MM, + CVT_L_S_MM, CVT_S_D32_MM, CVT_S_D64_MM, + CVT_S_W_MM, CVT_W_D32_MM, CVT_W_D64_MM, + CVT_W_S_MM, CEIL_W_MM, CEIL_W_S_MM, + FLOOR_W_MM, FLOOR_W_S_MM, NMADD_S_MM, + NMADD_D32_MM, NMSUB_S_MM, NMSUB_D32_MM, + MADD_S_MM, MADD_D32_MM, ROUND_W_MM, + ROUND_W_S_MM, TRUNC_W_MM, TRUNC_W_S_MM)>; + +def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z]_(S|D32|D64)_MM$")>; +def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z]_(S|D32|D64)_MM$")>; +def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z][A-Z]_(S|D32|D64)_MM$")>; +def : InstRW<[GenericWriteFPUCmp], (instregex "^C_NGLE_(S|D32|D64)_MM$")>; +def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_S32_MM, FCMP_D32_MM)>; + +def : InstRW<[GenericWriteFPUS], (instrs MFC1_MM, MFHC1_D32_MM, MFHC1_D64_MM, + MTC1_MM, MTHC1_D32_MM, MTHC1_D64_MM)>; + +def : InstRW<[GenericWriteFPUS], (instrs FABS_D32_MM, FABS_D64_MM, FABS_S_MM, + FNEG_D32_MM, FNEG_D64_MM, FNEG_S_MM, + FADD_D32_MM, FADD_D64_MM, FADD_S_MM, + FMOV_D32_MM, FMOV_D64_MM, FMOV_S_MM, + FMUL_D32_MM, FMUL_D64_MM, FMUL_S_MM, + FSUB_D32_MM, FSUB_D64_MM, FSUB_S_MM, + MSUB_S_MM, MSUB_D32_MM)>; + +def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S_MM)>; +def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32_MM, FDIV_D64_MM)>; + +def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S_MM)>; +def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32_MM, FSQRT_D64_MM)>; + +def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S_MM, RSQRT_S_MM)>; +def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32_MM, RECIP_D64_MM, + RSQRT_D32_MM, RSQRT_D64_MM)>; + +def : InstRW<[GenericWriteFPUStore], (instrs SDC1_MM, SWC1_MM, SUXC1_MM, + SWXC1_MM)>; + +def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs CFC1_MM, CTC1_MM)>; + +def : InstRW<[GenericWriteFPULoad], (instrs LDC1_MM, LUXC1_MM, LWC1_MM, + LWXC1_MM)>; + +// microMIPS32r6 +// ============= + +def : InstRW<[GenericWriteFPUS], (instrs FNEG_S_MMR6)>; + +def : InstRW<[GenericWriteFPUCmp], (instregex "CMP_[A-Z][A-Z]_(S|D)_MMR6")>; +def : InstRW<[GenericWriteFPUCmp], + (instregex "CMP_[A-Z][A-Z][A-Z]_(S|D)_MMR6")>; +def : InstRW<[GenericWriteFPUCmp], + (instregex "CMP_[A-Z][A-Z][A-Z][A-Z]_(S|D)_MMR6")>; -def : ItinRW<[GenericWriteALU], [II_SEQ_SNE, II_SEQI_SNEI, II_POP, II_BADDU, - II_BBIT]>; +def : InstRW<[GenericWriteFPUL], + (instregex "CVT_(L|D|S|W)_(L|D|S|L|W)_MMR6")>; + +def : InstRW<[GenericWriteFPUL], + (instregex "TRUNC_(L|W)_(D|S)_MMR6")>; + +def : InstRW<[GenericWriteFPUL], + (instregex "ROUND_(L|W)_(D|S)_MMR6")>; + +def : InstRW<[GenericWriteFPUL], + (instregex "FLOOR_(L|W)_(D|S)_MMR6")>; + +def : InstRW<[GenericWriteFPUL], + (instregex "CEIL_(L|W)_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUS], + (instrs MFC1_MMR6, MTC1_MMR6, CLASS_S_MMR6, CLASS_D_MMR6, + FADD_S_MMR6)>; + +def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)A_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUS], (instregex "SEL(EQ|NE)Z_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUS], (instregex "SEL_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUL], (instrs RINT_S_MMR6, RINT_D_MMR6)>; + +def : InstRW<[GenericWriteFPUS], (instregex "M(ADD|SUB)F_(S|D)_MMR6")>; + +def : InstRW<[GenericWriteFPUS], (instrs FMOV_S_MMR6, FMUL_S_MMR6, + FSUB_S_MMR6)>; + +def : InstRW<[GenericWriteFPUL], (instrs FDIV_S_MMR6)>; + +def : InstRW<[GenericWriteFPUStore], (instrs SDC1_D64_MMR6)>; + +def : InstRW<[GenericWriteFPULoad], (instrs LDC1_D64_MMR6)>; + +// MIPS64 +// ====== + +def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs DMFC1, DMTC1)>; // MIPS DSP ASE, HasDSP // ==================== +def : InstRW<[GenericWriteStore], (instrs SWDSP)>; + +def : InstRW<[GenericWriteLoad], (instrs LWDSP)>; + +def : InstRW<[GenericWriteMove], (instrs PseudoMTLOHI_DSP)>; + def GenericDSP : ProcResource<1> { let BufferSize = 1; } def GenericDSPShort : SchedWriteRes<[GenericDSP]> { let Latency = 2; } def GenericDSPLong : SchedWriteRes<[GenericDSP]> { let Latency = 6; } @@ -687,6 +1162,10 @@ // microMIPS DSP R1 - HasDSP, InMicroMips // ====================================== +def : InstRW<[GenericWriteLoad], (instrs LWDSP_MM)>; + +def : InstRW<[GenericWriteStore], (instrs SWDSP_MM)>; + def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH_MM$")>; @@ -740,7 +1219,6 @@ def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>; -def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>; @@ -902,12 +1380,12 @@ def : InstRW<[GenericWriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; -// and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b +// and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b, lsa def : InstRW<[GenericWriteMSAShortLogic], (instregex "^MOVE_V$")>; def : InstRW<[GenericWriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instrs LSA)>; def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; -def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b @@ -922,7 +1400,7 @@ def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>; -// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] +// pcnt.[bhwd], sat_s.[bhwd], sat_u.[bhwd] def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; @@ -935,10 +1413,6 @@ def : InstRW<[GenericWriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; -// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] -def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; -def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; - // fexp2_w, fexp2_d def : InstRW<[GenericWriteFPUS], (instregex "^FEXP2_(W|D)$")>; @@ -953,6 +1427,15 @@ def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LE_(S|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_F_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SAF_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SEQ_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLE_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLT_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUEQ_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULE_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULT_(D|S)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUN_(D|S)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FSUEQ_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FSULE_(W|D)$")>; @@ -995,7 +1478,6 @@ // interleave right/left, interleave even/odd, insert def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; -def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; // subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>;