Index: include/llvm/IR/IntrinsicsX86.td
===================================================================
--- include/llvm/IR/IntrinsicsX86.td
+++ include/llvm/IR/IntrinsicsX86.td
@@ -6403,10 +6403,14 @@
 }
 
 //===----------------------------------------------------------------------===//
-// Cache line write back intrinsics
+// Cache write back intrinsics
 
-// Write back no-invalidate
 let TargetPrefix = "x86" in {
+  // Write back and invalidate
+  def int_x86_wbinvd : GCCBuiltin<"__builtin_ia32_wbinvd">,
+      Intrinsic<[], [], []>;
+
+  // Write back no-invalidate
   def int_x86_wbnoinvd : GCCBuiltin<"__builtin_ia32_wbnoinvd">,
       Intrinsic<[], [], []>;
 }
Index: lib/Target/X86/X86InstrSystem.td
===================================================================
--- lib/Target/X86/X86InstrSystem.td
+++ lib/Target/X86/X86InstrSystem.td
@@ -481,7 +481,8 @@
 // Cache instructions
 let SchedRW = [WriteSystem] in {
 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
-def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
+def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd",
+               [(int_x86_wbinvd)], IIC_INVD>, TB;
 
 // wbnoinvd is like wbinvd, except without invalidation
 // encoding: like wbinvd + an 0xF3 prefix
Index: test/CodeGen/X86/wbinvd-intrinsic.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/wbinvd-intrinsic.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=i686
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=x86_64
+
+define void @test_wbinvd() {
+; i686-LABEL: test_wbinvd:
+; i686:       # %bb.0:
+; i686-NEXT:    wbinvd
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test_wbinvd:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    wbinvd
+; x86_64-NEXT:    retq
+  call void @llvm.x86.wbinvd()
+  ret void
+}
+
+declare void @llvm.x86.wbinvd()