Index: lib/Target/ARC/ARCInstrInfo.td
===================================================================
--- lib/Target/ARC/ARCInstrInfo.td
+++ lib/Target/ARC/ARCInstrInfo.td
@@ -356,11 +356,19 @@
                                  { let Size = 8; }
 } // let isBranch, isTerminator
 
-// Indirect, unconditional Jump.
-let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
-def J :  F32_DOP_RR<0b00100, 0b100000, 0,
-               (outs), (ins GPR32:$C),
-               "j\t[$C]", [(brind i32:$C)]>;
+// Unconditional Jump.
+let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
+  // Indirect.
+  let isIndirectBranch = 1 in
+  def J :  F32_DOP_RR<0b00100, 0b100000, 0,
+                      (outs), (ins GPR32:$C),
+                      "j\t[$C]", [(brind i32:$C)]>;
+
+  // Direct.
+  def J_LImm : F32_DOP_RLIMM<0b00100, 0b100000, 0,
+                             (outs), (ins i32imm:$LImm),
+                             "j\t$LImm", []>;
+}
 
 // Call instructions.
 let isCall = 1, isBarrier = 1, Defs = [BLINK], Uses = [SP] in {
@@ -372,6 +380,10 @@
   let isIndirectBranch = 1 in
   def JL : F32_DOP_RR<0b00100, 0b100010, 0, (outs), (ins GPR32:$C),
                      "jl\t[$C]", [(ARCJumpLink i32:$C)]>;
+
+  // Direct unconditional call.
+  def JL_LImm : F32_DOP_RLIMM<0b00100, 0b100010, 0, (outs), (ins i32imm:$LImm),
+                              "jl\t$LImm", []>;
 } // let isCall, isBarrier, Defs, Uses
 
 // Pattern to generate BL instruction.
Index: test/MC/Disassembler/ARC/misc.txt
===================================================================
--- test/MC/Disassembler/ARC/misc.txt
+++ test/MC/Disassembler/ARC/misc.txt
@@ -37,9 +37,15 @@
 # CHECK: jl [%r21]
 0x22 0x20 0x40 0x05
 
+# CHECK: jl 12345
+0x22 0x20 0x80 0x0f 0x00 0x00 0x39 0x30
+
 # CHECK: j [%r3]
 0x20 0x20 0xc0 0x00
 
+# CHECK: j 12345
+0x20 0x20 0x80 0x0f 0x00 0x00 0x39 0x30
+
 # CHECK: seteq %r3, %fp, %r1
 0x38 0x23 0x43 0x30