Index: llvm/lib/CodeGen/RegUsageInfoCollector.cpp
===================================================================
--- llvm/lib/CodeGen/RegUsageInfoCollector.cpp
+++ llvm/lib/CodeGen/RegUsageInfoCollector.cpp
@@ -97,6 +97,9 @@
 
   const Function &F = MF.getFunction();
 
+ if (!F.isDefinitionExact())
+    return false;
+
   PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
 
   PRUI->setTargetMachine(&TM);
Index: llvm/test/CodeGen/PowerPC/ipra-odr.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ipra-odr.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -enable-ipra < %s | FileCheck %s
+;
+; Check that IPRA does not run and change register allocation in functions that
+; have callees that could be redefined at link time.
+
+@x = local_unnamed_addr global i64 0, align 4
+
+; Function Attrs: norecurse nounwind
+define weak_odr void @bar(i64 signext %a, i64 signext %b) local_unnamed_addr {
+entry:
+b  %add = add nsw i64 %b, %a
+  store i64 %add, i64* @x, align 4
+  ret void
+}
+
+; CHECK-LABEL: @foo
+; CHECK: bl bar
+; CHECK: nop
+; CHECK: mr 3, {{[0-9]+}}
+; CHECK: mr 4, {{[0-9]+}}
+; CHECK: bl bar
+; CHECK: blr
+define signext i64 @foo(i64 signext %a, i64 signext %b) {
+entry:
+  call void @bar(i64 signext %a, i64 signext %b)
+  call void @bar(i64 signext %a, i64 signext %b)
+
+ret i64 0
+}
+