Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -193,6 +193,10 @@
   /// so that we can use initializer lists for subtarget initialization.
   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
+  struct MemLatencyMutation : public ScheduleDAGMutation {
+    void apply(ScheduleDAGInstrs *DAG) override;
+  };
+
 private:
   void initializeEnvironment();
   void initSubtargetFeatures(StringRef CPU, StringRef FS);
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -47,6 +47,26 @@
   return *this;
 }
 
+void PPCSubtarget::MemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
+  for (SUnit &SU : DAG->SUnits) {
+    // Looking for loads and stores.
+    if (!SU.getInstr()->mayLoad() && !SU.getInstr()->mayStore()) 
+      continue;
+
+    // If we have a memory dependency then set the latency to 4 cycles.
+    // The reason 4 is picked is because it is the best case scenario for a
+    // load when we get a cache hit.
+    for (SDep &Dep :  SU.Succs) {
+      if (Dep.isNormalMemory())
+        Dep.setLatency(4);
+    }
+    for (SDep &Dep :  SU.Preds) {
+      if (Dep.isNormalMemory())
+        Dep.setLatency(4);
+    }
+  }
+}
+
 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
Index: lib/Target/PowerPC/PPCTargetMachine.cpp
===================================================================
--- lib/Target/PowerPC/PPCTargetMachine.cpp
+++ lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -309,6 +309,20 @@
     return getTM<PPCTargetMachine>();
   }
 
+  ScheduleDAGInstrs *
+  createMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
+    DAG->addMutation(llvm::make_unique<PPCSubtarget::MemLatencyMutation>());
+    return DAG;
+  }
+
+  ScheduleDAGInstrs *
+  createPostMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
+    DAG->addMutation(llvm::make_unique<PPCSubtarget::MemLatencyMutation>());
+    return DAG;
+  }
+
   void addIRPasses() override;
   bool addPreISel() override;
   bool addILPOpts() override;