Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6446,7 +6446,7 @@
 
 
   if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
-      VT != MVT::f64 &&
+      !VT.isVector() && VT != MVT::f64 &&
       ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) {
     // max(max(a, b), c) -> max3(a, b, c)
     // min(min(a, b), c) -> min3(a, b, c)
Index: llvm/trunk/test/CodeGen/AMDGPU/fmax3.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmax3.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/fmax3.ll
@@ -84,9 +84,38 @@
   ret void
 }
 
+; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of max3
+; since there are no pack instructions for fmax3.
+; GCN-LABEL: {{^}}no_fmax3_v2f16:
+
+; SI: v_cvt_f16_f32_e32
+; SI: v_max_f32_e32
+; SI-NEXT: v_max_f32_e32
+; SI-NEXT: v_max3_f32
+; SI-NEXT: v_max3_f32
+
+; VI: v_max_f16_e32
+; VI-NEXT: v_max_f16_e32
+; VI-NEXT: v_max_f16_e32
+; VI-NEXT: v_max_f16_e32
+; VI-NEXT: v_max_f16_e32
+; VI-NEXT: v_max_f16_e32
+
+; GFX9: v_pk_max_f16
+; GFX9-NEXT: v_pk_max_f16
+; GFX9-NEXT: v_pk_max_f16
+define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
+entry:
+  %max = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+  %max1 = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max)
+  %res = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %max1, <2 x half> %d)
+  ret <2 x half> %res
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare float @llvm.maxnum.f32(float, float) #1
 declare half @llvm.maxnum.f16(half, half) #1
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }
Index: llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll
@@ -82,9 +82,38 @@
   ret void
 }
 
+; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of min3
+; since there are no pack instructions for fmin3.
+; GCN-LABEL: {{^}}no_fmin3_v2f16:
+
+; SI: v_cvt_f16_f32_e32
+; SI: v_min_f32_e32
+; SI-NEXT: v_min_f32_e32
+; SI-NEXT: v_min3_f32
+; SI-NEXT: v_min3_f32
+
+; VI: v_min_f16_e32
+; VI-NEXT: v_min_f16_e32
+; VI-NEXT: v_min_f16_e32
+; VI-NEXT: v_min_f16_e32
+; VI-NEXT: v_min_f16_e32
+; VI-NEXT: v_min_f16_e32
+
+; GFX9: v_pk_min_f16
+; GFX9: v_pk_min_f16
+; GFX9: v_pk_min_f16
+define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
+entry:
+  %min = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
+  %min1 = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %c, <2 x half> %min)
+  %res = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %min1, <2 x half> %d)
+  ret <2 x half> %res
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare float @llvm.minnum.f32(float, float) #1
 declare half @llvm.minnum.f16(half, half) #1
+declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }