Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -1054,6 +1054,7 @@
   setOperationAction(ISD::SETCC,     MVT::f32, Expand);
   setOperationAction(ISD::SETCC,     MVT::f64, Expand);
   setOperationAction(ISD::SELECT,    MVT::i32, Custom);
+  setOperationAction(ISD::SELECT,    MVT::f16, Custom);
   setOperationAction(ISD::SELECT,    MVT::f32, Custom);
   setOperationAction(ISD::SELECT,    MVT::f64, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
@@ -4525,7 +4526,9 @@
   // Normalize the fp compare. If RHS is zero we keep it there so we match
   // CMPFPw0 instead of CMPFP.
   if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
-    (TrueVal.getValueType() == MVT::f32 || TrueVal.getValueType() == MVT::f64)) {
+     (TrueVal.getValueType() == MVT::f16 ||
+      TrueVal.getValueType() == MVT::f32 ||
+      TrueVal.getValueType() == MVT::f64)) {
     bool swpCmpOps = false;
     bool swpVselOps = false;
     checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
Index: test/CodeGen/ARM/fp16-instructions.ll
===================================================================
--- test/CodeGen/ARM/fp16-instructions.ll
+++ test/CodeGen/ARM/fp16-instructions.ll
@@ -746,26 +746,84 @@
 ; CHECK-HARDFP-FULLFP16:       vseleq.f16  s0, s{{.}}, s{{.}}
 }
 
+; FIXME: more tests need to be added for VSELGE and VSELGT.
+; That is, more combinations of immediate operands that can or can't
+; be encoded as an FP16 immediate need to be added here.
+;
 ; 36. VSELGE
-define half @select_cc2()  {
+define half @select_cc_ge1()  {
   %1 = fcmp nsz oge half undef, 0xH0001
   %2 = select i1 %1, half 0xHC000, half 0xH0002
   ret half %2
 
-; CHECK-LABEL:                 select_cc2:
+; CHECK-LABEL:                 select_cc_ge1:
 ; CHECK-HARDFP-FULLFP16:       vselge.f16  s0, s{{.}}, s{{.}}
 }
 
+define half @select_cc_ge2()  {
+  %1 = fcmp nsz ole half undef, 0xHC001
+  %2 = select i1 %1, half 0xHC004, half 0xHC002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_ge2:
+; FIXME
+}
+
+define half @select_cc_ge3()  {
+  %1 = fcmp nsz ugt half undef, 0xH0001
+  %2 = select i1 %1, half 0xHC000, half 0xH0002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_ge3:
+; CHECK-HARDFP-FULLFP16:       vselge.f16  s0, s{{.}}, s{{.}}
+}
+
+define half @select_cc_ge4()  {
+  %1 = fcmp nsz ult half undef, 0xHC001
+  %2 = select i1 %1, half 0xHC004, half 0xHC002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_ge4:
+; FIXME
+}
+
 ; 37. VSELGT
-define half @select_cc3()  {
+define half @select_cc_gt1()  {
   %1 = fcmp nsz ogt half undef, 0xH0001
   %2 = select i1 %1, half 0xHC000, half 0xH0002
   ret half %2
 
-; CHECK-LABEL:                 select_cc3:
+; CHECK-LABEL:                 select_cc_gt1:
 ; CHECK-HARDFP-FULLFP16:       vselgt.f16  s0, s{{.}}, s{{.}}
 }
 
+define half @select_cc_gt2()  {
+  %1 = fcmp nsz uge half undef, 0xH0001
+  %2 = select i1 %1, half 0xHC000, half 0xH0002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_gt2:
+; CHECK-HARDFP-FULLFP16:       vselgt.f16  s0, s{{.}}, s{{.}}
+}
+
+define half @select_cc_gt3()  {
+  %1 = fcmp nsz ule half undef, 0xHC001
+  %2 = select i1 %1, half 0xHC004, half 0xH0002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_gt3:
+; FIXME
+}
+
+define half @select_cc_gt4()  {
+  %1 = fcmp nsz olt half undef, 0xH0001
+  %2 = select i1 %1, half 0xHC004, half 0xH0002
+  ret half %2
+
+; CHECK-LABEL:                 select_cc_gt4:
+; FIXME
+}
+
 ; 38. VSELVS
 define half @select_cc4()  {
   %1 = fcmp nsz ueq half undef, 0xH0001