Index: llvm/trunk/lib/TableGen/Record.cpp =================================================================== --- llvm/trunk/lib/TableGen/Record.cpp +++ llvm/trunk/lib/TableGen/Record.cpp @@ -157,10 +157,10 @@ SmallVector Classes(UnsortedClasses.begin(), UnsortedClasses.end()); - std::sort(Classes.begin(), Classes.end(), - [](Record *LHS, Record *RHS) { - return LHS->getNameInitAsString() < RHS->getNameInitAsString(); - }); + llvm::sort(Classes.begin(), Classes.end(), + [](Record *LHS, Record *RHS) { + return LHS->getNameInitAsString() < RHS->getNameInitAsString(); + }); FoldingSetNodeID ID; ProfileRecordRecTy(ID, Classes); Index: llvm/trunk/utils/TableGen/CTagsEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/CTagsEmitter.cpp +++ llvm/trunk/utils/TableGen/CTagsEmitter.cpp @@ -73,7 +73,7 @@ for (const auto &D : Defs) Tags.push_back(Tag(D.first, locate(D.second.get()))); // Emit tags. - std::sort(Tags.begin(), Tags.end()); + llvm::sort(Tags.begin(), Tags.end()); OS << "!_TAG_FILE_FORMAT\t1\t/original ctags format/\n"; OS << "!_TAG_FILE_SORTED\t1\t/0=unsorted, 1=sorted, 2=foldcase/\n"; for (const Tag &T : Tags) Index: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp =================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp @@ -1305,7 +1305,7 @@ SmallVector PredList; for (const Predicate &P : Predicates) PredList.push_back(&P); - std::sort(PredList.begin(), PredList.end(), deref()); + llvm::sort(PredList.begin(), PredList.end(), deref()); std::string Check; for (unsigned i = 0, e = PredList.size(); i != e; ++i) { @@ -3698,7 +3698,7 @@ } // Sort so that different orders get canonicalized to the same string. - std::sort(Preds.begin(), Preds.end()); + llvm::sort(Preds.begin(), Preds.end()); return Preds; } Index: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp =================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp @@ -713,7 +713,7 @@ //===----------------------------------------------------------------------===// static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) { - std::sort(M.begin(), M.end(), deref()); + llvm::sort(M.begin(), M.end(), deref()); M.erase(std::unique(M.begin(), M.end(), deref()), M.end()); } @@ -985,7 +985,7 @@ for (auto &RC : RegClasses) if (SuperRegRCsBV[RC.EnumValue]) SuperRegRCs.emplace_back(&RC); - std::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder); + llvm::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder); assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first"); // Find all the subreg classes and order them by size too. @@ -996,11 +996,11 @@ if (SuperRegClassesBV.any()) SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV)); } - std::sort(SuperRegClasses.begin(), SuperRegClasses.end(), - [&](const std::pair &A, - const std::pair &B) { - return SizeOrder(A.first, B.first); - }); + llvm::sort(SuperRegClasses.begin(), SuperRegClasses.end(), + [&](const std::pair &A, + const std::pair &B) { + return SizeOrder(A.first, B.first); + }); // Find the biggest subclass and subreg class such that R:subidx is in the // subreg class for all R in subclass. @@ -1061,7 +1061,7 @@ if (!RU.Artificial) TmpUnits.push_back(*UnitI); } - std::sort(TmpUnits.begin(), TmpUnits.end()); + llvm::sort(TmpUnits.begin(), TmpUnits.end()); std::unique_copy(TmpUnits.begin(), TmpUnits.end(), std::back_inserter(RegUnits)); } @@ -1080,7 +1080,7 @@ // Read in the user-defined (named) sub-register indices. // More indices will be synthesized later. std::vector SRIs = Records.getAllDerivedDefinitions("SubRegIndex"); - std::sort(SRIs.begin(), SRIs.end(), LessRecord()); + llvm::sort(SRIs.begin(), SRIs.end(), LessRecord()); for (unsigned i = 0, e = SRIs.size(); i != e; ++i) getSubRegIdx(SRIs[i]); // Build composite maps from ComposedOf fields. @@ -1089,7 +1089,7 @@ // Read in the register definitions. std::vector Regs = Records.getAllDerivedDefinitions("Register"); - std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); + llvm::sort(Regs.begin(), Regs.end(), LessRecordRegister()); // Assign the enumeration values. for (unsigned i = 0, e = Regs.size(); i != e; ++i) getReg(Regs[i]); @@ -1100,7 +1100,7 @@ for (Record *R : Tups) { std::vector TupRegs = *Sets.expand(R); - std::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister()); + llvm::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister()); for (Record *RC : TupRegs) getReg(RC); } Index: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp =================================================================== --- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp +++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp @@ -244,7 +244,7 @@ /// Gather all processor models. void CodeGenSchedModels::collectProcModels() { RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); - std::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName()); + llvm::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName()); // Reserve space because we can. Reallocation would be ok. ProcModels.reserve(ProcRecords.size()+1); @@ -363,7 +363,7 @@ // Find all ReadWrites referenced by SchedAlias. AliasDefs needs to be sorted // for the loop below that initializes Alias vectors. RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias"); - std::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord()); + llvm::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord()); for (Record *ADef : AliasDefs) { Record *MatchDef = ADef->getValueAsDef("MatchRW"); Record *AliasDef = ADef->getValueAsDef("AliasRW"); @@ -381,12 +381,12 @@ } // Sort and add the SchedReadWrites directly referenced by instructions or // itinerary resources. Index reads and writes in separate domains. - std::sort(SWDefs.begin(), SWDefs.end(), LessRecord()); + llvm::sort(SWDefs.begin(), SWDefs.end(), LessRecord()); for (Record *SWDef : SWDefs) { assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite"); SchedWrites.emplace_back(SchedWrites.size(), SWDef); } - std::sort(SRDefs.begin(), SRDefs.end(), LessRecord()); + llvm::sort(SRDefs.begin(), SRDefs.end(), LessRecord()); for (Record *SRDef : SRDefs) { assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite"); SchedReads.emplace_back(SchedReads.size(), SRDef); @@ -613,7 +613,7 @@ } // Create classes for InstRW defs. RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); - std::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord()); + llvm::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord()); DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n"); for (Record *RWDef : InstRWDefs) createInstRWClass(RWDef); @@ -910,7 +910,7 @@ // Gather the read/write types for each itinerary class. void CodeGenSchedModels::collectProcItinRW() { RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); - std::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord()); + llvm::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord()); for (Record *RWDef : ItinRWDefs) { if (!RWDef->getValueInit("SchedModel")->isComplete()) PrintFatalError(RWDef->getLoc(), "SchedModel is undefined"); @@ -1609,12 +1609,12 @@ } // Finalize each ProcModel by sorting the record arrays. for (CodeGenProcModel &PM : ProcModels) { - std::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(), - LessRecord()); - std::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(), - LessRecord()); - std::sort(PM.ProcResourceDefs.begin(), PM.ProcResourceDefs.end(), - LessRecord()); + llvm::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(), + LessRecord()); + llvm::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(), + LessRecord()); + llvm::sort(PM.ProcResourceDefs.begin(), PM.ProcResourceDefs.end(), + LessRecord()); DEBUG( PM.dump(); dbgs() << "WriteResDefs: "; Index: llvm/trunk/utils/TableGen/CodeGenTarget.cpp =================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp @@ -278,7 +278,7 @@ void CodeGenTarget::ReadRegAltNameIndices() const { RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); - std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord()); + llvm::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord()); } /// getRegisterByName - If there is a register with the specific AsmName, @@ -303,7 +303,7 @@ } // Remove duplicates. - std::sort(Result.begin(), Result.end()); + llvm::sort(Result.begin(), Result.end()); Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); return Result; } @@ -314,7 +314,7 @@ LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); // Remove duplicates. - std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); + llvm::sort(LegalValueTypes.begin(), LegalValueTypes.end()); LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), LegalValueTypes.end()), LegalValueTypes.end()); @@ -382,8 +382,9 @@ // All of the instructions are now in random order based on the map iteration. // Sort them by name. - std::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), - [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { + llvm::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), + [](const CodeGenInstruction *Rec1, + const CodeGenInstruction *Rec2) { return Rec1->TheDef->getName() < Rec2->TheDef->getName(); }); } @@ -507,11 +508,11 @@ if (isTarget == TargetOnly) Intrinsics.push_back(CodeGenIntrinsic(Defs[I])); } - std::sort(Intrinsics.begin(), Intrinsics.end(), - [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { - return std::tie(LHS.TargetPrefix, LHS.Name) < - std::tie(RHS.TargetPrefix, RHS.Name); - }); + llvm::sort(Intrinsics.begin(), Intrinsics.end(), + [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { + return std::tie(LHS.TargetPrefix, LHS.Name) < + std::tie(RHS.TargetPrefix, RHS.Name); + }); Targets.push_back({"", 0, 0}); for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) if (Intrinsics[I].TargetPrefix != Targets.back().Name) { @@ -703,6 +704,6 @@ Properties = parseSDPatternOperatorProperties(R); // Sort the argument attributes for later benefit. - std::sort(ArgumentAttributes.begin(), ArgumentAttributes.end()); + llvm::sort(ArgumentAttributes.begin(), ArgumentAttributes.end()); } Index: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp @@ -153,7 +153,7 @@ // We want to process the matches in order of minimal cost. Sort the patterns // so the least cost one is at the start. - std::sort(Patterns.begin(), Patterns.end(), PatternSortingPredicate(CGP)); + llvm::sort(Patterns.begin(), Patterns.end(), PatternSortingPredicate(CGP)); // Convert each variant of each pattern into a Matcher. Index: llvm/trunk/utils/TableGen/FastISelEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp @@ -811,7 +811,7 @@ = SignaturesWithConstantForms.find(Operands); if (MI != SignaturesWithConstantForms.end()) { // Unique any duplicates out of the list. - std::sort(MI->second.begin(), MI->second.end()); + llvm::sort(MI->second.begin(), MI->second.end()); MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), MI->second.end()); Index: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp +++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp @@ -148,7 +148,7 @@ const LLT &get() const { return Ty; } - /// This ordering is used for std::unique() and std::sort(). There's no + /// This ordering is used for std::unique() and llvm::sort(). There's no /// particular logic behind the order but either A < B or B < A must be /// true if A != B. bool operator<(const LLTCodeGen &Other) const { @@ -2207,7 +2207,7 @@ std::vector MergeInsnIDs; for (const auto &IDMatcherPair : Rule.defined_insn_vars()) MergeInsnIDs.push_back(IDMatcherPair.second); - std::sort(MergeInsnIDs.begin(), MergeInsnIDs.end()); + llvm::sort(MergeInsnIDs.begin(), MergeInsnIDs.end()); for (const auto &MergeInsnID : MergeInsnIDs) Table << MatchTable::IntValue(MergeInsnID); Table << MatchTable::NamedValue("GIU_MergeMemOperands_EndOfList") @@ -2435,7 +2435,7 @@ InsnIDs.push_back(Pair.second); } - std::sort(InsnIDs.begin(), InsnIDs.end()); + llvm::sort(InsnIDs.begin(), InsnIDs.end()); for (const auto &InsnID : InsnIDs) { // Reject the difficult cases until we have a more accurate check. @@ -3732,11 +3732,11 @@ std::vector ComplexPredicates = RK.getAllDerivedDefinitions("GIComplexOperandMatcher"); - std::sort(ComplexPredicates.begin(), ComplexPredicates.end(), orderByName); + llvm::sort(ComplexPredicates.begin(), ComplexPredicates.end(), orderByName); std::vector CustomRendererFns = RK.getAllDerivedDefinitions("GICustomOperandRenderer"); - std::sort(CustomRendererFns.begin(), CustomRendererFns.end(), orderByName); + llvm::sort(CustomRendererFns.begin(), CustomRendererFns.end(), orderByName); unsigned MaxTemporaries = 0; for (const auto &Rule : Rules) @@ -3812,7 +3812,7 @@ std::vector TypeObjects; for (const auto &Ty : LLTOperandMatcher::KnownTypes) TypeObjects.push_back(Ty); - std::sort(TypeObjects.begin(), TypeObjects.end()); + llvm::sort(TypeObjects.begin(), TypeObjects.end()); OS << "// LLT Objects.\n" << "enum {\n"; for (const auto &TypeObject : TypeObjects) { @@ -3834,7 +3834,7 @@ std::vector> FeatureBitsets; for (auto &Rule : Rules) FeatureBitsets.push_back(Rule.getRequiredFeatures()); - std::sort( + llvm::sort( FeatureBitsets.begin(), FeatureBitsets.end(), [&](const std::vector &A, const std::vector &B) { if (A.size() < B.size()) Index: llvm/trunk/utils/TableGen/InfoByHwMode.cpp =================================================================== --- llvm/trunk/utils/TableGen/InfoByHwMode.cpp +++ llvm/trunk/utils/TableGen/InfoByHwMode.cpp @@ -84,7 +84,7 @@ std::vector Pairs; for (const auto &P : Map) Pairs.push_back(&P); - std::sort(Pairs.begin(), Pairs.end(), deref>()); + llvm::sort(Pairs.begin(), Pairs.end(), deref>()); OS << '{'; for (unsigned i = 0, e = Pairs.size(); i != e; ++i) { @@ -176,7 +176,7 @@ std::vector Pairs; for (const auto &P : Map) Pairs.push_back(&P); - std::sort(Pairs.begin(), Pairs.end(), deref>()); + llvm::sort(Pairs.begin(), Pairs.end(), deref>()); OS << '{'; for (unsigned i = 0, e = Pairs.size(); i != e; ++i) { Index: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp @@ -296,7 +296,7 @@ PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); } - std::sort(PSets[i].begin(), PSets[i].end()); + llvm::sort(PSets[i].begin(), PSets[i].end()); PSetsSeqs.add(PSets[i]); } Index: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp @@ -134,7 +134,7 @@ // Get all records of class and sort std::vector DefList = Records.getAllDerivedDefinitions("SubtargetFeature"); - std::sort(DefList.begin(), DefList.end(), LessRecord()); + llvm::sort(DefList.begin(), DefList.end(), LessRecord()); unsigned N = DefList.size(); if (N == 0) @@ -173,7 +173,7 @@ if (FeatureList.empty()) return 0; - std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); + llvm::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" @@ -223,7 +223,7 @@ // Gather and sort processor information std::vector ProcessorList = Records.getAllDerivedDefinitions("Processor"); - std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); + llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" @@ -1091,7 +1091,7 @@ WriteIDs.push_back(SchedModels.getSchedRWIdx(VW, /*IsRead=*/false)); } } - std::sort(WriteIDs.begin(), WriteIDs.end()); + llvm::sort(WriteIDs.begin(), WriteIDs.end()); for(unsigned W : WriteIDs) { MCReadAdvanceEntry RAEntry; RAEntry.UseIdx = UseIdx; @@ -1109,8 +1109,8 @@ // compression. // // WritePrecRes entries are sorted by ProcResIdx. - std::sort(WriteProcResources.begin(), WriteProcResources.end(), - LessWriteProcResources()); + llvm::sort(WriteProcResources.begin(), WriteProcResources.end(), + LessWriteProcResources()); SCDesc.NumWriteProcResEntries = WriteProcResources.size(); std::vector::iterator WPRPos = @@ -1322,7 +1322,7 @@ // Gather and sort processor information std::vector ProcessorList = Records.getAllDerivedDefinitions("Processor"); - std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); + llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); // Begin processor table OS << "\n"; @@ -1387,7 +1387,7 @@ << " const TargetSchedModel *SchedModel) const {\n"; std::vector Prologs = Records.getAllDerivedDefinitions("PredicateProlog"); - std::sort(Prologs.begin(), Prologs.end(), LessRecord()); + llvm::sort(Prologs.begin(), Prologs.end(), LessRecord()); for (Record *P : Prologs) { OS << P->getValueAsString("Code") << '\n'; } @@ -1471,7 +1471,7 @@ unsigned NumProcs) { std::vector Features = Records.getAllDerivedDefinitions("SubtargetFeature"); - std::sort(Features.begin(), Features.end(), LessRecord()); + llvm::sort(Features.begin(), Features.end(), LessRecord()); OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" << "// subtarget options.\n"