Index: include/llvm/CodeGen/AsmPrinter.h =================================================================== --- include/llvm/CodeGen/AsmPrinter.h +++ include/llvm/CodeGen/AsmPrinter.h @@ -233,7 +233,7 @@ /// Return information about subtarget. const MCSubtargetInfo &getSubtargetInfo() const; - void EmitToStreamer(MCStreamer &S, const MCInst &Inst); + virtual void EmitToStreamer(MCStreamer &S, const MCInst &Inst); /// Return the current section we are emitting to. const MCSection *getCurrentSection() const; Index: lib/Target/RISCV/RISCVAsmPrinter.cpp =================================================================== --- lib/Target/RISCV/RISCVAsmPrinter.cpp +++ lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -49,6 +49,7 @@ unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) override; + void EmitToStreamer(MCStreamer &S, const MCInst &Inst) override; bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI); @@ -59,22 +60,27 @@ }; } +#define GEN_COMPRESS_INSTR +#include "RISCVGenCompressInstEmitter.inc" +void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(), + OutStreamer->getContext()); + AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); +} + // Simple pseudo-instructions have their lowering (with expansion to real // instructions) auto-generated. #include "RISCVGenMCPseudoLowering.inc" -#define GEN_COMPRESS_INSTR -#include "RISCVGenCompressInstEmitter.inc" void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Do any auto-generated pseudo lowerings. if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; - MCInst TmpInst, CInst; + MCInst TmpInst; LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this); - bool Res = compressInst(CInst, TmpInst, *TM.getMCSubtargetInfo(), - OutStreamer->getContext()); - EmitToStreamer(*OutStreamer, Res ? CInst : TmpInst); + EmitToStreamer(*OutStreamer, TmpInst); } bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, Index: test/CodeGen/RISCV/compress-Pseudo.ll =================================================================== --- /dev/null +++ test/CodeGen/RISCV/compress-Pseudo.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=riscv32 -mattr=+c -riscv-no-aliases -o %t1 < %s +; RUN: FileCheck %s < %t1 + +define void @foo() { +; CHECK-LABEL: foo: +; CHECK: c.jr + +end: + ret void +}