[AMDGPU] Define code object identification string used in AMDHSA runtimes.

[kzhuravl]

LGTM

[t-tye]

Change target feature element of the target identification string to be comma separated so hyphens only delimit the elements.

[kzhuravl]

LGTM.

[b-sumner]

LGTM, but I'd rather use '+' instead of ',' for the features.

[t-tye]

Change syntax for target features to be concatenated to Processor using a plus prefix for each target feature.

[t-tye]

In D44718#1047028, @b-sumner wrote:

LGTM, but I'd rather use '+' instead of ',' for the features.

Changed to use + prefix as suggested by Laurent.

[b-sumner]

LGTM

[kzhuravl]

docs/AMDGPUUsage.rst

941 ↗

(On Diff #139643)

I'd rather have a '-' separator, as it would be easier to tokenize.

llvm/trunk/docs/AMDGPUUsage.rst

 AMDHSA
 ------
 
 This section provides code conventions used when the target triple OS is
 ``amdhsa`` (see :ref:`amdgpu-target-triples`).
 
 .. _amdgpu-amdhsa-hsa-code-object-metadata:
 
+Code Object Target Identification
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The AMDHSA OS uses the following syntax to specify the code object
+target as a single string:
+
+  ``<Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target Features>``
+
+Where:
+
+  - ``<Architecture>``, ``<Vendor>``, ``<OS>`` and ``<Environment>``
+    are the same as the *Target Triple* (see
+    :ref:`amdgpu-target-triples`).
+
+  - ``<Processor>`` is the same as the *Processor* (see
+    :ref:`amdgpu-processors`).
+
+  - ``<Target Features>`` is a list of the enabled *Target Features*
+    (see :ref:`amdgpu-target-features`), each prefixed by a plus, that
+    apply to *Processor*. The list must be in the same order as listed
+    in the table :ref:`amdgpu-target-feature-table`. Note that *Target
+    Features* must be included in the list if they are enabled even if
+    that is the default for *Processor*.
+
+For example:
+
+  ``"amdgcn-amd-amdhsa--gfx902+xnack"``
+
 Code Object Metadata
 ~~~~~~~~~~~~~~~~~~~~
 
 The code object metadata specifies extensible metadata associated with the code
 objects executed on HSA [HSA]_ compatible runtimes such as AMD's ROCm
 [AMD-ROCm]_. It is specified by the ``NT_AMD_AMDGPU_HSA_METADATA`` note record
 (see :ref:`amdgpu-note-records`) and is required when the target triple OS is
 ``amdhsa`` (see :ref:`amdgpu-target-triples`). It must contain the minimum