[GlobalISel][X86][ARM] Relaxing type constraints on G_SHL and friends

[rtereshin]

Summary

This is WIP.

G_SHL, G_ASHR, and G_LSHR opcodes have a single type index at the moment, forcing all the operands to have the same LLT.
This is consistent with the corresponding LLVM IR opcodes, but not so much with the apparent target requirements and pre-existing *.td-defined selection rules / instruction patterns.

For instance, most (if not all) AArch64 patterns fall into one of the following categories:

1. scalar shifts, having the second source operand ("number of bits to shift") of type i64 (regardless of the type of the main operands, being i32 or i64 most of the time)
2. vector shifts, having the second source operand of type i32 (immediate or variable both), regardless of the type of the main operands (number of vector lanes and size of the vector elements both)

In other words, the type of the second source operand is not fixed (it could be i64 or i32), it could be larger or smaller than the type of the main operands, and it could be scalar even if the rest of the instruction operates on vectors.

The existing instruction selection artifacts include (but not limited to):
a) patterns, like the following:

multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
  def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
            (SHLLv8i8 V64:$Rn)>;

b) immediate predicates, like GIPFP_I64_Predicate_imm0_31

X86 patterns, on the other hand, fall into one of the following categories:

1. scalar shifts with the second source typed as i8 (as before, regardless of the types of the rest of the operands)
2. vector shifts following LLVM IR scheme with all the operands having the same type

A typical pattern from (1) looks like this:

// x << (32 - y) >> (32 - y)
def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))),
               (i8 (trunc (sub 32, GR32:$lz)))),
          (BZHI32rr GR32:$src, GR32:$lz)>;
def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))),
               (i8 (trunc (sub 32, GR32:$lz)))),
          (BZHI32rm addr:$src, GR32:$lz)>;

Mips appears to have the second source operand typed as i32 or i64, independent of the rest of the types, as usual.

This discrepancy creates the following issues:

1. Non-optimized and mildly-optimized (pre- https://reviews.llvm.org/D44700 patch) Tablegen'erated InstructionSelect's MatchTable contains rules that could not possibly match, forcing targets to implement shifts' selection by hand in C++
2. Aggressively optimized MatchTable (post- https://reviews.llvm.org/D44700 patch) contains rules that can and will actually match, but then execute renderers that expect the values having different types (from original SelectionDAG ISel patterns), resulting in miscopmiles.
3. Testgen (https://reviews.llvm.org/D43962) generates test-cases that don't represent the actual contents of the MatchTable

(2) and (3) due to the fact that aggressive optimizations and test-generation exploits type constrains as defined by Tablegen'erated MCInstrDesc to reduce the number of type checks performed during selection and properly handle partially optimized match tables respectively.

Issue (1) for x86 is mentioned in the following commit message: https://github.com/llvm-mirror/llvm/commit/5b113a2c3b054e1d894ab9e44a6a08e1d0cd7ff3 (git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327499 91177308-0d34-0410-b5e6-96231b3b80d8, https://reviews.llvm.org/D44395), adding as much hand-written C++ selecting shifts as could be seen here: https://github.com/llvm-mirror/llvm/blob/5b113a2c3b054e1d894ab9e44a6a08e1d0cd7ff3/lib/Target/X86/X86InstructionSelector.cpp#L1405-L1482

AArch64 ended up having manually written C++ for selecting all the shifts and G_GEP for GPR RegBank, and the majority of binary ops for FPR RegBank.

I see 2 ways of solving the problem:

1. Change GlobalISel Emitter the Tablegen backend so it would intelligently adapt the patterns being imported and re-write them so they would work with existing G_* shifts
2. Relax the type constraints for G_* shifts and allow the second source operand to have an independent type

Given the diversity between targets (1) will have to be target-specific, and in any way it will most likely end up being quite complicated and fragile. Also, vector shifts with a scalar shift amount (AArch64) won't be possible, therefore selecting an efficient opcode will only be possible for vector shifts if the vector operand for shift amounts have the same vreg for every vector element, which is again, fragile and will probably require an additional combine to happen more often. It makes more sense, IMO, to allow such mixed shifts on MIR level explicitly.

Also, shifts aren't regular arithmetic/logical binary ops anyway, they aren't commutative nor associative, their second source operand is always an unsigned integer type regardless of the rest of the operands being signed or unsigned, and the corresponding LLVM IR opcodes have special rules regarding poison values WRT that operand. Therefore they require special handling across the selector anyway.

So this patch is to track progress on implementing the solution (2) at the moment, and get it reviewed as soon as it's done.

[dsanders]

The GenericOpcodes.td change makes sense to me but I'm surprised that only AMGGPU's LegalizerInfo is changing and only for SHL. I'd have expected most (probably all) GlobalISel targets to need to change all three shifts.

Also, could you add a test case?

[rtereshin]

In D44704#1049848, @dsanders wrote:

The GenericOpcodes.td change makes sense to me but I'm surprised that only AMGGPU's LegalizerInfo is changing and only for SHL. I'd have expected most (probably all) GlobalISel targets to need to change all three shifts.

Also, could you add a test case?

AMDGPU only legalizes G_SHL, non of the others. And w/o the setAction({G_SHL, 1, S32}, Legal); already existing tests fail (CodeGen/AMDGPU/GlobalISel/legalize-shl.mir and CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir), so no need to add another one. As for the selector, this is entire AMDGPU's selector:

case TargetOpcode::G_ADD:
  return selectG_ADD(I);
case TargetOpcode::G_CONSTANT:
  return selectG_CONSTANT(I);
case TargetOpcode::G_GEP:
  return selectG_GEP(I);
case TargetOpcode::G_LOAD:
  return selectG_LOAD(I);
case TargetOpcode::G_STORE:
  return selectG_STORE(I);

Every other target legalizes shifts by using the new-style legalization action builders, and those have a couple of rather dangerous properties:

1. If actions are built for multiple opcodes simultaneously, they are actually directly defined for a representative only, making the rest aliases, which is fine, but nothing checks that all the aliases agree in the number of type indices.
2. while actions are built for the representative, nothing checks that they are properly defined for every type index, implicitly making any type legal for any type index not mentioned with no action required.

This is why none of the other already existing tests fail, though there are plenty that test legalization of shifts.

[rtereshin]

Here's a fine example of the issue mentioned earlier:

This is how we legalize G_INTTOPTR for AArch64 right now:

getActionDefinitionsBuilder(G_INTTOPTR)
    .unsupportedIf([&](const LegalityQuery &Query) {
      return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
    })
    .legalFor({s64, p0});

(https://github.com/llvm-mirror/llvm/blob/27c28519031032a11a917fa4dbf05417fbe78740/lib/Target/AArch64/AArch64LegalizerInfo.cpp#L215-L219)

Who can spot a problem?

In fact, 2 problems at once. I'm working on a simple validation for LegalizerInfo that would catch this.

SPOILERS below:

a tip, the following MIR:

--- |
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  
  define i64 @broken(<4 x i16> %v) {
    %res = bitcast <4 x i16> %v to i64
    ret i64 %res
  }

...
---
name:            broken
alignment:       2
tracksRegLiveness: true
registers:       
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0
  
    %0:_(<4 x s16>) = COPY $d0
    %1:_(s64) = G_INTTOPTR %0(<4 x s16>)
    $x0 = COPY %1(s64)
    RET_ReallyLR implicit $x0

...

will be successfully legalized by

./bin/llc -run-pass=legalizer -verify-machineinstrs -simplify-mir <INPUT>.mir -o -

with the following output:

--- |
  ; ModuleID = 'out.mir'
  source_filename = "out.mir"
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  
  define i64 @broken(<4 x i16> %v) {
    %res = bitcast <4 x i16> %v to i64
    ret i64 %res
  }

...
---
name:            broken
alignment:       2
legalized:       true
tracksRegLiveness: true
registers:       
  - { id: 0, class: _ }
  - { id: 1, class: _ }
frameInfo:       
  maxCallFrameSize: 0
body:             |
  bb.0 (%ir-block.0):
    liveins: $d0
  
    %0:_(<4 x s16>) = COPY $d0
    %1:_(s64) = G_INTTOPTR %0(<4 x s16>)
    $x0 = COPY %1(s64)
    RET_ReallyLR implicit $x0

...

[dsanders]

It's worth mentioning that:

%1:_(s64) = G_INTTOPTR %0(<4 x s16>)

isn't a valid G_INTTOPTR. The result should be a pointer type and the input should be a scalar. However, your point stands even with that fixed.

The first problem is that it should be using the pair version of legalFor() like so:

.legalFor({{s64, p0}});

I see your point that it's too easy to mix these two overloads up at the moment:

LegalizeRuleSet &legalFor(std::initializer_list<LLT> Types);
LegalizeRuleSet &legalFor(std::initializer_list<std::pair<LLT, LLT>> Types);

A partial fix would be to rename the latter legalForPair() or similar which would make it easier to spot but even then we'd still want something to make sure we don't mix up legalFor() and legalForPair()

The next problem is that the types are backwards. It should be:

.legalFor({{p0, s64}});

[rtereshin]

Nailed it.

isn't a valid G_INTTOPTR. The result should be a pointer type and the input should be a scalar.

Well, it should be because we like it to be, MachineVerifier doesn't check that.

[rtereshin]

This is what I eventually came up with to reduce the number of such mistakes in the future:
first: https://reviews.llvm.org/D46338
second: https://reviews.llvm.org/D46339

PTAL

[rtereshin]

This is pretty much finished, PTAL

[aemerson]

I'd like to get this in. LGTM but needs one issue addressed.

lib/Target/AArch64/AArch64InstructionSelector.cpp

1092

Even though this may be true, I'd rather we not use unreachable here. If for some reason Tablegen fails to select the user we want to have SDAG try it.

[aemerson]

lib/Target/AArch64/AArch64InstructionSelector.cpp

1092

s/select the user/select, for the user

[aemerson]

This is already done in another patch. Abandon?

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

bool tryCombineSExt(MachineInstr &MI,
                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
 
     if (MI.getOpcode() != TargetOpcode::G_SEXT)
       return false;
     if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
                                            MI.getOperand(1).getReg(), MRI)) {
       unsigned DstReg = MI.getOperand(0).getReg();
       LLT DstTy = MRI.getType(DstReg);
-      if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy}}) ||
-          isInstUnsupported({TargetOpcode::G_ASHR, {DstTy}}) ||
+      if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy, DstTy}}) ||
+          isInstUnsupported({TargetOpcode::G_ASHR, {DstTy, DstTy}}) ||
           isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
         return false;
       DEBUG(dbgs() << ".. Combine MI: " << MI;);
       Builder.setInstr(MI);
       unsigned SExtSrc = MI.getOperand(1).getReg();
       LLT SExtSrcTy = MRI.getType(SExtSrc);
       unsigned SizeDiff = DstTy.getSizeInBits() - SExtSrcTy.getSizeInBits();
       auto SizeDiffMIB = Builder.buildConstant(DstTy, SizeDiff);

include/llvm/Target/GenericOpcodes.td

def G_XOR : GenericInstruction {
   let InOperandList = (ins type0:$src1, type0:$src2);
   let hasSideEffects = 0;
   let isCommutable = 1;
 }
 
 // Generic left-shift.
 def G_SHL : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 
 // Generic logical right-shift.
 def G_LSHR : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 
 // Generic arithmetic right-shift.
 def G_ASHR : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 
 // Generic integer comparison.
 def G_ICMP : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2);
   let hasSideEffects = 0;

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case TargetOpcode::G_SUB:
     // original type.
     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
     widenScalarDst(MI, WideTy);
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
 
   case TargetOpcode::G_SHL:
-    widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
     // The "number of bits to shift" operand must preserve its value as an
     // unsigned integer:
+    if (TypeIdx == 1)
       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
+    else {
+      widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
       widenScalarDst(MI, WideTy);
+    }
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
 
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_SREM:
     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
     widenScalarDst(MI, WideTy);
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
 
   case TargetOpcode::G_ASHR:
-    widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
     // The "number of bits to shift" operand must preserve its value as an
     // unsigned integer:
+    if (TypeIdx == 1)
       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
+    else {
+      widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
       widenScalarDst(MI, WideTy);
+    }
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
 
   case TargetOpcode::G_UDIV:
   case TargetOpcode::G_UREM:
-  case TargetOpcode::G_LSHR:
     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
     widenScalarDst(MI, WideTy);
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
 
+  case TargetOpcode::G_LSHR:
+    if (TypeIdx == 1)
+      widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
+    else {
+      widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
+      widenScalarDst(MI, WideTy);
+    }
+    MIRBuilder.recordInsertion(&MI);
+    return Legalized;
+
   case TargetOpcode::G_SELECT:
     if (TypeIdx != 0)
       return UnableToLegalize;
     // Perform operation at larger width (any extension is fine here, high bits
     // don't affect the result) and then truncate the result back to the
     // original type.
     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
     widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);

lib/Target/AArch64/AArch64InstrFormats.td

multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
   def Wr : BaseShift<shift_type, GPR32, asm> {
     let Inst{31} = 0;
   }
 
   def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
     let Inst{31} = 1;
   }
 
-  def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
+  def : Pat<(i32 (OpNode GPR32:$Rn, GPR64:$Rm)),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
-                                             (EXTRACT_SUBREG i64:$Rm, sub_32))>;
+                                             (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
 
   def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
 
   def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
 
   def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
+
+  def : Pat<(i32 (OpNode GPR32:$Rn, GPR32:$Rm)),
+            (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
 }
 
 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
     : InstAlias<asm#"\t$dst, $src1, $src2",
                 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
 
 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
                        RegisterClass addtype, string asm,

lib/Target/AArch64/AArch64InstrInfo.td

 
 def AArch64saddv    : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
 def AArch64uaddv    : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
 def AArch64sminv    : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
 def AArch64uminv    : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
 def AArch64smaxv    : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
 def AArch64umaxv    : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
 
+
+def : GINodeEquiv<G_SHL, AArch64vshl>;
+
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 
 // AArch64 Instruction Predicate Definitions.
 // We could compute these on a per-module basis but doing so requires accessing
 // the Function object through the <Target>Subtarget and objections were raised
 // to that (see post-commit review comments for r301750).

lib/Target/AArch64/AArch64InstructionSelector.cpp

case TargetOpcode::G_UMULH: {
     unsigned NewOpc = I.getOpcode() == TargetOpcode::G_SMULH ? AArch64::SMULHrr
                                                              : AArch64::UMULHrr;
     I.setDesc(TII.get(NewOpc));
 
     // Now that we selected an opcode, we need to constrain the register
     // operands to use appropriate classes.
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
+  case TargetOpcode::G_SHL:
+    llvm_unreachable("G_SHL is expected to be tablegen-selectable");
+  case TargetOpcode::G_LSHR:
+    llvm_unreachable("G_LSHR is expected to be tablegen-selectable");
+  case TargetOpcode::G_ASHR:
+    llvm_unreachable("G_ASHR is expected to be tablegen-selectable");
+
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
   case TargetOpcode::G_FDIV:
 
   case TargetOpcode::G_OR:
-  case TargetOpcode::G_SHL:
-  case TargetOpcode::G_LSHR:
-  case TargetOpcode::G_ASHR:
   case TargetOpcode::G_GEP: {
     // Reject the various things we don't support yet.
     if (unsupportedBinOp(I, RBI, MRI, TRI))
       return false;
 
     const unsigned OpSize = Ty.getSizeInBits();
 
     const unsigned DefReg = I.getOperand(0).getReg();

lib/Target/AArch64/AArch64LegalizerInfo.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Type.h"
 
 using namespace llvm;
 using namespace LegalizeActions;
+using namespace LegalizeMutations;
 using namespace LegalityPredicates;
 
 AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   using namespace TargetOpcode;
   const LLT p0 = LLT::pointer(0, 64);
   const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
getActionDefinitionsBuilder(G_PHI)
       .clampScalar(0, s16, s64)
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder(G_BSWAP)
       .legalFor({s32, s64})
       .clampScalar(0, s16, s64)
       .widenScalarToNextPow2(0);
 
-  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL})
+  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
       .legalFor({s32, s64, v2s32, v4s32, v2s64})
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0)
       .clampNumElements(0, v2s32, v4s32)
       .clampNumElements(0, v2s64, v2s64)
       .moreElementsToNextPow2(0);
 
   getActionDefinitionsBuilder(G_GEP)
       .legalFor({{p0, s64}})
       .clampScalar(1, s64, s64);
 
   getActionDefinitionsBuilder(G_PTR_MASK).legalFor({p0});
 
-  getActionDefinitionsBuilder({G_LSHR, G_ASHR, G_SDIV, G_UDIV})
+  getActionDefinitionsBuilder({G_SDIV, G_UDIV})
       .legalFor({s32, s64})
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0);
 
+  getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
+      .legalFor({{s32, s32}, {s32, s64}, {s64, s64}, {v4s32, s32}})
+      .clampScalar(0, s32, s64)
+      .widenScalarToNextPow2(0)
+      .maxScalar(1, s64)
+      .widenScalarIf(
+          [s64](const LegalityQuery &Query) {
+            return Query.Types[0] != Query.Types[1] && Query.Types[1] != s64;
+          },
+          [s64](const LegalityQuery &Query) {
+            return ((Query.Types[0].getSizeInBits() <
+                     Query.Types[1].getSizeInBits())
+                        ? changeTo(1, s64)
+                        : changeTo(1, 0))(Query);
+          });
+
   getActionDefinitionsBuilder({G_SREM, G_UREM})
       .lowerFor({s1, s8, s16, s32, s64});
 
   getActionDefinitionsBuilder({G_SMULO, G_UMULO})
       .lowerFor({{s64, s1}});
 
   getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
 
AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   getActionDefinitionsBuilder(G_FCMP)
       .legalFor({{s32, s32}, {s32, s64}})
       .clampScalar(0, s32, s32)
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(1);
 
   // Extensions
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
-      .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
+      .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
+      .legalFor({{v4s32, v4s16}});
 
   // FP conversions
   getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
       {{s16, s32}, {s16, s64}, {s32, s64}});
   getActionDefinitionsBuilder(G_FPEXT).legalFor(
       {{s32, s16}, {s64, s16}, {s64, s32}});
 
   // Conversions

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_GEP:
   case TargetOpcode::G_MUL:
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_UDIV:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
-    // Shifts.
-  case TargetOpcode::G_SHL:
-  case TargetOpcode::G_LSHR:
-  case TargetOpcode::G_ASHR:
     // Floating point ops.
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
   case TargetOpcode::G_FDIV:
     return getSameKindOfOperandsMapping(MI);
   case TargetOpcode::G_FPEXT: {
     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

.legalIf([=, &ST](const LegalityQuery &Query) {
       });
 
 
 
   setAction({G_SELECT, S32}, Legal);
   setAction({G_SELECT, 1, S1}, Legal);
 
   setAction({G_SHL, S32}, Legal);
+  setAction({G_SHL, 1, S32}, Legal);
 
 
   // FIXME: When RegBankSelect inserts copies, it will only create new
   // registers with scalar types.  This means we can end up with
   // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
   // operands.  In assert builds, the instruction selector will assert
   // if it sees a generic instruction which isn't legal, so we need to
   // tell it that scalar types are legal for pointer operands

lib/Target/ARM/ARMLegalizerInfo.cpp

ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   }
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
       .legalForCartesianProduct({s32}, {s1, s8, s16});
 
   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
   getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
 
-  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({s32});
+  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({{s32, s32}});
 
   getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
 
   getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
                                                                  {s1});
 
   getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
 

lib/Target/X86/X86LegalizerInfo.cpp

void X86LegalizerInfo::setLegalizerInfo32bit() {
 
   if (!Subtarget.is64Bit()) {
     getActionDefinitionsBuilder(G_PTRTOINT)
         .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
         .maxScalar(0, s32)
         .widenScalarToNextPow2(0, /*Min*/ 8);
     getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
 
-    // Shifts and SDIV
-    getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
+    // Shifts
+    getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
+        .legalFor({{s8, s8}, {s16, s16}, {s32, s32}})
+        .clampScalar(0, s8, s32)
+        .clampScalar(1, s8, s32);
+
+    // SDIV
+    getActionDefinitionsBuilder(G_SDIV)
         .legalFor({s8, s16, s32})
         .clampScalar(0, s8, s32);
   }
 
   // Control-flow
   setAction({G_BRCOND, s1}, Legal);
 
   // Constants
void X86LegalizerInfo::setLegalizerInfo64bit() {
   // Extensions
   for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
     setAction({extOp, s64}, Legal);
   }
 
   // Comparison
   setAction({G_ICMP, 1, s64}, Legal);
 
-  // Shifts and SDIV
-  getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
+  // Shifts
+  getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
+    .legalFor({{s8, s8}, {s16, s16}, {s32, s32}, {s64, s64}})
+    .clampScalar(0, s8, s64)
+    .clampScalar(1, s8, s64);
+
+  // SDIV
+  getActionDefinitionsBuilder(G_SDIV)
     .legalFor({s8, s16, s32, s64})
     .clampScalar(0, s8, s64);
 
   // Merge/Unmerge
   setAction({G_MERGE_VALUES, s128}, Legal);
   setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
   setAction({G_MERGE_VALUES, 1, s128}, Legal);
   setAction({G_UNMERGE_VALUES, s128}, Legal);

test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test_shift() {
   entry:
     ret void
   }
+  define void @test_vector_shift() {
+  entry:
+    ret void
+  }
 ...
 
 ---
 name:            test_shift
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }
+  - { id: 7, class: _ }
+  - { id: 8, class: _ }
+  - { id: 9, class: _ }
+  - { id: 10, class: _ }
+  - { id: 11, class: _ }
+tracksRegLiveness: true
 body: |
   bb.0.entry:
-    liveins: $x0, $x1, $x2, $x3
+    liveins: $x0, $w1, $w2
+
     ; CHECK-LABEL: name: test_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $x0, $w1, $w2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[AND]](s32)
+    ; CHECK: $w1 = COPY [[ASHR]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
-    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]]
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
-    ; CHECK: $w0 = COPY [[COPY2]](s32)
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY]](s64)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: $w1 = COPY [[COPY5]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64)
+    ; CHECK: $x0 = COPY [[SHL]](s64)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[COPY1]](s32)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
+    ; CHECK: $w1 = COPY [[COPY7]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
     ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND2]]
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: $w0 = COPY [[COPY3]](s32)
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C4]]
-    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[AND3]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
-    ; CHECK: $w0 = COPY [[COPY4]](s32)
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND3]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
+    ; CHECK: $w1 = COPY [[COPY10]](s32)
     %0(s64) = COPY $x0
-    %1(s64) = COPY $x1
-    %2(s8) = G_TRUNC %0
-    %3(s8) = G_TRUNC %1
-
-    %4(s8) = G_ASHR %2, %3
-    %7:_(s32) = G_ANYEXT %4
-    $w0 = COPY %7
-
-
-    %5(s8) = G_LSHR %2, %3
-    %8:_(s32) = G_ANYEXT %5
-    $w0 = COPY %8
-
-    %6(s8) = G_SHL %2, %3
-    %9:_(s32) = G_ANYEXT %6
-    $w0 = COPY %9
+    %1(s32) = COPY $w1
+    %2(s32) = COPY $w2
+    %3(s8) = G_TRUNC %2
+
+    %4(s32) = G_ASHR %1, %3(s8)
+    $w1 = COPY %4
+
+    %5(s8) = G_LSHR %3, %0(s64)
+    %6(s32) = G_ANYEXT %5
+    $w1 = COPY %6
+
+    %7(s64) = G_SHL %0, %3(s8)
+    $x0 = COPY %7
+
+    %8(s8) = G_SHL %3, %1(s32)
+    %9(s32) = G_ANYEXT %8
+    $w1 = COPY %9
+
+    %10(s8) = G_SHL %3, %3(s8)
+    %11(s32) = G_ANYEXT %10
+    $w1 = COPY %11
+...
+
+---
+name:            test_vector_shift
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+  - { id: 6, class: _ }
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; CHECK-LABEL: name: test_vector_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $q0, $d0
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[C]](s32)
+    ; CHECK: $q1 = COPY [[SHL]](<4 x s32>)
+    ; CHECK: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL1:%[0-9]+]]:_(<4 x s32>) = G_SHL [[SEXT]], [[C1]](s32)
+    ; CHECK: $q2 = COPY [[SHL1]](<4 x s32>)
+    %0(<4 x s32>) = COPY $q0
+    %5(<4 x s16>) = COPY $d0
+
+    %1(s32) = G_CONSTANT i32 3
+    %2(<4 x s32>) = G_SHL %0, %1(s32)
+    $q1 = COPY %2
+
+    %6(<4 x s32>) = G_SEXT %5(<4 x s16>)
+    %3(s32) = G_CONSTANT i32 16
+    %4(<4 x s32>) = G_SHL %6, %3(s32)
+    $q2 = COPY %4
 ...

test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_ZEXT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
-# DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 1 type index
-# DEBUG:      .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 2 type indices
+# DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected
 #
-# DEBUG-NEXT: G_LSHR (opcode {{[0-9]+}}): 1 type index
-# DEBUG:      .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: G_LSHR (opcode {{[0-9]+}}): 2 type indices
+# DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected
 #
-# DEBUG-NEXT: G_ASHR (opcode {{[0-9]+}}): 1 type index
-# DEBUG:      .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: G_ASHR (opcode {{[0-9]+}}): 2 type indices
+# DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected
 #
 # DEBUG-NEXT: G_ICMP (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_FCMP (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_SELECT (opcode {{[0-9]+}}): 2 type indices

test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -disable-gisel-legality-check %s -o - | FileCheck %s
 
 # Check the default mappings for various instructions.
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @test_add_s32() { ret void }
   define void @test_add_v4s32() { ret void }

test/CodeGen/AArch64/GlobalISel/regbankselect-shift.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_shift() {
+  entry:
+    ret void
+  }
+  define void @test_vector_shift() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_shift
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w1, $w2
+
+    ; CHECK-LABEL: name: test_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $x0, $w1, $w2
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 255
+    ; CHECK: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY2]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY1]], [[AND]](s32)
+    ; CHECK: $w1 = COPY [[ASHR]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 255
+    ; CHECK: [[AND1:%[0-9]+]]:gpr(s32) = G_AND [[COPY2]], [[C1]]
+    ; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[AND1]], [[COPY]](s64)
+    ; CHECK: $w1 = COPY [[LSHR]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 255
+    ; CHECK: [[ANYEXT:%[0-9]+]]:gpr(s64) = G_ANYEXT [[COPY2]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:gpr(s64) = G_AND [[ANYEXT]], [[C2]]
+    ; CHECK: [[SHL:%[0-9]+]]:gpr(s64) = G_SHL [[COPY]], [[AND2]](s64)
+    ; CHECK: $x0 = COPY [[SHL]](s64)
+    ; CHECK: [[COPY3:%[0-9]+]]:gpr(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:gpr(s32) = G_SHL [[COPY3]], [[COPY1]](s32)
+    ; CHECK: $w1 = COPY [[SHL1]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY4:%[0-9]+]]:gpr(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:gpr(s32) = G_AND [[COPY4]], [[C3]]
+    ; CHECK: [[SHL2:%[0-9]+]]:gpr(s32) = G_SHL [[COPY2]], [[AND3]](s32)
+    ; CHECK: $w1 = COPY [[SHL2]](s32)
+    %0:_(s64) = COPY $x0
+    %1:_(s32) = COPY $w1
+    %2:_(s32) = COPY $w2
+
+    %21:_(s32) = G_CONSTANT i32 255
+    %20:_(s32) = G_AND %2, %21
+    %4:_(s32) = G_ASHR %1, %20(s32)
+    $w1 = COPY %4(s32)
+
+    %23:_(s32) = G_CONSTANT i32 255
+    %18:_(s32) = G_AND %2, %23
+    %19:_(s32) = G_LSHR %18, %0(s64)
+    $w1 = COPY %19(s32)
+
+    %25:_(s64) = G_CONSTANT i64 255
+    %24:_(s64) = G_ANYEXT %2(s32)
+    %17:_(s64) = G_AND %24, %25
+    %7:_(s64) = G_SHL %0, %17(s64)
+    $x0 = COPY %7(s64)
+
+    %15:_(s32) = COPY %2(s32)
+    %16:_(s32) = G_SHL %15, %1(s32)
+    $w1 = COPY %16(s32)
+
+    %27:_(s32) = G_CONSTANT i32 255
+    %28:_(s32) = COPY %2(s32)
+    %14:_(s32) = G_AND %28, %27
+    %13:_(s32) = G_SHL %2, %14(s32)
+    $w1 = COPY %13(s32)
+...
+
+---
+name:            test_vector_shift
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; CHECK-LABEL: name: test_vector_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $q0, $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+    ; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[C]](s32)
+    ; CHECK: $q1 = COPY [[SHL]](<4 x s32>)
+    ; CHECK: [[SEXT:%[0-9]+]]:fpr(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
+    ; CHECK: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL1:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[SEXT]], [[C1]](s32)
+    ; CHECK: $q2 = COPY [[SHL1]](<4 x s32>)
+    %0:_(<4 x s32>) = COPY $q0
+    %5:_(<4 x s16>) = COPY $d0
+
+    %1:_(s32) = G_CONSTANT i32 3
+    %2:_(<4 x s32>) = G_SHL %0, %1(s32)
+    $q1 = COPY %2(<4 x s32>)
+
+    %6:_(<4 x s32>) = G_SEXT %5(<4 x s16>)
+    %3:_(s32) = G_CONSTANT i32 16
+    %4:_(<4 x s32>) = G_SHL %6, %3(s32)
+    $q2 = COPY %4(<4 x s32>)
+...

test/CodeGen/AArch64/GlobalISel/select-shift.mir

+# RUN: llc -O0 -run-pass=instruction-select %s -o - | FileCheck %s
+# RUN: llc -O0 -start-before=instruction-select %s -o - | FileCheck %s --check-prefix=ASM
+
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_shift() {
+  entry:
+    ret void
+  }
+  define void @test_vector_shift() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_shift
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w1, $w2
+
+    ; CHECK-LABEL: name: test_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $x0, $w1, $w2
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 255
+    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY2]], [[MOVi32imm]]
+    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY1]], [[ANDWrr]]
+    ; CHECK: $w1 = COPY [[ASRVWr]]
+    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 255
+    ; CHECK: [[ANDWrr1:%[0-9]+]]:gpr32 = ANDWrr [[COPY2]], [[MOVi32imm1]]
+    ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[ANDWrr1]], [[COPY3]]
+    ; CHECK: $w1 = COPY [[LSRVWr]]
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 255
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
+    ; CHECK: [[COPY4:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+    ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY4]], [[MOVi64imm]]
+    ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[ANDXrr]]
+    ; CHECK: $x0 = COPY [[LSLVXr]]
+    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY2]], [[COPY1]]
+    ; CHECK: $w1 = COPY [[LSLVWr]]
+    ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 255
+    ; CHECK: [[ANDWrr2:%[0-9]+]]:gpr32 = ANDWrr [[COPY2]], [[MOVi32imm2]]
+    ; CHECK: [[LSLVWr1:%[0-9]+]]:gpr32 = LSLVWr [[COPY2]], [[ANDWrr2]]
+    ; CHECK: $w1 = COPY [[LSLVWr1]]
+    %0:gpr(s64) = COPY $x0
+    %1:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w2
+
+    %3:gpr(s32) = G_CONSTANT i32 255
+    %4:gpr(s32) = G_AND %2, %3
+    %5:gpr(s32) = G_ASHR %1, %4(s32)
+    $w1 = COPY %5(s32)
+
+    %6:gpr(s32) = G_CONSTANT i32 255
+    %7:gpr(s32) = G_AND %2, %6
+    %8:gpr(s32) = G_LSHR %7, %0(s64)
+    $w1 = COPY %8(s32)
+
+    %9:gpr(s64) = G_CONSTANT i64 255
+    %10:gpr(s64) = G_ANYEXT %2(s32)
+    %11:gpr(s64) = G_AND %10, %9
+    %12:gpr(s64) = G_SHL %0, %11(s64)
+    $x0 = COPY %12(s64)
+
+    %13:gpr(s32) = COPY %2(s32)
+    %14:gpr(s32) = G_SHL %13, %1(s32)
+    $w1 = COPY %14(s32)
+
+    %15:gpr(s32) = G_CONSTANT i32 255
+    %16:gpr(s32) = COPY %2(s32)
+    %17:gpr(s32) = G_AND %16, %15
+    %18:gpr(s32) = G_SHL %2, %17(s32)
+    $w1 = COPY %18(s32)
+...
+
+---
+name:            test_vector_shift
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d6
+
+    ; CHECK-LABEL: name: test_vector_shift
+    ; CHECK-NOT: failedISel: true
+    ; CHECK: liveins: $q0, $d6
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d6
+    ; CHECK: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 3
+    ; CHECK: $q1 = COPY [[SHLv4i32_shift]]
+    ; CHECK: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 [[COPY1]]
+    ; CHECK: $q2 = COPY [[SHLLv4i16_]]
+
+    ; ASM-LABEL: test_vector_shift:
+    ; ASM:       shl   v1.4s, v0.4s, #3
+    ; ASM-NEXT:  shll  v2.4s, v6.4h, #16
+
+    %0:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s16>) = COPY $d6
+
+    %2:gpr(s32) = G_CONSTANT i32 3
+    %3:fpr(<4 x s32>) = G_SHL %0, %2(s32)
+    $q1 = COPY %3(<4 x s32>)
+
+    %4:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
+    %5:gpr(s32) = G_CONSTANT i32 16
+    %6:fpr(<4 x s32>) = G_SHL %4, %5(s32)
+    $q2 = COPY %6(<4 x s32>)
+...