Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -83,6 +83,7 @@
 STATISTIC(OpsNarrowed     , "Number of load/op/store narrowed");
 STATISTIC(LdStFP2Int      , "Number of fp load/store pairs transformed to int");
 STATISTIC(SlicedLoads, "Number of load sliced");
+STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops");
 
 static cl::opt<bool>
 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
@@ -9843,19 +9844,29 @@
     FPOpcode = ISD::FNEG;
     SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits());
     break;
-  // TODO: ISD::OR --> ISD::FNABS?
+  case ISD::OR:
+    FPOpcode = ISD::FABS;
+    SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits());
+    break;
   default:
     return SDValue();
   }
 
   // Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
   // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
+  // Fold (bitcast int (or (bitcast fp X to int), 0x8000...) to fp) ->
+  //   fneg (fabs X)
   SDValue LogicOp0 = N0.getOperand(0);
   ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true);
   if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask &&
       LogicOp0.getOpcode() == ISD::BITCAST &&
-      LogicOp0.getOperand(0).getValueType() == VT)
-    return DAG.getNode(FPOpcode, SDLoc(N), VT, LogicOp0.getOperand(0));
+      LogicOp0.getOperand(0).getValueType() == VT) {
+    SDValue FPOp = DAG.getNode(FPOpcode, SDLoc(N), VT, LogicOp0.getOperand(0));
+    NumFPLogicOpsConv++;
+    if (N0.getOpcode() == ISD::OR)
+      return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp);
+    return FPOp;
+  }
 
   return SDValue();
 }
Index: test/CodeGen/AArch64/fabs.ll
===================================================================
--- test/CodeGen/AArch64/fabs.ll
+++ test/CodeGen/AArch64/fabs.ll
@@ -37,9 +37,8 @@
 define float @nabsf(float %a) {
 ; CHECK-LABEL: nabsf:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    orr w8, w8, #0x80000000
-; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fabs s0, s0
+; CHECK-NEXT:    fneg s0, s0
 ; CHECK-NEXT:    ret
   %conv = bitcast float %a to i32
   %and = or i32 %conv, -2147483648
@@ -50,9 +49,8 @@
 define double @nabsd(double %a) {
 ; CHECK-LABEL: nabsd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov x8, d0
-; CHECK-NEXT:    orr x8, x8, #0x8000000000000000
-; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    fabs d0, d0
+; CHECK-NEXT:    fneg d0, d0
 ; CHECK-NEXT:    ret
   %conv = bitcast double %a to i64
   %and = or i64 %conv, -9223372036854775808
Index: test/CodeGen/PowerPC/float-logic-ops.ll
===================================================================
--- test/CodeGen/PowerPC/float-logic-ops.ll
+++ test/CodeGen/PowerPC/float-logic-ops.ll
@@ -124,3 +124,51 @@
   %conv1 = bitcast <2 x i64> %and to <2 x double>
   ret <2 x double> %conv1
 }
+define float @nabsf(float %a) {
+; CHECK-LABEL: nabsf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fnabs f1, f1
+; CHECK-NEXT:    blr
+entry:
+  %conv = bitcast float %a to i32
+  %and = or i32 %conv, -2147483648
+  %conv1 = bitcast i32 %and to float
+  ret float %conv1
+}
+
+define double @nabsd(double %a) {
+; CHECK-LABEL: nabsd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsnabsdp f1, f1
+; CHECK-NEXT:    blr
+entry:
+  %conv = bitcast double %a to i64
+  %and = or i64 %conv, -9223372036854775808
+  %conv1 = bitcast i64 %and to double
+  ret double %conv1
+}
+
+define <4 x float> @nabsv4f32(<4 x float> %a) {
+; CHECK-LABEL: nabsv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvnabssp vs34, vs34
+; CHECK-NEXT:    blr
+entry:
+  %conv = bitcast <4 x float> %a to <4 x i32>
+  %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+  %conv1 = bitcast <4 x i32> %and to <4 x float>
+  ret <4 x float> %conv1
+}
+
+define <2 x double> @nabsv2d64(<2 x double> %a) {
+; CHECK-LABEL: nabsv2d64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvnabsdp vs34, vs34
+; CHECK-NEXT:    blr
+entry:
+  %conv = bitcast <2 x double> %a to <2 x i64>
+  %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
+  %conv1 = bitcast <2 x i64> %and to <2 x double>
+  ret <2 x double> %conv1
+}
+
Index: test/CodeGen/X86/fp-logic.ll
===================================================================
--- test/CodeGen/X86/fp-logic.ll
+++ test/CodeGen/X86/fp-logic.ll
@@ -311,8 +311,7 @@
 define float @nabsf(float %a) {
 ; CHECK-LABEL: nabsf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %conv = bitcast float %a to i32
   %and = or i32 %conv, -2147483648
@@ -323,8 +322,7 @@
 define double @nabsd(double %a) {
 ; CHECK-LABEL: nabsd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %conv = bitcast double %a to i64
   %and = or i64 %conv, -9223372036854775808