Index: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h @@ -96,6 +96,8 @@ void printRegOperand(unsigned RegNo, raw_ostream &O); void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printVINTRPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, + raw_ostream &O); void printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O); void printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI, Index: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -380,6 +380,16 @@ printOperand(MI, OpNo, STI, O); } +void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O) { + if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) + O << " "; + else + O << "_e32 "; + + printOperand(MI, OpNo, STI, O); +} + void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) { Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -1937,6 +1937,8 @@ // Interpolation opcodes //===----------------------------------------------------------------------===// +class VINTRPDstOperand : RegisterOperand ; + class VINTRP_Pseudo pattern> : VINTRPCommon , SIMCInstr { Index: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td @@ -40,15 +40,18 @@ // VINTRP Instructions //===----------------------------------------------------------------------===// +// Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI) +def VINTRPDst : VINTRPDstOperand ; + let Uses = [M0, EXEC] in { // FIXME: Specify SchedRW for VINTRP insturctions. multiclass V_INTERP_P1_F32_m : VINTRP_m < 0x00000000, - (outs VGPR_32:$vdst), + (outs VINTRPDst:$vdst), (ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan), - "v_interp_p1_f32 $vdst, $vsrc, $attr$attrchan", + "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan", [(set f32:$vdst, (AMDGPUinterp_p1 f32:$vsrc, (i32 imm:$attrchan), (i32 imm:$attr)))] >; @@ -69,9 +72,9 @@ defm V_INTERP_P2_F32 : VINTRP_m < 0x00000001, - (outs VGPR_32:$vdst), + (outs VINTRPDst:$vdst), (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan), - "v_interp_p2_f32 $vdst, $vsrc, $attr$attrchan", + "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan", [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 imm:$attrchan), (i32 imm:$attr)))]>; @@ -79,9 +82,9 @@ defm V_INTERP_MOV_F32 : VINTRP_m < 0x00000002, - (outs VGPR_32:$vdst), + (outs VINTRPDst:$vdst), (ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan), - "v_interp_mov_f32 $vdst, $vsrc, $attr$attrchan", + "v_interp_mov_f32$vdst, $vsrc, $attr$attrchan", [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan), (i32 imm:$attr)))]>; Index: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll @@ -6,10 +6,10 @@ ; GCN-LABEL: {{^}}v_interp: ; GCN-NOT: s_wqm ; GCN: s_mov_b32 m0, s{{[0-9]+}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p0, attr0.x{{$}} define amdgpu_ps void @v_interp(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x float> %arg4) #0 { main_body: %i = extractelement <2 x float> %arg4, i32 0 @@ -26,19 +26,19 @@ ; GCN-LABEL: {{^}}v_interp_p1: ; GCN: s_movk_i32 m0, 0x100 -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} - -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr1.x{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr2.y{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr3.z{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr4.w{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr63.w{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.w{{$}} -; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} + +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr1.x{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr2.y{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr3.z{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr4.w{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr63.w{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.w{{$}} +; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} define amdgpu_ps void @v_interp_p1(float %i) #0 { bb: %p0_0 = call float @llvm.amdgcn.interp.p1(float %i, i32 0, i32 0, i32 256) @@ -71,15 +71,15 @@ ; GCN-LABEL: {{^}}v_interp_p2: ; GCN: s_movk_i32 m0, 0x100 -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr63.x{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} -; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr63.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} +; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}} define amdgpu_ps void @v_interp_p2(float %x, float %j) #0 { bb: %p2_0 = call float @llvm.amdgcn.interp.p2(float %x, float %j, i32 0, i32 0, i32 256) @@ -107,21 +107,21 @@ ; GCN-LABEL: {{^}}v_interp_mov: ; GCN: s_movk_i32 m0, 0x100 -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p20, attr0.x{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_3, attr0.x{{$}} - -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.z{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.w{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_8, attr0.x{{$}} - -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr63.y{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr64.y{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_3, attr64.y{{$}} -; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_10, attr64.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p20, attr0.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p0, attr0.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_3, attr0.x{{$}} + +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.z{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.w{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_8, attr0.x{{$}} + +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr63.y{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr64.y{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_3, attr64.y{{$}} +; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_10, attr64.x{{$}} define amdgpu_ps void @v_interp_mov(float %x, float %j) #0 { bb: %mov_0 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 0, i32 256) @@ -167,7 +167,7 @@ ; TODO-VI-LABEL: v_interp_readnone: ; TODO-VI: s_mov_b32 m0, 0 ; TODO-VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 -; TODO-VI-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}} +; TODO-VI-DAG: v_interp_mov_f32_e32 v{{[0-9]+}}, p0, attr0.x{{$}} ; TODO-VI: s_mov_b32 m0, -1{{$}} ; TODO-VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4 ;define amdgpu_ps void @v_interp_readnone(float addrspace(3)* %lds) #0 { @@ -184,7 +184,7 @@ ; on 16 bank LDS chips. ; GCN-LABEL: {{^}}v_interp_p1_bank16_bug: -; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]] +; 16BANK-NOT: v_interp_p1_f32{{(_e32)*}} [[DST:v[0-9]+]], [[DST]] define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg13, [17 x <4 x i32>] addrspace(2)* byval %arg14, [34 x <8 x i32>] addrspace(2)* byval %arg15, float inreg %arg16, i32 inreg %arg17, <2 x i32> %arg18, <2 x i32> %arg19, <2 x i32> %arg20, <3 x i32> %arg21, <2 x i32> %arg22, <2 x i32> %arg23, <2 x i32> %arg24, float %arg25, float %arg26, float %arg27, float %arg28, float %arg29, float %arg30, i32 %arg31, float %arg32, float %arg33) #0 { main_body: %i.i = extractelement <2 x i32> %arg19, i32 0 Index: llvm/trunk/test/MC/AMDGPU/vintrp.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/vintrp.s +++ llvm/trunk/test/MC/AMDGPU/vintrp.s @@ -3,103 +3,103 @@ v_interp_p1_f32 v1, v0, attr0.x // SI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xc8] -// VI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4] +// VI: v_interp_p1_f32_e32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4] v_interp_p1_f32 v2, v0, attr0.y // SI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xc8] -// VI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4] +// VI: v_interp_p1_f32_e32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4] v_interp_p1_f32 v3, v0, attr0.z // SI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xc8] -// VI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4] +// VI: v_interp_p1_f32_e32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4] v_interp_p1_f32 v4, v0, attr0.w // SI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xc8] -// VI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4] +// VI: v_interp_p1_f32_e32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4] v_interp_p1_f32 v5, v0, attr0.x // SI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xc8] -// VI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4] +// VI: v_interp_p1_f32_e32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4] v_interp_p1_f32 v6, v0, attr1.x // SI: v_interp_p1_f32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xc8] -// VI: v_interp_p1_f32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xd4] +// VI: v_interp_p1_f32_e32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xd4] v_interp_p1_f32 v7, v0, attr2.y // SI: v_interp_p1_f32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xc8] -// VI: v_interp_p1_f32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xd4] +// VI: v_interp_p1_f32_e32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xd4] v_interp_p1_f32 v8, v0, attr3.z // SI: v_interp_p1_f32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xc8] -// VI: v_interp_p1_f32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xd4] +// VI: v_interp_p1_f32_e32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xd4] v_interp_p1_f32 v9, v0, attr4.w // SI: v_interp_p1_f32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xc8] -// VI: v_interp_p1_f32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xd4] +// VI: v_interp_p1_f32_e32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xd4] v_interp_p1_f32 v10, v0, attr63.w // SI: v_interp_p1_f32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xc8] -// VI: v_interp_p1_f32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xd4] +// VI: v_interp_p1_f32_e32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xd4] v_interp_p2_f32 v2, v1, attr0.x // SI: v_interp_p2_f32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xc8] -// VI: v_interp_p2_f32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xd4] +// VI: v_interp_p2_f32_e32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xd4] v_interp_p2_f32 v3, v1, attr0.y // SI: v_interp_p2_f32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xc8] -// VI: v_interp_p2_f32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xd4] +// VI: v_interp_p2_f32_e32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xd4] v_interp_p2_f32 v4, v1, attr0.z // SI: v_interp_p2_f32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xc8] -// VI: v_interp_p2_f32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xd4] +// VI: v_interp_p2_f32_e32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xd4] v_interp_p2_f32 v5, v1, attr0.w // SI: v_interp_p2_f32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xc8] -// VI: v_interp_p2_f32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xd4] +// VI: v_interp_p2_f32_e32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xd4] v_interp_p2_f32 v6, v1, attr0.x // SI: v_interp_p2_f32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xc8] -// VI: v_interp_p2_f32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xd4] +// VI: v_interp_p2_f32_e32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xd4] v_interp_p2_f32 v7, v1, attr1.x // SI: v_interp_p2_f32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xc8] -// VI: v_interp_p2_f32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xd4] +// VI: v_interp_p2_f32_e32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xd4] v_interp_p2_f32 v8, v1, attr63.x // SI: v_interp_p2_f32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xc8] -// VI: v_interp_p2_f32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xd4] +// VI: v_interp_p2_f32_e32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xd4] v_interp_mov_f32 v0, p10, attr0.x // SI: v_interp_mov_f32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xc8] -// VI: v_interp_mov_f32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xd4] +// VI: v_interp_mov_f32_e32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xd4] v_interp_mov_f32 v1, p20, attr0.x // SI: v_interp_mov_f32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xc8] -// VI: v_interp_mov_f32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xd4] +// VI: v_interp_mov_f32_e32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xd4] v_interp_mov_f32 v2, p0, attr0.x // SI: v_interp_mov_f32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xc8] -// VI: v_interp_mov_f32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xd4] +// VI: v_interp_mov_f32_e32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xd4] v_interp_mov_f32 v4, p10, attr0.y // SI: v_interp_mov_f32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xc8] -// VI: v_interp_mov_f32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xd4] +// VI: v_interp_mov_f32_e32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xd4] v_interp_mov_f32 v5, p10, attr0.z // SI: v_interp_mov_f32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xc8] -// VI: v_interp_mov_f32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xd4] +// VI: v_interp_mov_f32_e32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xd4] v_interp_mov_f32 v6, p10, attr0.w // SI: v_interp_mov_f32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xc8] -// VI: v_interp_mov_f32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xd4] +// VI: v_interp_mov_f32_e32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xd4] v_interp_mov_f32 v7, p10, attr0.x // SI: v_interp_mov_f32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xc8] -// VI: v_interp_mov_f32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xd4] +// VI: v_interp_mov_f32_e32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xd4] v_interp_mov_f32 v9, p10, attr63.y // SI: v_interp_mov_f32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xc8] -// VI: v_interp_mov_f32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xd4] +// VI: v_interp_mov_f32_e32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xd4] Index: llvm/trunk/test/MC/Disassembler/AMDGPU/vintrp.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/vintrp.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/vintrp.txt @@ -1,49 +1,49 @@ # RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI -#VI: v_interp_p1_f32 v7, v212, attr16.y +#VI: v_interp_p1_f32_e32 v7, v212, attr16.y 0xd4 0x41 0x1c 0xd4 -#VI: v_interp_p2_f32 v7, v212, attr16.y +#VI: v_interp_p2_f32_e32 v7, v212, attr16.y 0xd4 0x41 0x1d 0xd4 -#VI: v_interp_mov_f32 v7, invalid_param_212, attr16.y +#VI: v_interp_mov_f32_e32 v7, invalid_param_212, attr16.y 0xd4 0x41 0x1e 0xd4 -#VI: v_interp_mov_f32 v7, p10, attr16.y +#VI: v_interp_mov_f32_e32 v7, p10, attr16.y 0x00 0x41 0x1e 0xd4 -#VI: v_interp_mov_f32 v7, p20, attr16.y +#VI: v_interp_mov_f32_e32 v7, p20, attr16.y 0x01 0x41 0x1e 0xd4 -#VI: v_interp_mov_f32 v7, p0, attr16.y +#VI: v_interp_mov_f32_e32 v7, p0, attr16.y 0x02 0x41 0x1e 0xd4 -#VI: v_interp_mov_f32 v7, invalid_param_3, attr16.y +#VI: v_interp_mov_f32_e32 v7, invalid_param_3, attr16.y 0x03 0x41 0x1e 0xd4 -# VI: v_interp_p1_f32 v0, v0, attr0.x +# VI: v_interp_p1_f32_e32 v0, v0, attr0.x 0x00 0x00 0x00 0xd4 -# VI: v_interp_p1_f32 v0, v0, attr0.x +# VI: v_interp_p1_f32_e32 v0, v0, attr0.x 0x00 0x00 0x00 0xd4 -# VI: v_interp_p1_f32 v0, v1, attr0.x +# VI: v_interp_p1_f32_e32 v0, v1, attr0.x 0x01 0x00 0x00 0xd4 -# VI: v_interp_p1_f32 v0, v1, attr0.w +# VI: v_interp_p1_f32_e32 v0, v1, attr0.w 0x01 0x03 0x00 0xd4 -# VI: v_interp_p2_f32 v0, v1, attr0.x +# VI: v_interp_p2_f32_e32 v0, v1, attr0.x 0x01 0x00 0x01 0xd4 -# VI: v_interp_mov_f32 v0, p20, attr0.x +# VI: v_interp_mov_f32_e32 v0, p20, attr0.x 0x01 0x00 0x02 0xd4 -#VI: v_interp_p2_f32 v0, v1, attr63.x +#VI: v_interp_p2_f32_e32 v0, v1, attr63.x 0x01 0xfc 0x01 0xd4 -#VI: v_interp_p2_f32 v0, v1, attr63.x +#VI: v_interp_p2_f32_e32 v0, v1, attr63.x 0x01 0xfc 0x01 0xd4 -#VI: v_interp_p2_f32 v0, v1, attr63.w +#VI: v_interp_p2_f32_e32 v0, v1, attr63.w 0x01 0xff 0x01 0xd4