Index: lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
===================================================================
--- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -262,10 +262,15 @@
   assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
 
   const ConstantInt *NewVal = &Val;
-  if (Ty.getSizeInBits() != Val.getBitWidth())
-    NewVal = ConstantInt::get(MF->getFunction().getContext(),
-                              Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
-
+  if (Ty.getSizeInBits() != Val.getBitWidth()) {
+    APInt V;
+    // Booleans should be zero extended.
+    if (Val.getBitWidth() == 1)
+      V = Val.getValue().zext(Ty.getSizeInBits());
+    else
+      V = Val.getValue().sextOrTrunc(Ty.getSizeInBits());
+    NewVal = ConstantInt::get(MF->getFunction().getContext(), V);
+  }
   return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
 }
 
Index: test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -44,6 +44,7 @@
     ; CHECK: %x0 = COPY [[C4]](s64)
     ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK: %x0 = COPY [[C5]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     %0(s1) = G_CONSTANT i1 0
     %6:_(s32) = G_ANYEXT %0
     %w0 = COPY %6
@@ -59,6 +60,8 @@
     %x0 = COPY %4
     %5(s64) = G_CONSTANT i64 0
     %x0 = COPY %5
+    %9:_(s1) = G_CONSTANT i1 1
+    %10:_(s32) = COPY %9
 ...
 
 ---
Index: test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -626,7 +626,7 @@
     ; SOFT-NOT: G_FCMP
     ; For soft float we just need to return a '-1' constant, but the truncation
     ; to 1 bit is converted by the combiner to the following masking sequence.
-    ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
     ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
@@ -1348,7 +1348,7 @@
     ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
     ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     ; SOFT-NOT: G_FCMP
-    ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; The result needs to be truncated, and the combiner turns the truncation
     ; into the following masking sequence.
     ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Index: test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -900,7 +900,7 @@
     %3(s1) = G_CONSTANT i1 1
     G_STORE %3(s1), %4(p0) :: (store 1)
     ; CHECK-NOT: G_CONSTANT i1
-    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i1