Index: llvm/trunk/include/llvm/MC/MCSchedule.h =================================================================== --- llvm/trunk/include/llvm/MC/MCSchedule.h +++ llvm/trunk/include/llvm/MC/MCSchedule.h @@ -15,6 +15,7 @@ #ifndef LLVM_MC_MCSCHEDULE_H #define LLVM_MC_MCSCHEDULE_H +#include "llvm/ADT/Optional.h" #include "llvm/Support/DataTypes.h" #include @@ -231,6 +232,11 @@ static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc); + /// Returns the reciprocal throughput information from a MCSchedClassDesc. + static Optional + getReciprocalThroughput(const MCSubtargetInfo &STI, + const MCSchedClassDesc &SCDesc); + /// Returns the default initialized model. static const MCSchedModel &GetDefaultSchedModel() { return Default; } static const MCSchedModel Default; Index: llvm/trunk/lib/CodeGen/TargetSchedule.cpp =================================================================== --- llvm/trunk/lib/CodeGen/TargetSchedule.cpp +++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp @@ -347,38 +347,13 @@ return Throughput; } -static Optional -getRThroughputFromInstrSchedModel(const MCSchedClassDesc *SCDesc, - const TargetSubtargetInfo *STI, - const MCSchedModel &SchedModel) { - Optional Throughput; - - for (const MCWriteProcResEntry *WPR = STI->getWriteProcResBegin(SCDesc), - *WEnd = STI->getWriteProcResEnd(SCDesc); - WPR != WEnd; ++WPR) { - if (WPR->Cycles) { - unsigned NumUnits = - SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits; - double Temp = NumUnits * 1.0 / WPR->Cycles; - Throughput = Throughput.hasValue() - ? std::min(Throughput.getValue(), Temp) - : Temp; - } - } - if (Throughput.hasValue()) - // We need reciprocal throughput that's why we return such value. - return 1 / Throughput.getValue(); - return Throughput; -} - Optional TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const { if (hasInstrItineraries()) return getRThroughputFromItineraries(MI->getDesc().getSchedClass(), getInstrItineraries()); if (hasInstrSchedModel()) - return getRThroughputFromInstrSchedModel(resolveSchedClass(MI), STI, - SchedModel); + return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI)); return Optional(); } @@ -388,9 +363,9 @@ if (hasInstrItineraries()) return getRThroughputFromItineraries(SchedClass, getInstrItineraries()); if (hasInstrSchedModel()) { - const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); - if (SCDesc->isValid() && !SCDesc->isVariant()) - return getRThroughputFromInstrSchedModel(SCDesc, STI, SchedModel); + const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); + if (SCDesc.isValid() && !SCDesc.isVariant()) + return MCSchedModel::getReciprocalThroughput(*STI, SCDesc); } return Optional(); } Index: llvm/trunk/lib/MC/MCSchedule.cpp =================================================================== --- llvm/trunk/lib/MC/MCSchedule.cpp +++ llvm/trunk/lib/MC/MCSchedule.cpp @@ -49,3 +49,27 @@ } return Latency; } + + +Optional +MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, + const MCSchedClassDesc &SCDesc) { + Optional Throughput; + const MCSchedModel &SchedModel = STI.getSchedModel(); + + for (const MCWriteProcResEntry *WPR = STI.getWriteProcResBegin(&SCDesc), + *WEnd = STI.getWriteProcResEnd(&SCDesc); + WPR != WEnd; ++WPR) { + if (WPR->Cycles) { + unsigned NumUnits = + SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits; + double Temp = NumUnits * 1.0 / WPR->Cycles; + Throughput = + Throughput.hasValue() ? std::min(Throughput.getValue(), Temp) : Temp; + } + } + + if (Throughput.hasValue()) + return 1 / Throughput.getValue(); + return Throughput; +}