Index: lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- lib/Target/AMDGPU/SIFoldOperands.cpp
+++ lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -471,7 +471,8 @@
                                                MachineOperand &Op) {
   if (Op.isReg()) {
     // If this has a subregister, it obviously is a register source.
-    if (Op.getSubReg() != AMDGPU::NoSubRegister)
+    if (Op.getSubReg() != AMDGPU::NoSubRegister ||
+        !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
       return &Op;
 
     MachineInstr *Def = MRI.getVRegDef(Op.getReg());
Index: test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
===================================================================
--- test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -804,3 +804,30 @@
     S_ENDPGM
 
 ...
+---
+# Make sure there is no crash if one of the operands is a physical register
+# GCN-LABEL: name: constant_fold_physreg_op{{$}}
+# GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
+
+name: constant_fold_physreg_op
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.3
+    liveins: $vgpr0, $sgpr4_sgpr5
+
+    %19:sreg_64 = IMPLICIT_DEF
+    %0:sreg_64 = SI_IF killed %19, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+    %6:sreg_64 = S_MOV_B64 0
+    %7:sreg_64 = S_AND_B64 $exec, killed %6, implicit-def dead $scc
+    $vcc = COPY %7
+
+  bb.3:
+    liveins: $vcc
+    SI_END_CF %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_ENDPGM implicit $vcc
+
+...