Index: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
@@ -9,7 +9,7 @@
 
 class MMDSPInst<string opstr = "">
     : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   let AdditionalPredicates = [InMicroMips];
   string BaseOpcode = opstr;
   string Arch = "mmdsp";
@@ -18,7 +18,7 @@
 
 class MMDSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
     : InstAlias<Asm, Result, Emit>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   let AdditionalPredicates = [InMicroMips];
 }
 
Index: llvm/trunk/lib/Target/Mips/Mips.td
===================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td
+++ llvm/trunk/lib/Target/Mips/Mips.td
@@ -28,8 +28,10 @@
   list<Predicate> PTRPredicates = [];
   // Predicates for the FGR size and layout such as IsFP64bit
   list<Predicate> FGRPredicates = [];
-  // Predicates for the instruction group membership such as ISA's and ASE's
+  // Predicates for the instruction group membership such as ISA's.
   list<Predicate> InsnPredicates = [];
+  // Predicate for the ASE that an instruction belongs to.
+  list<Predicate> ASEPredicate = [];
   // Predicate for marking the instruction as usable in hard-float mode only.
   list<Predicate> HardFloatPredicate = [];
   // Predicates for anything else
@@ -40,6 +42,7 @@
                                            FGRPredicates,
                                            InsnPredicates,
                                            HardFloatPredicate,
+                                           ASEPredicate,
                                            AdditionalPredicates);
 }
 
Index: llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -29,11 +29,11 @@
                AssemblerPredicate<"FeatureDSPR3">;
 
 class ISA_DSPR2 {
-  list<Predicate> InsnPredicates = [HasDSPR2];
+  list<Predicate> ASEPredicate = [HasDSPR2];
 }
 
 class ISA_DSPR3 {
-  list<Predicate> InsnPredicates = [HasDSPR3];
+  list<Predicate> ASEPredicate = [HasDSPR3];
 }
 
 // Fields.
@@ -46,7 +46,7 @@
 
 class DSPInst<string opstr = "">
     : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   string BaseOpcode = opstr;
   string Arch = "dsp";
 }
@@ -54,12 +54,12 @@
 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
                 InstrItinClass itin = IIPseudo>
     : MipsPseudo<outs, ins, pattern, itin> {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
 }
 
 class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
     : InstAlias<Asm, Result, Emit>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
 }
 
 // ADDU.QB sub-class format.
Index: llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td
@@ -178,37 +178,37 @@
 //===----------------------------------------------------------------------===//
 
 /// Load and Store EVA Instructions
-def LBE     : MMRel, LBE_ENC, LBE_DESC, INSN_EVA;
-def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA;
-def LHE     : MMRel, LHE_ENC, LHE_DESC, INSN_EVA;
-def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA;
+def LBE     : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
+def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
+def LHE     : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
+def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
 let AdditionalPredicates = [NotInMicroMips] in {
-def LWE     : MMRel, LWE_ENC, LWE_DESC, INSN_EVA;
+def LWE     : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
 }
-def SBE     : MMRel, SBE_ENC, SBE_DESC, INSN_EVA;
-def SHE     : MMRel, SHE_ENC, SHE_DESC, INSN_EVA;
+def SBE     : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
+def SHE     : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
 let AdditionalPredicates = [NotInMicroMips] in {
-def SWE     : MMRel, SWE_ENC, SWE_DESC, INSN_EVA;
+def SWE     : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
 }
 
 /// load/store left/right EVA
 let AdditionalPredicates = [NotInMicroMips] in {
-def LWLE    : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6;
-def LWRE    : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6;
-def SWLE    : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6;
-def SWRE    : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6;
+def LWLE    : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def LWRE    : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def SWLE    : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def SWRE    : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
 }
 
 /// Load-linked EVA, Store-conditional EVA
 let AdditionalPredicates = [NotInMicroMips] in {
-def LLE     : MMRel, LLE_ENC, LLE_DESC, INSN_EVA;
-def SCE     : MMRel, SCE_ENC, SCE_DESC, INSN_EVA;
+def LLE     : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
+def SCE     : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
-  def TLBINV  : TLBINV_ENC, TLBINV_DESC, INSN_EVA;
-  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA;
+  def TLBINV  : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
+  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
 }
 
-def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA;
-def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA;
+def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
+def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -361,10 +361,7 @@
   list<Predicate> InsnPredicates = [NotMips32r6];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
-class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
-class INSN_EVA_NOT_32R6_64R6 {
-  list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
-}
+class ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; }
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 {
@@ -419,31 +416,31 @@
 }
 
 class ASE_CNMIPS {
-  list<Predicate> InsnPredicates = [HasCnMips];
+  list<Predicate> ASEPredicate = [HasCnMips];
 }
 
 class NOT_ASE_CNMIPS {
-  list<Predicate> InsnPredicates = [NotCnMips];
+  list<Predicate> ASEPredicate = [NotCnMips];
 }
 
 class ASE_MIPS64_CNMIPS {
-  list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
+  list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
 }
 
 class ASE_MSA {
-  list<Predicate> InsnPredicates = [HasMSA];
+  list<Predicate> ASEPredicate = [HasMSA];
 }
 
 class ASE_MSA_NOT_MSA64 {
-  list<Predicate> InsnPredicates = [HasMSA, NotMips64];
+  list<Predicate> ASEPredicate = [HasMSA, NotMips64];
 }
 
 class ASE_MSA64 {
-  list<Predicate> InsnPredicates = [HasMSA, HasMips64];
+  list<Predicate> ASEPredicate = [HasMSA, HasMips64];
 }
 
 class ASE_MT {
-  list <Predicate> InsnPredicates = [HasMT];
+  list <Predicate> ASEPredicate = [HasMT];
 }
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
@@ -454,7 +451,7 @@
 }
 
 class ASE_NOT_DSP {
-  list<Predicate> InsnPredicates = [NotDSP];
+  list<Predicate> ASEPredicate = [NotDSP];
 }
 
 class MADD4 {