Index: lib/Target/AMDGPU/AMDGPUInstructions.td =================================================================== --- lib/Target/AMDGPU/AMDGPUInstructions.td +++ lib/Target/AMDGPU/AMDGPUInstructions.td @@ -248,6 +248,10 @@ return cast(N)->getAlignment() % 8 == 0; }]>; +class Aligned16Bytes : PatFrag (N)->getAlignment() >= 16; +}]>; + class LoadFrag : PatFrag<(ops node:$ptr), (op node:$ptr)>; class StoreFrag : PatFrag < @@ -371,6 +375,10 @@ (ops node:$ptr), (load_local node:$ptr) >; +def load_align16_local : Aligned16Bytes < + (ops node:$ptr), (load_local node:$ptr) +>; + def store_align8_local : Aligned8Bytes < (ops node:$val, node:$ptr), (store_local node:$val, node:$ptr) >; Index: lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.h +++ lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -414,6 +414,12 @@ return FlatForGlobal; } + /// \returns If target supports ds_read/write_b128 and user enables generation + /// of ds_read/write_b128. + bool useDS128(bool UserEnable) const { + return CIInsts && UserEnable; + } + /// \returns If MUBUF instructions always perform range checking, even for /// buffer resources used for private memory access. bool privateMemoryResourceIsRangeChecked() const { Index: lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -265,11 +265,11 @@ return 512; } - if (AddrSpace == AS.FLAT_ADDRESS) - return 128; - if (AddrSpace == AS.LOCAL_ADDRESS || + if (AddrSpace == AS.FLAT_ADDRESS || + AddrSpace == AS.LOCAL_ADDRESS || AddrSpace == AS.REGION_ADDRESS) - return 64; + return 128; + if (AddrSpace == AS.PRIVATE_ADDRESS) return 8 * ST->getMaxPrivateElementSize(); Index: lib/Target/AMDGPU/DSInstructions.td =================================================================== --- lib/Target/AMDGPU/DSInstructions.td +++ lib/Target/AMDGPU/DSInstructions.td @@ -649,6 +649,7 @@ let AddedComplexity = 100 in { defm : DSReadPat_mc ; +defm : DSReadPat_mc ; } // End AddedComplexity = 100 Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -94,6 +94,11 @@ cl::desc("Use GPR indexing mode instead of movrel for vector indexing"), cl::init(false)); +static cl::opt EnableDS128( + "amdgpu-ds128", + cl::desc("Use DS_read/write_b128"), + cl::init(false)); + static cl::opt AssumeFrameIndexHighZeroBits( "amdgpu-frame-index-zero-bits", cl::desc("High bits of frame index assumed to be zero"), @@ -5425,14 +5430,13 @@ llvm_unreachable("unsupported private_element_size"); } } else if (AS == AMDGPUASI.LOCAL_ADDRESS) { - if (NumElements > 2) - return SplitVectorLoad(Op, DAG); - - if (NumElements == 2) + // Use ds_read_b128 if possible. + if (Subtarget->useDS128(EnableDS128) && Load->getAlignment() >= 16 && + MemVT.getStoreSize() == 16) return SDValue(); - // If properly aligned, if we split we might be able to use ds_read_b64. - return SplitVectorLoad(Op, DAG); + if (NumElements > 2) + return SplitVectorLoad(Op, DAG); } return SDValue(); } Index: lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.td +++ lib/Target/AMDGPU/SIInstrInfo.td @@ -410,6 +410,9 @@ def load_glue_align8 : Aligned8Bytes < (ops node:$ptr), (load_glue node:$ptr) >; +def load_glue_align16 : Aligned16Bytes < + (ops node:$ptr), (load_glue node:$ptr) +>; def load_local_m0 : LoadFrag, LocalAddress; @@ -418,6 +421,7 @@ def az_extloadi8_local_m0 : LoadFrag, LocalAddress; def az_extloadi16_local_m0 : LoadFrag, LocalAddress; def load_align8_local_m0 : LoadFrag , LocalAddress; +def load_align16_local_m0 : LoadFrag , LocalAddress; def AMDGPUst_glue : SDNode <"ISD::STORE", SDTStore, Index: test/CodeGen/AMDGPU/load-local-i32.ll =================================================================== --- test/CodeGen/AMDGPU/load-local-i32.ll +++ test/CodeGen/AMDGPU/load-local-i32.ll @@ -3,6 +3,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s + ; FUNC-LABEL: {{^}}local_load_i32: ; GCN-NOT: s_wqm_b64 ; SICIVI: s_mov_b32 m0, -1 @@ -175,6 +179,19 @@ ret void } +; FUNC-LABEL: {{^}}local_v4i32_to_128: +; SI-NOT: ds_read_b128 +; CIVI: ds_read_b128 +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define amdgpu_kernel void @local_v4i32_to_128(<4 x i32> addrspace(3)* %out, <4 x i32> addrspace(3)* %in) { + %ld = load <4 x i32>, <4 x i32> addrspace(3)* %in, align 16 + store <4 x i32> %ld, <4 x i32> addrspace(3)* %out + ret void +} + ; FUNC-LABEL: {{^}}local_zextload_v8i32_to_v8i64: ; SICIVI: s_mov_b32 m0, -1 ; GFX9-NOT: m0 Index: test/CodeGen/AMDGPU/load-local-i64.ll =================================================================== --- test/CodeGen/AMDGPU/load-local-i64.ll +++ test/CodeGen/AMDGPU/load-local-i64.ll @@ -4,6 +4,9 @@ ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s + ; FUNC-LABEL: {{^}}local_load_i64: ; SICIVI: s_mov_b32 m0 ; GFX9-NOT: m0 @@ -36,6 +39,15 @@ ret void } +; FUNC-LABEL: {{^}}local_load_v2i64_to_128: +; CIVI: ds_read_b128 +define amdgpu_kernel void @local_load_v2i64_to_128(<2 x i64> addrspace(3)* %out, <2 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <2 x i64>, <2 x i64> addrspace(3)* %in + store <2 x i64> %ld, <2 x i64> addrspace(3)* %out + ret void +} + ; FUNC-LABEL: {{^}}local_load_v3i64: ; SICIVI: s_mov_b32 m0 ; GFX9-NOT: m0 Index: test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll =================================================================== --- test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -504,8 +504,7 @@ } ; CHECK-LABEL: @merge_local_store_4_constants_i32 -; CHECK: store <2 x i32> , <2 x i32> addrspace(3)* -; CHECK: store <2 x i32> , <2 x i32> addrspace(3)* +; CHECK: store <4 x i32> , <4 x i32> addrspace(3)* define amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1 %out.gep.2 = getelementptr i32, i32 addrspace(3)* %out, i32 2 Index: test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll =================================================================== --- test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll +++ test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll @@ -29,11 +29,10 @@ ; longest chain vectorized ; CHECK-LABEL: @interleave_get_longest -; CHECK: load <2 x i32> +; CHECK: load <4 x i32> ; CHECK: load i32 ; CHECK: store <2 x i32> zeroinitializer ; CHECK: load i32 -; CHECK: load <2 x i32> ; CHECK: load i32 ; CHECK: load i32