Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -777,32 +777,49 @@ def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel, LW_FM_MM<0x3e>; } - +} +let DecoderNamespace = "MicroMips" in { let DecoderMethod = "DecodeMemMMImm9" in { def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>, - POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA; def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>, - POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; - def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, - null_frag, II_LHE>, - POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; - def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, - null_frag, II_LHUE>, - POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; - def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, - null_frag, II_LWE>, - POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>; - def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, - null_frag, II_SBE>, - POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>; - def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, - null_frag, II_SHE>, - POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>; - def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, - null_frag, II_SWE>, - POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>; - } + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA; + def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, + II_LHE>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA; + def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, + II_LHUE>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA; + def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, + II_LWE>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA; + def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, + II_SBE>, + POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA; + def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag, + II_SHE>, + POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA; + def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag, + II_SWE>, + POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA; + def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9, + II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>, + ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA; + def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9, + II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>, + ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA; + def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9, + II_SWLE>, + POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>, + ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA; + def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9, + II_SWRE>, + POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, + ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA; + } +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>; /// Load and Store Instructions - unaligned @@ -814,18 +831,6 @@ LWL_FM_MM<0x8>; def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>, LWL_FM_MM<0x9>; - let DecoderMethod = "DecodeMemMMImm9" in { - def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9, - II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>; - def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9, - II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>; - def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9, - II_SWLE>, - POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>; - def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9, - II_SWRE>, - POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6; - } /// Load and Store Instructions - multiple def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>; @@ -978,23 +983,28 @@ /// Load-linked, Store-conditional def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>; - - def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>; - def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>; - +} +let DecoderNamespace = "MicroMips" in { + def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>, + ISA_MICROMIPS, ASE_EVA; + def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>, + ISA_MICROMIPS, ASE_EVA; +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { let DecoderMethod = "DecodeCacheOpMM" in { def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>, CACHE_PREF_FM_MM<0x08, 0x6>; def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>, CACHE_PREF_FM_MM<0x18, 0x2>; } - - let DecoderMethod = "DecodePrefeOpMM" in { +} +let DecoderNamespace = "MicroMips", DecoderMethod = "DecodePrefeOpMM" in { def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>, - CACHE_PREFE_FM_MM<0x18, 0x2>; + CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA; def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>, - CACHE_PREFE_FM_MM<0x18, 0x3>; - } + CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA; +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>; def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>; def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>; Index: lib/Target/Mips/Mips.td =================================================================== --- lib/Target/Mips/Mips.td +++ lib/Target/Mips/Mips.td @@ -28,8 +28,10 @@ list PTRPredicates = []; // Predicates for the FGR size and layout such as IsFP64bit list FGRPredicates = []; - // Predicates for the instruction group membership such as ISA's and ASE's + // Predicates for the instruction group membership such as ISA's. list InsnPredicates = []; + // Predicate for the ASE that an instruction belongs to. + list ASEPredicate = []; // Predicate for marking the instruction as usable in hard-float mode only. list HardFloatPredicate = []; // Predicates for anything else @@ -40,6 +42,7 @@ FGRPredicates, InsnPredicates, HardFloatPredicate, + ASEPredicate, AdditionalPredicates); } Index: lib/Target/Mips/MipsEVAInstrInfo.td =================================================================== --- lib/Target/Mips/MipsEVAInstrInfo.td +++ lib/Target/Mips/MipsEVAInstrInfo.td @@ -95,6 +95,7 @@ string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list Pattern = []; string DecoderMethod = "DecodeMemEVA"; + string BaseOpcode = instr_asm; string Constraints = "$src = $rt"; bit canFoldAsLoad = 1; InstrItinClass Itinerary = itin; @@ -110,6 +111,7 @@ string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list Pattern = []; string DecoderMethod = "DecodeMemEVA"; + string BaseOpcode = instr_asm; InstrItinClass Itinerary = itin; } @@ -177,38 +179,32 @@ // //===----------------------------------------------------------------------===// -/// Load and Store EVA Instructions -def LBE : MMRel, LBE_ENC, LBE_DESC, INSN_EVA; -def LBuE : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA; -def LHE : MMRel, LHE_ENC, LHE_DESC, INSN_EVA; -def LHuE : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA; -let AdditionalPredicates = [NotInMicroMips] in { -def LWE : MMRel, LWE_ENC, LWE_DESC, INSN_EVA; -} -def SBE : MMRel, SBE_ENC, SBE_DESC, INSN_EVA; -def SHE : MMRel, SHE_ENC, SHE_DESC, INSN_EVA; -let AdditionalPredicates = [NotInMicroMips] in { -def SWE : MMRel, SWE_ENC, SWE_DESC, INSN_EVA; -} - -/// load/store left/right EVA let AdditionalPredicates = [NotInMicroMips] in { -def LWLE : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6; -def LWRE : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6; -def SWLE : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6; -def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6; + /// Load and Store EVA Instructions + def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA; + def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA; + def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA; + def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA; + def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA; + def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA; + def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA; + def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA; + + /// load/store left/right EVA + def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; + def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; + def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; + def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; + + /// Load-linked EVA, Store-conditional EVA + def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA; + def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA; + + /// TLB invalidate instructions + def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA; + def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA; + + /// EVA versions of cache and pref + def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA; + def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA; } - -/// Load-linked EVA, Store-conditional EVA -let AdditionalPredicates = [NotInMicroMips] in { -def LLE : MMRel, LLE_ENC, LLE_DESC, INSN_EVA; -def SCE : MMRel, SCE_ENC, SCE_DESC, INSN_EVA; -} - -let AdditionalPredicates = [NotInMicroMips] in { - def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; - def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; -} - -def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA; -def PREFE : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -235,7 +235,7 @@ def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; def HasEVA : Predicate<"Subtarget->hasEVA()">, - AssemblerPredicate<"FeatureEVA,FeatureMips32r2">; + AssemblerPredicate<"FeatureEVA">; def HasMSA : Predicate<"Subtarget->hasMSA()">, AssemblerPredicate<"FeatureMSA">; def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">, @@ -361,10 +361,7 @@ list InsnPredicates = [NotMips32r6]; list EncodingPredicates = [InMicroMips]; } -class INSN_EVA { list InsnPredicates = [HasEVA]; } -class INSN_EVA_NOT_32R6_64R6 { - list InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA]; -} +class ASE_EVA { list ASEPredicate = [HasEVA]; } // The portions of MIPS-III that were also added to MIPS32 class INSN_MIPS3_32 { Index: test/CodeGen/Mips/micromips-eva.mir =================================================================== --- test/CodeGen/Mips/micromips-eva.mir +++ test/CodeGen/Mips/micromips-eva.mir @@ -1,5 +1,5 @@ # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips -start-after=expand-isel-pseudos \ -# RUN: -filetype obj %s -o - | llvm-objdump -d - | FileCheck %s +# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s --- | Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips,eva \ # RUN: | FileCheck %s 0xf9 0x4f # CHECK: addiusp -16 Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips,eva \ # RUN: | FileCheck %s 0x4f 0xf9 # CHECK: addiusp -16 Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips,eva | FileCheck %s 0x6f 0x83 # CHECK: addiur1sp $7, 4 0x6f 0x7e # CHECK: addiur2 $6, $7, -1 Index: test/MC/Mips/micromips-control-instructions.s =================================================================== --- test/MC/Mips/micromips-control-instructions.s +++ test/MC/Mips/micromips-control-instructions.s @@ -39,15 +39,7 @@ # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] -# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4] -# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6] # CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09] -# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2] -# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0] -# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66] -# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64] -# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c] -# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -81,15 +73,7 @@ # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] -# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] -# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] # CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0] -# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05] -# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05] -# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05] -# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02] -# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08] -# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08] sdbbp sdbbp 34 @@ -118,12 +102,5 @@ tlbr tlbwi tlbwr - prefe 1, 8($5) - cachee 1, 8($5) prefx 1, $3($5) - swre $24, 5($3) - swle $24, 5($3) - lwre $24, 5($3) - lwle $24, 2($4) - lle $2, 8($4) - sce $2, 8($4) + Index: test/MC/Mips/micromips-eva.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips-eva.s @@ -0,0 +1,96 @@ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r2 \ +# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s +# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r2 \ +# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s +# Check that the assembler can handle the documented syntax +# for EVA instructions. +#------------------------------------------------------------------------------ +# microMIPS EVA Instructions +#------------------------------------------------------------------------------ +# Little endian +#------------------------------------------------------------------------------ +# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4] +# CHECK-EL-NEXT: # %t1 +# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips,eva 2>%t1 # RUN: FileCheck %s < %t1 addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 Index: test/MC/Mips/micromips/valid.s =================================================================== --- test/MC/Mips/micromips/valid.s +++ test/MC/Mips/micromips/valid.s @@ -199,23 +199,7 @@ addiupc $7, -16777216 # CHECK: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00] ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] -cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] -prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] prefx 1, $3($5) # CHECK: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0] -lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08] -lbe $4, 8($2) # CHECK: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08] -lbue $4, 8($2) # CHECK: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08] -lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] -lwe $4, 8($2) # CHECK: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08] -sbe $5, 8($4) # CHECK: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08] -she $5, 8($4) # CHECK: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08] -swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] -swre $24, 5($3) # CHECK: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05] -swle $24, 5($3) # CHECK: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05] -lwre $24, 5($3) # CHECK: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05] -lwle $24, 2($4) # CHECK: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02] -lle $2, 8($4) # CHECK: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08] -sce $2, 8($4) # CHECK: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08] syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c] syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] # FIXME: ldc1 should accept uneven registers Index: test/MC/Mips/micromips32r6/invalid-wrong-error.s =================================================================== --- test/MC/Mips/micromips32r6/invalid-wrong-error.s +++ test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -24,3 +24,4 @@ swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t1 # RUN: FileCheck %s < %t1 addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -68,9 +68,7 @@ lapc $7, 1048572 # CHECK: lapc $7, 1048572 # encoding: [0x78,0xe3,0xff,0xff] lapc $7, -1048576 # CHECK: lapc $7, -1048576 # encoding: [0x78,0xe4,0x00,0x00] lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] - lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] - lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] @@ -148,7 +146,6 @@ xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] - swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] # CHECK-NEXT: #