Index: test/CodeGen/X86/GlobalISel/x86_64-instruction-select-testgen-selected.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/GlobalISel/x86_64-instruction-select-testgen-selected.mir
@@ -0,0 +1,25611 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+#
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple x86_64-- -run-pass instruction-select \
+# RUN:     -testgen-set-all-features -disable-gisel-legality-check \
+# RUN:     -verify-machineinstrs -simplify-mir %s -o - 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=SELECTED
+#
+# Test if this file is in sync with the current state of the selector:
+# RUN: cat %s | FileCheck --check-prefix=TESTGEND \
+# RUN:     %S/x86_64-instruction-select-testgen-testgend.mir
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64--"
+
+  define void @test_return() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1_id142_at_idx177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule2_id143_at_idx227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule3_id144_at_idx277() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule4_id145_at_idx327() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule7_id18370_at_idx641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule8_id18371_at_idx746() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule9_id18382_at_idx851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule10_id18383_at_idx956() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule11_id16183_at_idx1061() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule12_id16184_at_idx1166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule13_id16195_at_idx1271() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule14_id16196_at_idx1376() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule15_id18378_at_idx1481() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule16_id18379_at_idx1586() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule17_id18380_at_idx1691() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule18_id18381_at_idx1796() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule19_id18366_at_idx1901() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule20_id18367_at_idx2006() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule21_id16191_at_idx2111() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule22_id16192_at_idx2216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule23_id16193_at_idx2321() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule24_id16194_at_idx2426() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule25_id16179_at_idx2531() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule26_id16180_at_idx2636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule27_id12362_at_idx2741() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule28_id12363_at_idx2775() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule29_id12364_at_idx2811() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule30_id12306_at_idx2847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule31_id92_at_idx2881() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule32_id1485_at_idx2955() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule33_id1487_at_idx3038() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule34_id1489_at_idx3121() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule35_id1491_at_idx3204() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule36_id2549_at_idx3287() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule37_id2551_at_idx3370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule38_id2553_at_idx3453() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule39_id2555_at_idx3536() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule40_id2557_at_idx3619() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule41_id2559_at_idx3702() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule42_id2561_at_idx3785() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule43_id2563_at_idx3868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule44_id2607_at_idx3951() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule45_id2609_at_idx4034() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule46_id2631_at_idx4117() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule47_id2677_at_idx4200() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule48_id2679_at_idx4283() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule49_id2681_at_idx4366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule50_id11490_at_idx4449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule51_id11492_at_idx4532() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule52_id11494_at_idx4615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule53_id90_at_idx4698() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule54_id2673_at_idx4769() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule55_id2675_at_idx4840() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule56_id102_at_idx4911() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule57_id104_at_idx4987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule58_id18350_at_idx5063() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule59_id18351_at_idx5140() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule60_id18364_at_idx5217() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule61_id18365_at_idx5294() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule62_id18354_at_idx5371() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule63_id18355_at_idx5448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule64_id14478_at_idx5525() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule65_id16153_at_idx5657() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule66_id16154_at_idx5734() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule67_id16177_at_idx5811() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule68_id16178_at_idx5888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule69_id16157_at_idx5965() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule70_id16158_at_idx6042() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule71_id18158_at_idx6119() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule72_id18374_at_idx6251() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule73_id18375_at_idx6328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule74_id18376_at_idx6405() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule75_id18377_at_idx6482() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule76_id18368_at_idx6559() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule77_id18369_at_idx6636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule78_id16187_at_idx6713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule79_id16188_at_idx6790() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule80_id16189_at_idx6867() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule81_id16190_at_idx6944() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule82_id16181_at_idx7021() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule83_id16182_at_idx7098() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule84_id18352_at_idx7175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule85_id18353_at_idx7252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule86_id18372_at_idx7329() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule87_id18373_at_idx7406() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule88_id18170_at_idx7483() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule89_id14486_at_idx7615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule90_id16155_at_idx7747() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule91_id16156_at_idx7824() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule92_id16185_at_idx7901() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule93_id16186_at_idx7978() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule94_id18171_at_idx8055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule95_id12302_at_idx8187() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule96_id12307_at_idx8239() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule97_id15615_at_idx8289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule98_id15616_at_idx8356() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule99_id12365_at_idx8423() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule100_id12366_at_idx8461() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule101_id1221_at_idx8499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule102_id1223_at_idx8571() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule103_id1225_at_idx8643() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule104_id1227_at_idx8715() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule105_id1229_at_idx8787() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule106_id1231_at_idx8859() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule107_id1233_at_idx8931() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule108_id1235_at_idx9003() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule109_id1237_at_idx9075() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule110_id1239_at_idx9147() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule111_id1241_at_idx9219() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule112_id1243_at_idx9291() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule113_id2583_at_idx9363() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule114_id2585_at_idx9435() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule115_id2587_at_idx9507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule116_id2589_at_idx9579() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule117_id2591_at_idx9651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule118_id2593_at_idx9723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule119_id82_at_idx9795() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule120_id84_at_idx9855() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule121_id86_at_idx9915() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule122_id88_at_idx9975() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule123_id1377_at_idx10035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule124_id1379_at_idx10095() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule125_id1381_at_idx10155() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule126_id1383_at_idx10215() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule127_id1385_at_idx10275() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule128_id1387_at_idx10335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule129_id1389_at_idx10395() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule130_id1391_at_idx10455() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule131_id1425_at_idx10515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule132_id1427_at_idx10575() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule133_id1431_at_idx10635() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule134_id1433_at_idx10695() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule135_id2339_at_idx10755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule136_id2341_at_idx10815() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule137_id2343_at_idx10875() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule138_id2345_at_idx10935() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule139_id2347_at_idx10995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule140_id2363_at_idx11055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule141_id2365_at_idx11115() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule142_id2367_at_idx11175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule143_id2369_at_idx11235() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule144_id2371_at_idx11295() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule145_id2381_at_idx11355() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule146_id2383_at_idx11415() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule147_id2385_at_idx11475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule148_id2389_at_idx11535() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule149_id2391_at_idx11595() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule150_id2624_at_idx11655() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule151_id2626_at_idx11715() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule152_id2628_at_idx11775() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule153_id2630_at_idx11835() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule154_id2633_at_idx11895() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule155_id2635_at_idx11955() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule156_id2637_at_idx12015() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule157_id2641_at_idx12075() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule158_id2643_at_idx12135() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule159_id2645_at_idx12195() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule160_id2647_at_idx12255() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule161_id2649_at_idx12315() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule162_id2651_at_idx12375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule163_id2653_at_idx12435() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule164_id2655_at_idx12495() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule165_id2657_at_idx12555() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule166_id2659_at_idx12615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule167_id2661_at_idx12675() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule168_id2663_at_idx12735() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule169_id2665_at_idx12795() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule170_id2667_at_idx12855() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule171_id2684_at_idx12915() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule172_id2686_at_idx12975() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule173_id11466_at_idx13035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule174_id11468_at_idx13095() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule175_id11470_at_idx13155() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule176_id11472_at_idx13215() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule177_id11474_at_idx13275() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule178_id11476_at_idx13335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule179_id11478_at_idx13395() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule180_id11480_at_idx13455() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule181_id11482_at_idx13515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule182_id11484_at_idx13575() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule183_id11486_at_idx13635() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule184_id11488_at_idx13695() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule185_id15146_at_idx13755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule186_id15148_at_idx13815() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule187_id15150_at_idx13875() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule188_id15152_at_idx13935() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule189_id15154_at_idx13995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule190_id15605_at_idx14055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule191_id15607_at_idx14108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule192_id15609_at_idx14161() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule193_id15611_at_idx14214() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule194_id15775_at_idx14267() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule195_id15776_at_idx14319() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule196_id15777_at_idx14371() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule197_id15778_at_idx14423() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule198_id15779_at_idx14475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule199_id15780_at_idx14527() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule200_id15781_at_idx14579() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule201_id15782_at_idx14631() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule202_id625_at_idx14683() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule203_id626_at_idx14733() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule204_id627_at_idx14783() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule205_id628_at_idx14833() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule206_id1135_at_idx14883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule207_id1137_at_idx14931() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule208_id1139_at_idx14979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule209_id1141_at_idx15027() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule210_id1143_at_idx15075() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule211_id1145_at_idx15123() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule212_id1147_at_idx15171() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule213_id1149_at_idx15219() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule214_id1151_at_idx15267() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule215_id1153_at_idx15315() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule216_id1155_at_idx15363() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule217_id1157_at_idx15411() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule218_id1159_at_idx15459() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule219_id1161_at_idx15507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule220_id1163_at_idx15555() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule221_id1165_at_idx15603() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule222_id1167_at_idx15651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule223_id1169_at_idx15699() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule224_id1171_at_idx15747() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule225_id1173_at_idx15795() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule226_id1175_at_idx15843() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule227_id1369_at_idx15891() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule228_id1371_at_idx15939() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule229_id1373_at_idx15987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule230_id1375_at_idx16035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule231_id1393_at_idx16083() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule232_id1395_at_idx16131() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule233_id1397_at_idx16179() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule234_id1399_at_idx16227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule235_id1401_at_idx16275() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule236_id1403_at_idx16323() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule237_id1405_at_idx16371() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule238_id1407_at_idx16419() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule239_id1409_at_idx16467() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule240_id1411_at_idx16515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule241_id1413_at_idx16563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule242_id1415_at_idx16611() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule243_id2669_at_idx16659() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule244_id2671_at_idx16707() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule245_id12550_at_idx16755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule246_id12552_at_idx16807() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule247_id12554_at_idx16859() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule248_id12556_at_idx16911() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule249_id13332_at_idx16963() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule250_id13356_at_idx17015() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule251_id13360_at_idx17067() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule252_id13364_at_idx17119() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule253_id13368_at_idx17171() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule254_id13372_at_idx17223() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule255_id15138_at_idx17275() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule256_id15140_at_idx17323() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule257_id15142_at_idx17371() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule258_id15144_at_idx17419() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule259_id15160_at_idx17467() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule260_id15162_at_idx17515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule261_id15164_at_idx17563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule262_id15166_at_idx17611() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule263_id12311_at_idx17659() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule264_id12312_at_idx17711() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule265_id601_at_idx17763() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule266_id602_at_idx17813() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule267_id603_at_idx17863() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule268_id604_at_idx17913() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule269_id15656_at_idx17963() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule270_id15657_at_idx18017() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule271_id15658_at_idx18071() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule272_id15659_at_idx18125() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule273_id1_at_idx18179() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule274_id2_at_idx18219() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule275_id95_at_idx18259() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule276_id97_at_idx18299() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule277_id12299_at_idx18339() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule278_id12335_at_idx18379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule279_id12336_at_idx18417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule280_id12337_at_idx18457() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule281_id12338_at_idx18497() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule282_id12339_at_idx18537() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule283_id12344_at_idx18577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule284_id3_at_idx18617() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule285_id4_at_idx18657() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule286_id94_at_idx18697() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule287_id96_at_idx18737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule288_id12309_at_idx18777() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule289_id12310_at_idx18817() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule290_id12334_at_idx18857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule291_id12340_at_idx18895() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule292_id12341_at_idx18935() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule293_id12342_at_idx18975() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule294_id12343_at_idx19015() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule295_id1819_at_idx19055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule296_id1820_at_idx19081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule297_id1821_at_idx19109() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule298_id1822_at_idx19137() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule299_id2719_at_idx19165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule300_id2720_at_idx19193() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule301_id12066_at_idx19221() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule302_id12285_at_idx19249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule303_id12300_at_idx19277() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule304_id12313_at_idx19305() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule305_id12319_at_idx19333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule306_id15730_at_idx19361() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule307_id15731_at_idx19429() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule308_id15762_at_idx19497() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule309_id15763_at_idx19565() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule310_id15824_at_idx19633() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule311_id15825_at_idx19701() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule312_id15826_at_idx19769() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule313_id15827_at_idx19837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule314_id15755_at_idx19905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule315_id15756_at_idx19973() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule316_id15771_at_idx20041() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule317_id15772_at_idx20109() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule318_id15794_at_idx20177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule319_id15795_at_idx20245() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule320_id15796_at_idx20313() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule321_id15797_at_idx20381() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule322_id15741_at_idx20449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule323_id15742_at_idx20517() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule324_id15767_at_idx20585() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule325_id15768_at_idx20653() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule326_id15809_at_idx20721() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule327_id15810_at_idx20789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule328_id15811_at_idx20857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule329_id15812_at_idx20925() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule330_id13375_at_idx20993() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule331_id13376_at_idx21081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule332_id18122_at_idx21169() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule333_id18123_at_idx21257() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule334_id15727_at_idx21345() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule335_id15728_at_idx21410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule336_id15729_at_idx21475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule337_id15821_at_idx21540() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule338_id15822_at_idx21605() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule339_id15823_at_idx21670() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule340_id621_at_idx21735() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule341_id622_at_idx21800() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule342_id623_at_idx21865() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule343_id624_at_idx21930() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule344_id597_at_idx21995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule345_id598_at_idx22060() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule346_id599_at_idx22125() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule347_id600_at_idx22190() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule348_id15753_at_idx22255() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule349_id15754_at_idx22320() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule350_id15791_at_idx22385() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule351_id15792_at_idx22450() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule352_id15793_at_idx22515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule353_id577_at_idx22580() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule354_id578_at_idx22645() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule355_id579_at_idx22710() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule356_id580_at_idx22775() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule357_id15738_at_idx22840() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule358_id15739_at_idx22905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule359_id15740_at_idx22970() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule360_id15806_at_idx23035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule361_id15807_at_idx23100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule362_id15808_at_idx23165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule363_id14434_at_idx23230() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule364_id14436_at_idx23294() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule365_id14433_at_idx23358() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule366_id14435_at_idx23420() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule367_id16197_at_idx23484() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule368_id16198_at_idx23568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule369_id18384_at_idx23652() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule370_id18385_at_idx23736() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule371_id22_at_idx23820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule372_id869_at_idx23856() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule373_id870_at_idx23891() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule374_id871_at_idx23926() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule375_id872_at_idx23961() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule376_id873_at_idx23996() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule377_id874_at_idx24029() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule380_id1831_at_idx24132() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule381_id1833_at_idx24175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule382_id1835_at_idx24218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule383_id1837_at_idx24261() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule384_id1839_at_idx24304() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule385_id1841_at_idx24347() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule386_id1843_at_idx24390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule387_id1845_at_idx24433() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule388_id1847_at_idx24476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule389_id1849_at_idx24519() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule390_id1851_at_idx24562() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule391_id1853_at_idx24605() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule392_id3957_at_idx24648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule393_id3966_at_idx24691() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule394_id3975_at_idx24734() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule395_id3984_at_idx24777() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule396_id3993_at_idx24820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule397_id4002_at_idx24863() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule398_id4011_at_idx24906() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule399_id4017_at_idx24949() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule400_id4023_at_idx24992() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule401_id4029_at_idx25035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule402_id4035_at_idx25078() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule403_id4041_at_idx25121() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule404_id15721_at_idx25164() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule405_id15722_at_idx25208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule406_id15723_at_idx25252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule407_id15761_at_idx25296() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule408_id1571_at_idx25340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule409_id1573_at_idx25383() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule410_id1575_at_idx25426() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule411_id3743_at_idx25469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule412_id3744_at_idx25512() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule413_id3745_at_idx25555() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule414_id3746_at_idx25598() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule415_id5010_at_idx25641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule416_id5019_at_idx25684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule417_id5028_at_idx25727() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule418_id13527_at_idx25770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule419_id14153_at_idx25813() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule420_id14473_at_idx25917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule421_id14474_at_idx26023() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule422_id14475_at_idx26127() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule423_id14476_at_idx26231() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule424_id15813_at_idx26335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule425_id15814_at_idx26379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule426_id15815_at_idx26423() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule427_id15816_at_idx26467() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule428_id2781_at_idx26511() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule429_id2783_at_idx26554() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule430_id6566_at_idx26597() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule431_id6575_at_idx26640() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule432_id6584_at_idx26683() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule433_id6593_at_idx26726() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule434_id6602_at_idx26769() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule435_id6611_at_idx26812() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule436_id6620_at_idx26855() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule437_id6626_at_idx26898() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule438_id6632_at_idx26941() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule439_id722_at_idx26984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule440_id723_at_idx27030() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule441_id724_at_idx27076() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule442_id1595_at_idx27120() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule443_id1597_at_idx27163() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule444_id1599_at_idx27206() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule445_id1601_at_idx27249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule446_id1603_at_idx27292() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule447_id1605_at_idx27335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule454_id5342_at_idx27636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule455_id5351_at_idx27679() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule456_id5360_at_idx27722() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule457_id5369_at_idx27765() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule458_id5378_at_idx27808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule459_id5387_at_idx27851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule460_id731_at_idx27894() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule461_id732_at_idx27940() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule462_id733_at_idx27986() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule463_id1655_at_idx28030() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule464_id1657_at_idx28073() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule465_id1659_at_idx28116() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule466_id1661_at_idx28159() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule467_id1663_at_idx28202() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule468_id1665_at_idx28245() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule475_id5522_at_idx28546() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule476_id5531_at_idx28589() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule477_id5540_at_idx28632() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule478_id5549_at_idx28675() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule479_id5558_at_idx28718() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule480_id5567_at_idx28761() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule481_id728_at_idx28804() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule482_id729_at_idx28850() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule483_id730_at_idx28896() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule484_id1615_at_idx28940() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule485_id1617_at_idx28983() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule486_id1619_at_idx29026() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule487_id1621_at_idx29069() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule488_id1623_at_idx29112() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule489_id1625_at_idx29155() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule496_id5402_at_idx29456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule497_id5411_at_idx29499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule498_id5420_at_idx29542() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule499_id5429_at_idx29585() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule500_id5438_at_idx29628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule501_id5447_at_idx29671() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule502_id725_at_idx29714() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule503_id726_at_idx29760() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule504_id727_at_idx29806() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule505_id1635_at_idx29850() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule506_id1637_at_idx29893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule507_id1639_at_idx29936() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule508_id1641_at_idx29979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule509_id1643_at_idx30022() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule510_id1645_at_idx30065() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule517_id5462_at_idx30366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule518_id5471_at_idx30409() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule519_id5480_at_idx30452() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule520_id5489_at_idx30495() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule521_id5498_at_idx30538() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule522_id5507_at_idx30581() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule523_id2773_at_idx30624() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule524_id2775_at_idx30667() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule525_id2777_at_idx30710() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule526_id2779_at_idx30753() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule527_id6638_at_idx30796() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule528_id6647_at_idx30839() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule529_id6656_at_idx30882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule530_id6665_at_idx30925() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule531_id6674_at_idx30968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule532_id6683_at_idx31011() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule533_id6692_at_idx31054() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule534_id6698_at_idx31097() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule535_id6704_at_idx31140() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule536_id1879_at_idx31183() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule537_id1881_at_idx31226() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule538_id1883_at_idx31269() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule539_id2537_at_idx31312() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule540_id2541_at_idx31355() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule541_id2545_at_idx31398() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule542_id4281_at_idx31441() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule543_id4290_at_idx31484() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule544_id4299_at_idx31527() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule545_id4308_at_idx31570() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule546_id4314_at_idx31613() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule547_id4320_at_idx31656() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule548_id4326_at_idx31699() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule549_id4335_at_idx31742() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule550_id4344_at_idx31785() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule551_id15749_at_idx31828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule552_id15750_at_idx31872() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule553_id15769_at_idx31916() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule554_id1577_at_idx31960() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule555_id1579_at_idx32003() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule556_id1581_at_idx32046() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule557_id3747_at_idx32089() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule558_id3748_at_idx32132() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule559_id3749_at_idx32175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule560_id3750_at_idx32218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule561_id5058_at_idx32261() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule562_id5067_at_idx32304() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule563_id5076_at_idx32347() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule564_id13528_at_idx32390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule565_id14156_at_idx32433() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule566_id14481_at_idx32537() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule567_id14482_at_idx32643() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule568_id14483_at_idx32747() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule569_id14484_at_idx32851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule570_id15783_at_idx32955() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule571_id15784_at_idx32999() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule572_id15785_at_idx33043() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule573_id15786_at_idx33087() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule574_id2765_at_idx33131() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule575_id2767_at_idx33174() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule576_id2769_at_idx33217() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule577_id2771_at_idx33260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule578_id6494_at_idx33303() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule579_id6503_at_idx33346() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule580_id6512_at_idx33389() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule581_id6521_at_idx33432() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule582_id6530_at_idx33475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule583_id6539_at_idx33518() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule584_id6548_at_idx33561() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule585_id6554_at_idx33604() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule586_id6560_at_idx33647() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule587_id1897_at_idx33690() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule588_id1899_at_idx33733() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule589_id1901_at_idx33776() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule590_id1903_at_idx33819() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule591_id1905_at_idx33862() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule592_id1907_at_idx33905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule593_id1909_at_idx33948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule594_id1911_at_idx33991() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule595_id1913_at_idx34034() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule596_id1915_at_idx34077() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule597_id1917_at_idx34120() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule598_id1919_at_idx34163() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule599_id4047_at_idx34206() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule600_id4056_at_idx34249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule601_id4065_at_idx34292() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule602_id4074_at_idx34335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule603_id4083_at_idx34378() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule604_id4092_at_idx34421() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule605_id4101_at_idx34464() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule606_id4107_at_idx34507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule607_id4113_at_idx34550() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule608_id4119_at_idx34593() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule609_id4125_at_idx34636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule610_id4131_at_idx34679() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule611_id15732_at_idx34722() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule612_id15733_at_idx34766() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule613_id15734_at_idx34810() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule614_id15765_at_idx34854() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule615_id1583_at_idx34898() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule616_id1585_at_idx34941() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule617_id1587_at_idx34984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule618_id3755_at_idx35027() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule619_id3756_at_idx35070() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule620_id3757_at_idx35113() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule621_id3758_at_idx35156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule622_id5106_at_idx35199() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule623_id5115_at_idx35242() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule624_id5124_at_idx35285() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule625_id13529_at_idx35328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule626_id14159_at_idx35371() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule627_id14489_at_idx35475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule628_id14490_at_idx35581() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule629_id14491_at_idx35685() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule630_id14492_at_idx35789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule631_id15798_at_idx35893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule632_id15799_at_idx35937() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule633_id15800_at_idx35981() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule634_id15801_at_idx36025() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule635_id15599_at_idx36069() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule636_id2219_at_idx36102() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule637_id2223_at_idx36137() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule638_id2224_at_idx36172() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule639_id2226_at_idx36207() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule640_id2235_at_idx36242() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule641_id2238_at_idx36277() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule642_id2240_at_idx36312() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule643_id2242_at_idx36347() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule644_id3924_at_idx36382() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule645_id3926_at_idx36417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule646_id3928_at_idx36452() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule647_id3934_at_idx36487() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule648_id14437_at_idx36522() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule649_id14438_at_idx36557() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule650_id14439_at_idx36592() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule651_id14440_at_idx36627() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule652_id15843_at_idx36662() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule653_id15844_at_idx36706() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule654_id15845_at_idx36750() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule655_id15846_at_idx36794() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule657_id15848_at_idx36882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule658_id15849_at_idx36926() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule659_id15850_at_idx36970() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule661_id15852_at_idx37058() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule662_id15853_at_idx37102() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule663_id15854_at_idx37146() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule664_id15855_at_idx37190() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule667_id15858_at_idx37322() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule668_id15859_at_idx37366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule669_id15860_at_idx37410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule682_id15873_at_idx37982() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule684_id15875_at_idx38070() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule685_id15876_at_idx38114() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule686_id15877_at_idx38158() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule688_id15879_at_idx38246() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule689_id15880_at_idx38290() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule690_id15881_at_idx38334() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule691_id15882_at_idx38378() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule693_id15884_at_idx38466() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule694_id15885_at_idx38510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule695_id15886_at_idx38554() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule696_id15887_at_idx38598() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule699_id15890_at_idx38730() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule700_id15891_at_idx38774() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule701_id15892_at_idx38818() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule714_id15905_at_idx39390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule715_id15906_at_idx39434() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule716_id15907_at_idx39478() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule717_id15908_at_idx39522() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule719_id15910_at_idx39610() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule720_id15911_at_idx39654() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule721_id15912_at_idx39698() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule722_id15913_at_idx39742() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule734_id15925_at_idx40270() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule735_id15926_at_idx40314() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule736_id15927_at_idx40358() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule740_id15931_at_idx40534() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule741_id15932_at_idx40578() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule742_id15933_at_idx40622() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule745_id5_at_idx40754() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule746_id6_at_idx40787() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule747_id15834_at_idx40820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule748_id19_at_idx40867() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule749_id20_at_idx40900() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule750_id800_at_idx40933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule751_id801_at_idx40971() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule752_id802_at_idx41009() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule753_id1429_at_idx41045() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule754_id1461_at_idx41080() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule755_id8438_at_idx41115() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule756_id8459_at_idx41150() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule757_id13475_at_idx41185() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule758_id15168_at_idx41245() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule759_id16241_at_idx41305() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule760_id16242_at_idx41342() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule761_id16243_at_idx41379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule762_id1345_at_idx41416() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule763_id1347_at_idx41451() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule764_id1349_at_idx41486() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule765_id1351_at_idx41521() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule766_id1353_at_idx41556() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule767_id1355_at_idx41591() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule768_id1357_at_idx41626() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule769_id1359_at_idx41661() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule770_id1447_at_idx41696() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule771_id1449_at_idx41731() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule772_id1451_at_idx41766() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule773_id1455_at_idx41801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule774_id8350_at_idx41836() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule775_id8355_at_idx41871() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule776_id8360_at_idx41906() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule777_id8365_at_idx41941() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule778_id8525_at_idx41976() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule779_id8537_at_idx42011() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule780_id8546_at_idx42046() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule781_id8555_at_idx42081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule782_id8576_at_idx42116() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule783_id8942_at_idx42151() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule784_id8954_at_idx42186() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule785_id8963_at_idx42221() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule786_id8972_at_idx42256() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule787_id8993_at_idx42291() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule788_id8370_at_idx42326() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule789_id8375_at_idx42361() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule790_id8380_at_idx42396() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule791_id8385_at_idx42431() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule792_id8585_at_idx42466() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule793_id8597_at_idx42501() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule794_id8606_at_idx42536() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule795_id8615_at_idx42571() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule796_id8636_at_idx42606() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule797_id9002_at_idx42641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule798_id9014_at_idx42676() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule799_id9023_at_idx42711() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule800_id9032_at_idx42746() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule801_id9053_at_idx42781() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule802_id1423_at_idx42816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule803_id1473_at_idx42851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule804_id8408_at_idx42886() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule805_id8429_at_idx42921() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule806_id13474_at_idx42956() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule807_id15172_at_idx43016() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule808_id16244_at_idx43076() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule809_id16245_at_idx43113() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule810_id16246_at_idx43150() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule811_id526_at_idx43187() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule812_id528_at_idx43220() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule813_id534_at_idx43253() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule814_id536_at_idx43286() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule815_id538_at_idx43319() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule816_id10064_at_idx43354() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule817_id10065_at_idx43389() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule818_id10066_at_idx43424() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule819_id10067_at_idx43459() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule820_id10068_at_idx43494() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule821_id10069_at_idx43529() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule822_id10070_at_idx43564() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule823_id10071_at_idx43599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule824_id10072_at_idx43634() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule825_id10073_at_idx43669() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule826_id10074_at_idx43704() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule827_id10075_at_idx43739() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule828_id15336_at_idx43774() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule829_id15337_at_idx43834() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule830_id1361_at_idx43894() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule831_id1363_at_idx43929() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule832_id1365_at_idx43964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule833_id1367_at_idx43999() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule834_id1417_at_idx44034() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule835_id1419_at_idx44069() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule836_id1421_at_idx44104() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule837_id1468_at_idx44139() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule838_id8468_at_idx44174() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule839_id8486_at_idx44209() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule840_id8495_at_idx44244() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule841_id8507_at_idx44279() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule842_id8516_at_idx44314() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule843_id9062_at_idx44349() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule844_id9074_at_idx44384() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule845_id9083_at_idx44419() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule846_id9122_at_idx44454() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule847_id9143_at_idx44489() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule848_id13470_at_idx44524() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule849_id13471_at_idx44584() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule850_id13472_at_idx44644() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule851_id13473_at_idx44704() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule852_id15126_at_idx44764() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule853_id15127_at_idx44824() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule854_id15128_at_idx44884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule855_id15129_at_idx44944() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule856_id9671_at_idx45004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule857_id9695_at_idx45039() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule858_id9698_at_idx45074() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule859_id9725_at_idx45109() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule860_id9749_at_idx45144() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule861_id9752_at_idx45179() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule862_id9776_at_idx45214() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule863_id9779_at_idx45249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule864_id15634_at_idx45284() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule865_id15640_at_idx45333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule866_id15641_at_idx45384() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule867_id8645_at_idx45435() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule868_id8663_at_idx45470() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule869_id8672_at_idx45505() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule870_id8684_at_idx45540() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule871_id8693_at_idx45575() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule872_id9092_at_idx45610() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule873_id9104_at_idx45645() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule874_id9113_at_idx45680() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule875_id9152_at_idx45715() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule876_id9173_at_idx45750() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule877_id15134_at_idx45785() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule878_id15135_at_idx45845() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule879_id15136_at_idx45905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule880_id15137_at_idx45965() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule881_id530_at_idx46025() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule882_id532_at_idx46058() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule883_id542_at_idx46091() {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            test_return
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_return
+    ; SELECTED: $noreg = PATCHABLE_RET
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1_id142_at_idx177
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule1_id142_at_idx177
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[NOT8r:%[0-9]+]]:gr8 = NOT8r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[NOT8r]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT -1
+    %0:gpr(s8) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule2_id143_at_idx227
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule2_id143_at_idx227
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[NOT16r:%[0-9]+]]:gr16 = NOT16r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[NOT16r]]
+    %1:gpr(s16) = COPY $ax
+    %2:gpr(s16) = G_CONSTANT -1
+    %0:gpr(s16) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule3_id144_at_idx277
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule3_id144_at_idx277
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[NOT32r:%[0-9]+]]:gr32 = NOT32r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[NOT32r]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule4_id145_at_idx327
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule4_id145_at_idx327
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[NOT64r:%[0-9]+]]:gr64 = NOT64r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[NOT64r]]
+    %1:gpr(s64) = COPY $rax
+    %2:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule7_id18370_at_idx641
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule7_id18370_at_idx641
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCIC32rr:%[0-9]+]]:gr32 = BLCIC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCIC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_XOR %5, %6
+    %0:gpr(s32) = G_ADD %5, %4
+    %2:gpr(s32) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule8_id18371_at_idx746
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule8_id18371_at_idx746
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCIC64rr:%[0-9]+]]:gr64 = BLCIC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCIC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_XOR %5, %6
+    %0:gpr(s64) = G_ADD %5, %4
+    %2:gpr(s64) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule9_id18382_at_idx851
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule9_id18382_at_idx851
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[TZMSK32rr:%[0-9]+]]:gr32 = TZMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[TZMSK32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_XOR %5, %6
+    %0:gpr(s32) = G_ADD %5, %4
+    %2:gpr(s32) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule10_id18383_at_idx956
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule10_id18383_at_idx956
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[TZMSK64rr:%[0-9]+]]:gr64 = TZMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[TZMSK64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_XOR %5, %6
+    %0:gpr(s64) = G_ADD %5, %4
+    %2:gpr(s64) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule11_id16183_at_idx1061
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule11_id16183_at_idx1061
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCIC32rr:%[0-9]+]]:gr32 = BLCIC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCIC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT 1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_ADD %5, %6
+    %0:gpr(s32) = G_XOR %5, %4
+    %2:gpr(s32) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule12_id16184_at_idx1166
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule12_id16184_at_idx1166
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCIC64rr:%[0-9]+]]:gr64 = BLCIC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCIC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT 1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_ADD %5, %6
+    %0:gpr(s64) = G_XOR %5, %4
+    %2:gpr(s64) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule13_id16195_at_idx1271
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule13_id16195_at_idx1271
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[TZMSK32rr:%[0-9]+]]:gr32 = TZMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[TZMSK32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_ADD %5, %6
+    %0:gpr(s32) = G_XOR %5, %4
+    %2:gpr(s32) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule14_id16196_at_idx1376
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule14_id16196_at_idx1376
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[TZMSK64rr:%[0-9]+]]:gr64 = TZMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[TZMSK64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_ADD %5, %6
+    %0:gpr(s64) = G_XOR %5, %4
+    %2:gpr(s64) = G_AND %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule15_id18378_at_idx1481
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule15_id18378_at_idx1481
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSIC32rr:%[0-9]+]]:gr32 = BLSIC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSIC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_XOR %5, %6
+    %0:gpr(s32) = G_ADD %5, %4
+    %2:gpr(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule16_id18379_at_idx1586
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule16_id18379_at_idx1586
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSIC64rr:%[0-9]+]]:gr64 = BLSIC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSIC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_XOR %5, %6
+    %0:gpr(s64) = G_ADD %5, %4
+    %2:gpr(s64) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule17_id18380_at_idx1691
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule17_id18380_at_idx1691
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[T1MSKC32rr:%[0-9]+]]:gr32 = T1MSKC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[T1MSKC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_XOR %5, %6
+    %0:gpr(s32) = G_ADD %5, %4
+    %2:gpr(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule18_id18381_at_idx1796
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule18_id18381_at_idx1796
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[T1MSKC64rr:%[0-9]+]]:gr64 = T1MSKC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[T1MSKC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_XOR %5, %6
+    %0:gpr(s64) = G_ADD %5, %4
+    %2:gpr(s64) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule19_id18366_at_idx1901
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule19_id18366_at_idx1901
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCI32rr:%[0-9]+]]:gr32 = BLCI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %6:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %3, %6
+    %0:gpr(s32) = G_XOR %1, %4
+    %2:gpr(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule20_id18367_at_idx2006
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule20_id18367_at_idx2006
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCI64rr:%[0-9]+]]:gr64 = BLCI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %6:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ADD %3, %6
+    %0:gpr(s64) = G_XOR %1, %4
+    %2:gpr(s64) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule21_id16191_at_idx2111
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule21_id16191_at_idx2111
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSIC32rr:%[0-9]+]]:gr32 = BLSIC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSIC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT -1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_ADD %5, %6
+    %0:gpr(s32) = G_XOR %5, %4
+    %2:gpr(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule22_id16192_at_idx2216
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule22_id16192_at_idx2216
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSIC64rr:%[0-9]+]]:gr64 = BLSIC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSIC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT -1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_ADD %5, %6
+    %0:gpr(s64) = G_XOR %5, %4
+    %2:gpr(s64) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule23_id16193_at_idx2321
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule23_id16193_at_idx2321
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[T1MSKC32rr:%[0-9]+]]:gr32 = T1MSKC32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[T1MSKC32rr]]
+    %5:gpr(s32) = COPY $eax
+    %6:gpr(s32) = G_CONSTANT 1
+    %4:gpr(s32) = G_CONSTANT -1
+    %1:gpr(s32) = G_ADD %5, %6
+    %0:gpr(s32) = G_XOR %5, %4
+    %2:gpr(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule24_id16194_at_idx2426
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule24_id16194_at_idx2426
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[T1MSKC64rr:%[0-9]+]]:gr64 = T1MSKC64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[T1MSKC64rr]]
+    %5:gpr(s64) = COPY $rax
+    %6:gpr(s64) = G_CONSTANT 1
+    %4:gpr(s64) = G_CONSTANT -1
+    %1:gpr(s64) = G_ADD %5, %6
+    %0:gpr(s64) = G_XOR %5, %4
+    %2:gpr(s64) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule25_id16179_at_idx2531
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule25_id16179_at_idx2531
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCI32rr:%[0-9]+]]:gr32 = BLCI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI32rr]]
+    %5:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %6:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %5, %6
+    %0:gpr(s32) = G_XOR %1, %4
+    %2:gpr(s32) = G_OR %5, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule26_id16180_at_idx2636
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule26_id16180_at_idx2636
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCI64rr:%[0-9]+]]:gr64 = BLCI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI64rr]]
+    %5:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %6:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ADD %5, %6
+    %0:gpr(s64) = G_XOR %1, %4
+    %2:gpr(s64) = G_OR %5, %0
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule27_id12362_at_idx2741
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule27_id12362_at_idx2741
+    ; SELECTED: [[MOV32ImmSExti8_:%[0-9]+]]:gr32 = MOV32ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV32ImmSExti8_]]
+    %0:gpr(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule28_id12363_at_idx2775
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule28_id12363_at_idx2775
+    ; SELECTED: [[MOV32ImmSExti8_:%[0-9]+]]:gr32 = MOV32ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV32ImmSExti8_]]
+    %0:gpr(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule29_id12364_at_idx2811
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule29_id12364_at_idx2811
+    ; SELECTED: [[MOV32ImmSExti8_:%[0-9]+]]:gr32 = MOV32ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV32ImmSExti8_]]
+    %0:gpr(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule30_id12306_at_idx2847
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule30_id12306_at_idx2847
+    ; SELECTED: INT3
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s8) = G_CONSTANT 3
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.int), %0(s8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule31_id92_at_idx2881
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule31_id92_at_idx2881
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BEXTRI64ri:%[0-9]+]]:gr64 = BEXTRI64ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BEXTRI64ri]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.tbm.bextri.u64), %2(s64), %0(s64)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule32_id1485_at_idx2955
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule32_id1485_at_idx2955
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCMPSSrr_Int:%[0-9]+]]:vr128 = VCMPSSrr_Int [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCMPSSrr_Int]]
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cmp.ss), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule33_id1487_at_idx3038
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule33_id1487_at_idx3038
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCMPSDrr_Int:%[0-9]+]]:vr128 = VCMPSDrr_Int [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCMPSDrr_Int]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cmp.sd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule34_id1489_at_idx3121
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule34_id1489_at_idx3121
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCMPSSrr_Int:%[0-9]+]]:vr128 = VCMPSSrr_Int [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCMPSSrr_Int]]
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cmp.ss), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule35_id1491_at_idx3204
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule35_id1491_at_idx3204
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCMPSDrr_Int:%[0-9]+]]:vr128 = VCMPSDrr_Int [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCMPSDrr_Int]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cmp.sd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule36_id2549_at_idx3287
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule36_id2549_at_idx3287
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMPSADBWrri:%[0-9]+]]:vr128 = VMPSADBWrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMPSADBWrri]]
+    %3:vecr(<16 x s8>) = COPY $xmm1
+    %2:vecr(<16 x s8>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.mpsadbw), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule37_id2551_at_idx3370
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule37_id2551_at_idx3370
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDPPSrri:%[0-9]+]]:vr128 = VDPPSrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDPPSrri]]
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dpps), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule38_id2553_at_idx3453
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule38_id2553_at_idx3453
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDPPDrri:%[0-9]+]]:vr128 = VDPPDrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDPPDrri]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dppd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule39_id2555_at_idx3536
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%2' }
+  - { reg: '$ymm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule39_id2555_at_idx3536
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VDPPSYrri:%[0-9]+]]:vr256 = VDPPSYrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDPPSYrri]]
+    %3:vecr(<8 x s32>) = COPY $ymm1
+    %2:vecr(<8 x s32>) = COPY $ymm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx.dp.ps.256), %2(<8 x s32>), %3(<8 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<8 x s32>)
+
+...
+---
+name:            test_rule40_id2557_at_idx3619
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%2' }
+  - { reg: '$ymm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule40_id2557_at_idx3619
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VMPSADBWYrri:%[0-9]+]]:vr256 = VMPSADBWYrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMPSADBWYrri]]
+    %3:vecr(<32 x s8>) = COPY $ymm1
+    %2:vecr(<32 x s8>) = COPY $ymm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.mpsadbw), %2(<32 x s8>), %3(<32 x s8>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<16 x s16>)
+
+...
+---
+name:            test_rule41_id2559_at_idx3702
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule41_id2559_at_idx3702
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMPSADBWrri:%[0-9]+]]:vr128 = VMPSADBWrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMPSADBWrri]]
+    %3:vecr(<16 x s8>) = COPY $xmm1
+    %2:vecr(<16 x s8>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.mpsadbw), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule42_id2561_at_idx3785
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule42_id2561_at_idx3785
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDPPSrri:%[0-9]+]]:vr128 = VDPPSrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDPPSrri]]
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dpps), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule43_id2563_at_idx3868
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule43_id2563_at_idx3868
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDPPDrri:%[0-9]+]]:vr128 = VDPPDrri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDPPDrri]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dppd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule44_id2607_at_idx3951
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule44_id2607_at_idx3951
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPCMPISTRM128REG:%[0-9]+]]:vr128 = VPCMPISTRM128REG [[COPY1]], [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPCMPISTRM128REG]]
+    %3:vecr(<16 x s8>) = COPY $xmm1
+    %2:vecr(<16 x s8>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse42.pcmpistrm128), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule45_id2609_at_idx4034
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule45_id2609_at_idx4034
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPCMPISTRM128REG:%[0-9]+]]:vr128 = VPCMPISTRM128REG [[COPY1]], [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPCMPISTRM128REG]]
+    %3:vecr(<16 x s8>) = COPY $xmm1
+    %2:vecr(<16 x s8>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse42.pcmpistrm128), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule46_id2631_at_idx4117
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule46_id2631_at_idx4117
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA1RNDS4rri:%[0-9]+]]:vr128 = SHA1RNDS4rri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1RNDS4rri]]
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1rnds4), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule47_id2677_at_idx4200
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule47_id2677_at_idx4200
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[PCLMULQDQrr:%[0-9]+]]:vr128 = PCLMULQDQrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[PCLMULQDQrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule48_id2679_at_idx4283
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule48_id2679_at_idx4283
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[PCLMULQDQrr:%[0-9]+]]:vr128 = PCLMULQDQrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[PCLMULQDQrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule49_id2681_at_idx4366
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%2' }
+  - { reg: '$ymm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule49_id2681_at_idx4366
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPCLMULQDQYrr:%[0-9]+]]:vr256 = VPCLMULQDQYrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPCLMULQDQYrr]]
+    %3:vecr(<4 x s64>) = COPY $ymm1
+    %2:vecr(<4 x s64>) = COPY $ymm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.256), %2(<4 x s64>), %3(<4 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s64>)
+
+...
+---
+name:            test_rule50_id11490_at_idx4449
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%2' }
+  - { reg: '$zmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule50_id11490_at_idx4449
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPCLMULQDQZrr:%[0-9]+]]:vr512 = VPCLMULQDQZrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPCLMULQDQZrr]]
+    %3:vecr(<8 x s64>) = COPY $zmm1
+    %2:vecr(<8 x s64>) = COPY $zmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.512), %2(<8 x s64>), %3(<8 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<8 x s64>)
+
+...
+---
+name:            test_rule51_id11492_at_idx4532
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule51_id11492_at_idx4532
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[PCLMULQDQrr:%[0-9]+]]:vr128 = PCLMULQDQrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[PCLMULQDQrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm1
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule52_id11494_at_idx4615
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%2' }
+  - { reg: '$ymm1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule52_id11494_at_idx4615
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPCLMULQDQYrr:%[0-9]+]]:vr256 = VPCLMULQDQYrr [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPCLMULQDQYrr]]
+    %3:vecr(<4 x s64>) = COPY $ymm1
+    %2:vecr(<4 x s64>) = COPY $ymm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.256), %2(<4 x s64>), %3(<4 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<4 x s64>)
+
+...
+---
+name:            test_rule53_id90_at_idx4698
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule53_id90_at_idx4698
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BEXTRI32ri:%[0-9]+]]:gr32 = BEXTRI32ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BEXTRI32ri]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.tbm.bextri.u32), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule54_id2673_at_idx4769
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule54_id2673_at_idx4769
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESKEYGENASSIST128rr:%[0-9]+]]:vr128 = VAESKEYGENASSIST128rr [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESKEYGENASSIST128rr]]
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aeskeygenassist), %2(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule55_id2675_at_idx4840
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule55_id2675_at_idx4840
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESKEYGENASSIST128rr:%[0-9]+]]:vr128 = VAESKEYGENASSIST128rr [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESKEYGENASSIST128rr]]
+    %2:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aeskeygenassist), %2(<2 x s64>), %0(s8)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule56_id102_at_idx4911
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule56_id102_at_idx4911
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: LWPVAL32rri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.lwpval32), %1(s32), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule57_id104_at_idx4987
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $eax
+
+    ; SELECTED-LABEL: name: test_rule57_id104_at_idx4987
+    ; SELECTED: liveins: $rax, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: LWPVAL64rri [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %2:gpr(s32) = COPY $eax
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.lwpval64), %1(s64), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule58_id18350_at_idx5063
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule58_id18350_at_idx5063
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSR32rr:%[0-9]+]]:gr32 = BLSR32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSR32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule59_id18351_at_idx5140
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule59_id18351_at_idx5140
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSR64rr:%[0-9]+]]:gr64 = BLSR64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSR64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule60_id18364_at_idx5217
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule60_id18364_at_idx5217
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCFILL32rr:%[0-9]+]]:gr32 = BLCFILL32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCFILL32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule61_id18365_at_idx5294
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule61_id18365_at_idx5294
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCFILL64rr:%[0-9]+]]:gr64 = BLCFILL64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCFILL64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule62_id18354_at_idx5371
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule62_id18354_at_idx5371
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSI32rr:%[0-9]+]]:gr32 = BLSI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSI32rr]]
+    %2:gpr(s32) = COPY $eax
+    %3:gpr(s32) = G_CONSTANT 0
+    %0:gpr(s32) = G_SUB %3, %2
+    %1:gpr(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule63_id18355_at_idx5448
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule63_id18355_at_idx5448
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSI64rr:%[0-9]+]]:gr64 = BLSI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSI64rr]]
+    %2:gpr(s64) = COPY $rax
+    %3:gpr(s64) = G_CONSTANT 0
+    %0:gpr(s64) = G_SUB %3, %2
+    %1:gpr(s64) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule64_id14478_at_idx5525
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule64_id14478_at_idx5525
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gpr(s1) = G_CONSTANT -1
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF1]], [[C]]
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(s1) = G_AND [[XOR]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](s1)
+    %2:gpr(s1) = IMPLICIT_DEF
+    %3:gpr(s1) = IMPLICIT_DEF
+    %4:gpr(s1) = G_CONSTANT -1
+    %0:gpr(s1) = G_XOR %3, %4
+    %1:gpr(s1) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s1)
+
+...
+---
+name:            test_rule65_id16153_at_idx5657
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule65_id16153_at_idx5657
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSR32rr:%[0-9]+]]:gr32 = BLSR32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSR32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule66_id16154_at_idx5734
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule66_id16154_at_idx5734
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSR64rr:%[0-9]+]]:gr64 = BLSR64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSR64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule67_id16177_at_idx5811
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule67_id16177_at_idx5811
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCFILL32rr:%[0-9]+]]:gr32 = BLCFILL32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCFILL32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule68_id16178_at_idx5888
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule68_id16178_at_idx5888
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCFILL64rr:%[0-9]+]]:gr64 = BLCFILL64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCFILL64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule69_id16157_at_idx5965
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule69_id16157_at_idx5965
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSI32rr:%[0-9]+]]:gr32 = BLSI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSI32rr]]
+    %4:gpr(s32) = COPY $eax
+    %3:gpr(s32) = G_CONSTANT 0
+    %0:gpr(s32) = G_SUB %3, %4
+    %1:gpr(s32) = G_AND %4, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule70_id16158_at_idx6042
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule70_id16158_at_idx6042
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSI64rr:%[0-9]+]]:gr64 = BLSI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSI64rr]]
+    %4:gpr(s64) = COPY $rax
+    %3:gpr(s64) = G_CONSTANT 0
+    %0:gpr(s64) = G_SUB %3, %4
+    %1:gpr(s64) = G_AND %4, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule71_id18158_at_idx6119
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule71_id18158_at_idx6119
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gpr(s1) = G_CONSTANT -1
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF1]], [[C]]
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(s1) = G_AND [[DEF]], [[XOR]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](s1)
+    %2:gpr(s1) = IMPLICIT_DEF
+    %3:gpr(s1) = IMPLICIT_DEF
+    %4:gpr(s1) = G_CONSTANT -1
+    %0:gpr(s1) = G_XOR %3, %4
+    %1:gpr(s1) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s1)
+
+...
+---
+name:            test_rule72_id18374_at_idx6251
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule72_id18374_at_idx6251
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCS32rr:%[0-9]+]]:gr32 = BLCS32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCS32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule73_id18375_at_idx6328
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule73_id18375_at_idx6328
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCS64rr:%[0-9]+]]:gr64 = BLCS64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCS64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule74_id18376_at_idx6405
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule74_id18376_at_idx6405
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSFILL32rr:%[0-9]+]]:gr32 = BLSFILL32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSFILL32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule75_id18377_at_idx6482
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule75_id18377_at_idx6482
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSFILL64rr:%[0-9]+]]:gr64 = BLSFILL64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSFILL64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule76_id18368_at_idx6559
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule76_id18368_at_idx6559
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCI32rr:%[0-9]+]]:gr32 = BLCI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI32rr]]
+    %2:gpr(s32) = COPY $eax
+    %3:gpr(s32) = G_CONSTANT -2
+    %0:gpr(s32) = G_SUB %3, %2
+    %1:gpr(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule77_id18369_at_idx6636
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule77_id18369_at_idx6636
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCI64rr:%[0-9]+]]:gr64 = BLCI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI64rr]]
+    %2:gpr(s64) = COPY $rax
+    %3:gpr(s64) = G_CONSTANT -2
+    %0:gpr(s64) = G_SUB %3, %2
+    %1:gpr(s64) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule78_id16187_at_idx6713
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule78_id16187_at_idx6713
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCS32rr:%[0-9]+]]:gr32 = BLCS32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCS32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule79_id16188_at_idx6790
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule79_id16188_at_idx6790
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCS64rr:%[0-9]+]]:gr64 = BLCS64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCS64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule80_id16189_at_idx6867
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule80_id16189_at_idx6867
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSFILL32rr:%[0-9]+]]:gr32 = BLSFILL32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSFILL32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule81_id16190_at_idx6944
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule81_id16190_at_idx6944
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSFILL64rr:%[0-9]+]]:gr64 = BLSFILL64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSFILL64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule82_id16181_at_idx7021
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule82_id16181_at_idx7021
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCI32rr:%[0-9]+]]:gr32 = BLCI32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI32rr]]
+    %4:gpr(s32) = COPY $eax
+    %3:gpr(s32) = G_CONSTANT -2
+    %0:gpr(s32) = G_SUB %3, %4
+    %1:gpr(s32) = G_OR %4, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule83_id16182_at_idx7098
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule83_id16182_at_idx7098
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCI64rr:%[0-9]+]]:gr64 = BLCI64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCI64rr]]
+    %4:gpr(s64) = COPY $rax
+    %3:gpr(s64) = G_CONSTANT -2
+    %0:gpr(s64) = G_SUB %3, %4
+    %1:gpr(s64) = G_OR %4, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule84_id18352_at_idx7175
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule84_id18352_at_idx7175
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSMSK32rr:%[0-9]+]]:gr32 = BLSMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSMSK32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule85_id18353_at_idx7252
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule85_id18353_at_idx7252
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSMSK64rr:%[0-9]+]]:gr64 = BLSMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSMSK64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule86_id18372_at_idx7329
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule86_id18372_at_idx7329
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCMSK32rr:%[0-9]+]]:gr32 = BLCMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCMSK32rr]]
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %2, %4
+    %1:gpr(s32) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule87_id18373_at_idx7406
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule87_id18373_at_idx7406
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCMSK64rr:%[0-9]+]]:gr64 = BLCMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCMSK64rr]]
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %2, %4
+    %1:gpr(s64) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule88_id18170_at_idx7483
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule88_id18170_at_idx7483
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gpr(s1) = G_CONSTANT -1
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF1]], [[C]]
+    ; SELECTED: [[XOR1:%[0-9]+]]:gpr(s1) = G_XOR [[XOR]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR1]](s1)
+    %2:gpr(s1) = IMPLICIT_DEF
+    %3:gpr(s1) = IMPLICIT_DEF
+    %4:gpr(s1) = G_CONSTANT -1
+    %0:gpr(s1) = G_XOR %3, %4
+    %1:gpr(s1) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s1)
+
+...
+---
+name:            test_rule89_id14486_at_idx7615
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule89_id14486_at_idx7615
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gpr(s1) = G_CONSTANT -1
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: [[XOR1:%[0-9]+]]:gpr(s1) = G_XOR [[XOR]], [[C]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR1]](s1)
+    %3:gpr(s1) = IMPLICIT_DEF
+    %4:gpr(s1) = IMPLICIT_DEF
+    %2:gpr(s1) = G_CONSTANT -1
+    %0:gpr(s1) = G_XOR %3, %4
+    %1:gpr(s1) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s1)
+
+...
+---
+name:            test_rule90_id16155_at_idx7747
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule90_id16155_at_idx7747
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLSMSK32rr:%[0-9]+]]:gr32 = BLSMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSMSK32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_XOR %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule91_id16156_at_idx7824
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule91_id16156_at_idx7824
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLSMSK64rr:%[0-9]+]]:gr64 = BLSMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLSMSK64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_XOR %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule92_id16185_at_idx7901
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule92_id16185_at_idx7901
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BLCMSK32rr:%[0-9]+]]:gr32 = BLCMSK32rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCMSK32rr]]
+    %3:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %3, %4
+    %1:gpr(s32) = G_XOR %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule93_id16186_at_idx7978
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule93_id16186_at_idx7978
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BLCMSK64rr:%[0-9]+]]:gr64 = BLCMSK64rr [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[BLCMSK64rr]]
+    %3:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %3, %4
+    %1:gpr(s64) = G_XOR %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule94_id18171_at_idx8055
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule94_id18171_at_idx8055
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gpr(s1) = G_CONSTANT -1
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF1]], [[C]]
+    ; SELECTED: [[XOR1:%[0-9]+]]:gpr(s1) = G_XOR [[DEF]], [[XOR]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR1]](s1)
+    %2:gpr(s1) = IMPLICIT_DEF
+    %3:gpr(s1) = IMPLICIT_DEF
+    %4:gpr(s1) = G_CONSTANT -1
+    %0:gpr(s1) = G_XOR %3, %4
+    %1:gpr(s1) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s1)
+
+...
+---
+name:            test_rule95_id12302_at_idx8187
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule95_id12302_at_idx8187
+    ; SELECTED: XABORT 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s8) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xabort), %0(s8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule96_id12307_at_idx8239
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule96_id12307_at_idx8239
+    ; SELECTED: INT 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s8) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.int), %0(s8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule97_id15615_at_idx8289
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule97_id15615_at_idx8289
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; SELECTED: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVZX32rr16_]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT 65535
+    %0:gpr(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule98_id15616_at_idx8356
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule98_id15616_at_idx8356
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; SELECTED: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVZX32rr8_]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT 255
+    %0:gpr(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule99_id12365_at_idx8423
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule99_id12365_at_idx8423
+    ; SELECTED: [[MOV32ImmSExti8_:%[0-9]+]]:gr32 = MOV32ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV32ImmSExti8_]]
+    %0:gpr(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule100_id12366_at_idx8461
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule100_id12366_at_idx8461
+    ; SELECTED: [[MOV64ImmSExti8_:%[0-9]+]]:gr64 = MOV64ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV64ImmSExti8_]]
+    %0:gpr(s64) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule101_id1221_at_idx8499
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule101_id1221_at_idx8499
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMADCSWDrr:%[0-9]+]]:vr128 = VPMADCSWDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMADCSWDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmadcswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule102_id1223_at_idx8571
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule102_id1223_at_idx8571
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMADCSSWDrr:%[0-9]+]]:vr128 = VPMADCSSWDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMADCSSWDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmadcsswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule103_id1225_at_idx8643
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule103_id1225_at_idx8643
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSWWrr:%[0-9]+]]:vr128 = VPMACSWWrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSWWrr]]
+    %3:vecr(<8 x s16>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsww), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule104_id1227_at_idx8715
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule104_id1227_at_idx8715
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSWDrr:%[0-9]+]]:vr128 = VPMACSWDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSWDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule105_id1229_at_idx8787
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule105_id1229_at_idx8787
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSSWWrr:%[0-9]+]]:vr128 = VPMACSSWWrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSSWWrr]]
+    %3:vecr(<8 x s16>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssww), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule106_id1231_at_idx8859
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule106_id1231_at_idx8859
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSSWDrr:%[0-9]+]]:vr128 = VPMACSSWDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSSWDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule107_id1233_at_idx8931
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule107_id1233_at_idx8931
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSSDQLrr:%[0-9]+]]:vr128 = VPMACSSDQLrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSSDQLrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdql), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule108_id1235_at_idx9003
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule108_id1235_at_idx9003
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSSDQHrr:%[0-9]+]]:vr128 = VPMACSSDQHrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSSDQHrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdqh), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule109_id1237_at_idx9075
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule109_id1237_at_idx9075
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSSDDrr:%[0-9]+]]:vr128 = VPMACSSDDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSSDDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdd), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule110_id1239_at_idx9147
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule110_id1239_at_idx9147
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSDQLrr:%[0-9]+]]:vr128 = VPMACSDQLrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSDQLrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdql), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule111_id1241_at_idx9219
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule111_id1241_at_idx9219
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSDQHrr:%[0-9]+]]:vr128 = VPMACSDQHrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSDQHrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdqh), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule112_id1243_at_idx9291
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule112_id1243_at_idx9291
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSDDrr:%[0-9]+]]:vr128 = VPMACSDDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSDDrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdd), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule113_id2583_at_idx9363
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule113_id2583_at_idx9363
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VBLENDVPDrr:%[0-9]+]]:vr128 = VBLENDVPDrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBLENDVPDrr]]
+    %3:vecr(<2 x s64>) = COPY $xmm2
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.blendvpd), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule114_id2585_at_idx9435
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+  - { reg: '$ymm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1, $ymm2
+
+    ; SELECTED-LABEL: name: test_rule114_id2585_at_idx9435
+    ; SELECTED: liveins: $ymm0, $ymm1, $ymm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VBLENDVPDYrr:%[0-9]+]]:vr256 = VBLENDVPDYrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBLENDVPDYrr]]
+    %3:vecr(<4 x s64>) = COPY $ymm2
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.avx.blendv.pd.256), %1(<4 x s64>), %2(<4 x s64>), %3(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule115_id2587_at_idx9507
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule115_id2587_at_idx9507
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VBLENDVPSrr:%[0-9]+]]:vr128 = VBLENDVPSrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBLENDVPSrr]]
+    %3:vecr(<4 x s32>) = COPY $xmm2
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.blendvps), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule116_id2589_at_idx9579
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+  - { reg: '$ymm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1, $ymm2
+
+    ; SELECTED-LABEL: name: test_rule116_id2589_at_idx9579
+    ; SELECTED: liveins: $ymm0, $ymm1, $ymm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VBLENDVPSYrr:%[0-9]+]]:vr256 = VBLENDVPSYrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBLENDVPSYrr]]
+    %3:vecr(<8 x s32>) = COPY $ymm2
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx.blendv.ps.256), %1(<8 x s32>), %2(<8 x s32>), %3(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule117_id2591_at_idx9651
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+  - { reg: '$xmm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule117_id2591_at_idx9651
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPBLENDVBrr:%[0-9]+]]:vr128 = VPBLENDVBrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPBLENDVBrr]]
+    %3:vecr(<16 x s8>) = COPY $xmm2
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.pblendvb), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule118_id2593_at_idx9723
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+  - { reg: '$ymm2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1, $ymm2
+
+    ; SELECTED-LABEL: name: test_rule118_id2593_at_idx9723
+    ; SELECTED: liveins: $ymm0, $ymm1, $ymm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPBLENDVBYrr:%[0-9]+]]:vr256 = VPBLENDVBYrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPBLENDVBYrr]]
+    %3:vecr(<32 x s8>) = COPY $ymm2
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.pblendvb), %1(<32 x s8>), %2(<32 x s8>), %3(<32 x s8>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule119_id82_at_idx9795
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule119_id82_at_idx9795
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[PDEP32rr:%[0-9]+]]:gr32 = PDEP32rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PDEP32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pdep.32), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule120_id84_at_idx9855
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule120_id84_at_idx9855
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[PDEP64rr:%[0-9]+]]:gr64 = PDEP64rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PDEP64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pdep.64), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule121_id86_at_idx9915
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule121_id86_at_idx9915
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[PEXT32rr:%[0-9]+]]:gr32 = PEXT32rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PEXT32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pext.32), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule122_id88_at_idx9975
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule122_id88_at_idx9975
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[PEXT64rr:%[0-9]+]]:gr64 = PEXT64rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PEXT64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pext.64), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule123_id1377_at_idx10035
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule123_id1377_at_idx10035
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SSrr_Int:%[0-9]+]]:vr128 = VCVTSI2SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SSrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule124_id1379_at_idx10095
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule124_id1379_at_idx10095
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SSrr_Int:%[0-9]+]]:vr128 = VCVTSI642SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SSrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule125_id1381_at_idx10155
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule125_id1381_at_idx10155
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SDrr_Int:%[0-9]+]]:vr128 = VCVTSI2SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SDrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule126_id1383_at_idx10215
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule126_id1383_at_idx10215
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SDrr_Int:%[0-9]+]]:vr128 = VCVTSI642SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SDrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule127_id1385_at_idx10275
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule127_id1385_at_idx10275
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SSrr_Int:%[0-9]+]]:vr128 = VCVTSI2SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SSrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule128_id1387_at_idx10335
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule128_id1387_at_idx10335
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SSrr_Int:%[0-9]+]]:vr128 = VCVTSI642SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SSrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule129_id1389_at_idx10395
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule129_id1389_at_idx10395
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SDrr_Int:%[0-9]+]]:vr128 = VCVTSI2SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SDrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule130_id1391_at_idx10455
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule130_id1391_at_idx10455
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SDrr_Int:%[0-9]+]]:vr128 = VCVTSI642SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SDrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule131_id1425_at_idx10515
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule131_id1425_at_idx10515
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SSrr_Int:%[0-9]+]]:vr128 = VCVTSD2SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SSrr_Int]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2ss), %1(<4 x s32>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule132_id1427_at_idx10575
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule132_id1427_at_idx10575
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SSrr_Int:%[0-9]+]]:vr128 = VCVTSD2SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SSrr_Int]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2ss), %1(<4 x s32>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule133_id1431_at_idx10635
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule133_id1431_at_idx10635
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SDrr_Int:%[0-9]+]]:vr128 = VCVTSS2SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SDrr_Int]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtss2sd), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule134_id1433_at_idx10695
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule134_id1433_at_idx10695
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SDrr_Int:%[0-9]+]]:vr128 = VCVTSS2SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SDrr_Int]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtss2sd), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule135_id2339_at_idx10755
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule135_id2339_at_idx10755
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNBrr:%[0-9]+]]:vr128 = VPSIGNBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.b.128), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule136_id2341_at_idx10815
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule136_id2341_at_idx10815
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNWrr:%[0-9]+]]:vr128 = VPSIGNWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.w.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule137_id2343_at_idx10875
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule137_id2343_at_idx10875
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNDrr:%[0-9]+]]:vr128 = VPSIGNDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.d.128), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule138_id2345_at_idx10935
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule138_id2345_at_idx10935
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDSWrr:%[0-9]+]]:vr128 = VPHADDSWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDSWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phadd.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule139_id2347_at_idx10995
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule139_id2347_at_idx10995
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHSUBSWrr:%[0-9]+]]:vr128 = VPHSUBSWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBSWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phsub.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule140_id2363_at_idx11055
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule140_id2363_at_idx11055
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSIGNBYrr:%[0-9]+]]:vr256 = VPSIGNBYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNBYrr]]
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.b), %1(<32 x s8>), %2(<32 x s8>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule141_id2365_at_idx11115
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule141_id2365_at_idx11115
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSIGNWYrr:%[0-9]+]]:vr256 = VPSIGNWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.w), %1(<16 x s16>), %2(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule142_id2367_at_idx11175
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule142_id2367_at_idx11175
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSIGNDYrr:%[0-9]+]]:vr256 = VPSIGNDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.d), %1(<8 x s32>), %2(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule143_id2369_at_idx11235
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule143_id2369_at_idx11235
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPHADDSWYrr:%[0-9]+]]:vr256 = VPHADDSWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDSWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.phadd.sw), %1(<16 x s16>), %2(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule144_id2371_at_idx11295
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule144_id2371_at_idx11295
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPHSUBSWYrr:%[0-9]+]]:vr256 = VPHSUBSWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBSWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.phsub.sw), %1(<16 x s16>), %2(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule145_id2381_at_idx11355
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule145_id2381_at_idx11355
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNBrr:%[0-9]+]]:vr128 = VPSIGNBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.b.128), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule146_id2383_at_idx11415
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule146_id2383_at_idx11415
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNWrr:%[0-9]+]]:vr128 = VPSIGNWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.w.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule147_id2385_at_idx11475
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule147_id2385_at_idx11475
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSIGNDrr:%[0-9]+]]:vr128 = VPSIGNDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSIGNDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.d.128), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule148_id2389_at_idx11535
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule148_id2389_at_idx11535
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDSWrr:%[0-9]+]]:vr128 = VPHADDSWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDSWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phadd.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule149_id2391_at_idx11595
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule149_id2391_at_idx11595
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHSUBSWrr:%[0-9]+]]:vr128 = VPHSUBSWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBSWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phsub.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule150_id2624_at_idx11655
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $al
+
+    ; SELECTED-LABEL: name: test_rule150_id2624_at_idx11655
+    ; SELECTED: liveins: $eax, $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CRC32r32r8_:%[0-9]+]]:gr32 = CRC32r32r8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32r32r8_]]
+    %2:gpr(s8) = COPY $al
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.8), %1(s32), %2(s8)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule151_id2626_at_idx11715
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ax
+
+    ; SELECTED-LABEL: name: test_rule151_id2626_at_idx11715
+    ; SELECTED: liveins: $eax, $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CRC32r32r16_:%[0-9]+]]:gr32 = CRC32r32r16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32r32r16_]]
+    %2:gpr(s16) = COPY $ax
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.16), %1(s32), %2(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule152_id2628_at_idx11775
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule152_id2628_at_idx11775
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CRC32r32r32_:%[0-9]+]]:gr32 = CRC32r32r32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32r32r32_]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.32), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule153_id2630_at_idx11835
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule153_id2630_at_idx11835
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CRC32r64r64_:%[0-9]+]]:gr64 = CRC32r64r64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32r64r64_]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.64.64), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule154_id2633_at_idx11895
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule154_id2633_at_idx11895
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA1NEXTErr:%[0-9]+]]:vr128 = SHA1NEXTErr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1NEXTErr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1nexte), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule155_id2635_at_idx11955
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule155_id2635_at_idx11955
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA1MSG1rr:%[0-9]+]]:vr128 = SHA1MSG1rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1MSG1rr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1msg1), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule156_id2637_at_idx12015
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule156_id2637_at_idx12015
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA1MSG2rr:%[0-9]+]]:vr128 = SHA1MSG2rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1MSG2rr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1msg2), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule157_id2641_at_idx12075
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule157_id2641_at_idx12075
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA256MSG1rr:%[0-9]+]]:vr128 = SHA256MSG1rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256MSG1rr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha256msg1), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule158_id2643_at_idx12135
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule158_id2643_at_idx12135
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SHA256MSG2rr:%[0-9]+]]:vr128 = SHA256MSG2rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256MSG2rr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha256msg2), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule159_id2645_at_idx12195
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule159_id2645_at_idx12195
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCrr:%[0-9]+]]:vr128 = VAESENCrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule160_id2647_at_idx12255
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule160_id2647_at_idx12255
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCLASTrr:%[0-9]+]]:vr128 = VAESENCLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule161_id2649_at_idx12315
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule161_id2649_at_idx12315
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECrr:%[0-9]+]]:vr128 = VAESDECrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule162_id2651_at_idx12375
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule162_id2651_at_idx12375
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECLASTrr:%[0-9]+]]:vr128 = VAESDECLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule163_id2653_at_idx12435
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule163_id2653_at_idx12435
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESENCYrr:%[0-9]+]]:vr256 = VAESENCYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule164_id2655_at_idx12495
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule164_id2655_at_idx12495
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESENCLASTYrr:%[0-9]+]]:vr256 = VAESENCLASTYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule165_id2657_at_idx12555
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule165_id2657_at_idx12555
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESDECYrr:%[0-9]+]]:vr256 = VAESDECYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule166_id2659_at_idx12615
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule166_id2659_at_idx12615
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESDECLASTYrr:%[0-9]+]]:vr256 = VAESDECLASTYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule167_id2661_at_idx12675
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule167_id2661_at_idx12675
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCrr:%[0-9]+]]:vr128 = VAESENCrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule168_id2663_at_idx12735
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule168_id2663_at_idx12735
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCLASTrr:%[0-9]+]]:vr128 = VAESENCLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule169_id2665_at_idx12795
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule169_id2665_at_idx12795
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECrr:%[0-9]+]]:vr128 = VAESDECrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule170_id2667_at_idx12855
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule170_id2667_at_idx12855
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECLASTrr:%[0-9]+]]:vr128 = VAESDECLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule171_id2684_at_idx12915
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule171_id2684_at_idx12915
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[EXTRQ:%[0-9]+]]:vr128 = EXTRQ [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EXTRQ]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse4a.extrq), %1(<2 x s64>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule172_id2686_at_idx12975
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule172_id2686_at_idx12975
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[INSERTQ:%[0-9]+]]:vr128 = INSERTQ [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[INSERTQ]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse4a.insertq), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule173_id11466_at_idx13035
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule173_id11466_at_idx13035
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCrr:%[0-9]+]]:vr128 = VAESENCrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule174_id11468_at_idx13095
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule174_id11468_at_idx13095
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESENCYrr:%[0-9]+]]:vr256 = VAESENCYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule175_id11470_at_idx13155
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule175_id11470_at_idx13155
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VAESENCZrr:%[0-9]+]]:vr512 = VAESENCZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.512), %1(<8 x s64>), %2(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule176_id11472_at_idx13215
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule176_id11472_at_idx13215
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESENCLASTrr:%[0-9]+]]:vr128 = VAESENCLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule177_id11474_at_idx13275
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule177_id11474_at_idx13275
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESENCLASTYrr:%[0-9]+]]:vr256 = VAESENCLASTYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule178_id11476_at_idx13335
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule178_id11476_at_idx13335
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VAESENCLASTZrr:%[0-9]+]]:vr512 = VAESENCLASTZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESENCLASTZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.512), %1(<8 x s64>), %2(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule179_id11478_at_idx13395
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule179_id11478_at_idx13395
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECrr:%[0-9]+]]:vr128 = VAESDECrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule180_id11480_at_idx13455
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule180_id11480_at_idx13455
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESDECYrr:%[0-9]+]]:vr256 = VAESDECYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule181_id11482_at_idx13515
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule181_id11482_at_idx13515
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VAESDECZrr:%[0-9]+]]:vr512 = VAESDECZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.512), %1(<8 x s64>), %2(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule182_id11484_at_idx13575
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule182_id11484_at_idx13575
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESDECLASTrr:%[0-9]+]]:vr128 = VAESDECLASTrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule183_id11486_at_idx13635
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule183_id11486_at_idx13635
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VAESDECLASTYrr:%[0-9]+]]:vr256 = VAESDECLASTYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.256), %1(<4 x s64>), %2(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule184_id11488_at_idx13695
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule184_id11488_at_idx13695
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VAESDECLASTZrr:%[0-9]+]]:vr512 = VAESDECLASTZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESDECLASTZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.512), %1(<8 x s64>), %2(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule185_id15146_at_idx13755
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule185_id15146_at_idx13755
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SSrr_Int:%[0-9]+]]:vr128 = VCVTSI2SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SSrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule186_id15148_at_idx13815
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule186_id15148_at_idx13815
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SSrr_Int:%[0-9]+]]:vr128 = VCVTSI642SSrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SSrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule187_id15150_at_idx13875
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule187_id15150_at_idx13875
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI2SDrr_Int:%[0-9]+]]:vr128 = VCVTSI2SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI2SDrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule188_id15152_at_idx13935
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $rax
+
+    ; SELECTED-LABEL: name: test_rule188_id15152_at_idx13935
+    ; SELECTED: liveins: $xmm0, $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSI642SDrr_Int:%[0-9]+]]:vr128 = VCVTSI642SDrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSI642SDrr_Int]]
+    %2:gpr(s64) = COPY $rax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule189_id15154_at_idx13995
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $eax
+
+    ; SELECTED-LABEL: name: test_rule189_id15154_at_idx13995
+    ; SELECTED: liveins: $xmm0, $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTUSI2SDZrr_Int:%[0-9]+]]:vr128x = VCVTUSI2SDZrr_Int [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUSI2SDZrr_Int]]
+    %2:gpr(s32) = COPY $eax
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.avx512.cvtusi2sd), %1(<2 x s64>), %2(s32)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule190_id15605_at_idx14055
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule190_id15605_at_idx14055
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[SUB16ri8_:%[0-9]+]]:gr16 = SUB16ri8 [[COPY]], -128, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB16ri8_]]
+    %1:gpr(s16) = COPY $ax
+    %2:gpr(s16) = G_CONSTANT 128
+    %0:gpr(s16) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule191_id15607_at_idx14108
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule191_id15607_at_idx14108
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[SUB32ri8_:%[0-9]+]]:gr32 = SUB32ri8 [[COPY]], -128, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB32ri8_]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT 128
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule192_id15609_at_idx14161
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule192_id15609_at_idx14161
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[SUB64ri8_:%[0-9]+]]:gr64 = SUB64ri8 [[COPY]], -128, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB64ri8_]]
+    %1:gpr(s64) = COPY $rax
+    %2:gpr(s64) = G_CONSTANT 128
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule193_id15611_at_idx14214
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule193_id15611_at_idx14214
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[SUB64ri32_:%[0-9]+]]:gr64 = SUB64ri32 [[COPY]], -2147483648, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB64ri32_]]
+    %1:gpr(s64) = COPY $rax
+    %2:gpr(s64) = G_CONSTANT 2147483648
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule194_id15775_at_idx14267
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule194_id15775_at_idx14267
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[INC8r:%[0-9]+]]:gr8 = INC8r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC8r]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule195_id15776_at_idx14319
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule195_id15776_at_idx14319
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[INC16r:%[0-9]+]]:gr16 = INC16r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC16r]]
+    %1:gpr(s16) = COPY $ax
+    %2:gpr(s16) = G_CONSTANT 1
+    %0:gpr(s16) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule196_id15777_at_idx14371
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule196_id15777_at_idx14371
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[INC32r:%[0-9]+]]:gr32 = INC32r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC32r]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT 1
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule197_id15778_at_idx14423
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule197_id15778_at_idx14423
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[INC64r:%[0-9]+]]:gr64 = INC64r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC64r]]
+    %1:gpr(s64) = COPY $rax
+    %2:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule198_id15779_at_idx14475
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule198_id15779_at_idx14475
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[DEC8r:%[0-9]+]]:gr8 = DEC8r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[DEC8r]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT -1
+    %0:gpr(s8) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule199_id15780_at_idx14527
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule199_id15780_at_idx14527
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[DEC16r:%[0-9]+]]:gr16 = DEC16r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[DEC16r]]
+    %1:gpr(s16) = COPY $ax
+    %2:gpr(s16) = G_CONSTANT -1
+    %0:gpr(s16) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule200_id15781_at_idx14579
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule200_id15781_at_idx14579
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[DEC32r]]
+    %1:gpr(s32) = COPY $eax
+    %2:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule201_id15782_at_idx14631
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule201_id15782_at_idx14631
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[DEC64r:%[0-9]+]]:gr64 = DEC64r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[DEC64r]]
+    %1:gpr(s64) = COPY $rax
+    %2:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule202_id625_at_idx14683
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule202_id625_at_idx14683
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule203_id626_at_idx14733
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule203_id626_at_idx14733
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule204_id627_at_idx14783
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule204_id627_at_idx14783
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule205_id628_at_idx14833
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule205_id628_at_idx14833
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule206_id1135_at_idx14883
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule206_id1135_at_idx14883
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHSUBWDrr:%[0-9]+]]:vr128 = VPHSUBWDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBWDrr]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubwd), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule207_id1137_at_idx14931
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule207_id1137_at_idx14931
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHSUBDQrr:%[0-9]+]]:vr128 = VPHSUBDQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBDQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubdq), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule208_id1139_at_idx14979
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule208_id1139_at_idx14979
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHSUBBWrr:%[0-9]+]]:vr128 = VPHSUBBWrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHSUBBWrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubbw), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule209_id1141_at_idx15027
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule209_id1141_at_idx15027
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDWQrr:%[0-9]+]]:vr128 = VPHADDWQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDWQrr]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddwq), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule210_id1143_at_idx15075
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule210_id1143_at_idx15075
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDWDrr:%[0-9]+]]:vr128 = VPHADDWDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDWDrr]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddwd), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule211_id1145_at_idx15123
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule211_id1145_at_idx15123
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUWQrr:%[0-9]+]]:vr128 = VPHADDUWQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUWQrr]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadduwq), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule212_id1147_at_idx15171
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule212_id1147_at_idx15171
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUWDrr:%[0-9]+]]:vr128 = VPHADDUWDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUWDrr]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadduwd), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule213_id1149_at_idx15219
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule213_id1149_at_idx15219
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUDQrr:%[0-9]+]]:vr128 = VPHADDUDQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUDQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddudq), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule214_id1151_at_idx15267
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule214_id1151_at_idx15267
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUBWrr:%[0-9]+]]:vr128 = VPHADDUBWrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUBWrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubw), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule215_id1153_at_idx15315
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule215_id1153_at_idx15315
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUBQrr:%[0-9]+]]:vr128 = VPHADDUBQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUBQrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubq), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule216_id1155_at_idx15363
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule216_id1155_at_idx15363
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDUBDrr:%[0-9]+]]:vr128 = VPHADDUBDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDUBDrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubd), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule217_id1157_at_idx15411
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule217_id1157_at_idx15411
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDDQrr:%[0-9]+]]:vr128 = VPHADDDQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDDQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadddq), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule218_id1159_at_idx15459
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule218_id1159_at_idx15459
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDBWrr:%[0-9]+]]:vr128 = VPHADDBWrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDBWrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbw), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule219_id1161_at_idx15507
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule219_id1161_at_idx15507
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDBQrr:%[0-9]+]]:vr128 = VPHADDBQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDBQrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbq), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule220_id1163_at_idx15555
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule220_id1163_at_idx15555
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPHADDBDrr:%[0-9]+]]:vr128 = VPHADDBDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPHADDBDrr]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbd), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule221_id1165_at_idx15603
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule221_id1165_at_idx15603
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VFRCZSSrr:%[0-9]+]]:vr128 = VFRCZSSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZSSrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule222_id1167_at_idx15651
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule222_id1167_at_idx15651
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VFRCZPSrr:%[0-9]+]]:vr128 = VFRCZPSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZPSrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ps), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule223_id1169_at_idx15699
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule223_id1169_at_idx15699
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VFRCZPSYrr:%[0-9]+]]:vr256 = VFRCZPSYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZPSYrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ps.256), %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule224_id1171_at_idx15747
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule224_id1171_at_idx15747
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VFRCZSDrr:%[0-9]+]]:vr128 = VFRCZSDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZSDrr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.sd), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule225_id1173_at_idx15795
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule225_id1173_at_idx15795
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VFRCZPDrr:%[0-9]+]]:vr128 = VFRCZPDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZPDrr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.pd), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule226_id1175_at_idx15843
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule226_id1175_at_idx15843
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VFRCZPDYrr:%[0-9]+]]:vr256 = VFRCZPDYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFRCZPDYrr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.pd.256), %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule227_id1369_at_idx15891
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule227_id1369_at_idx15891
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule228_id1371_at_idx15939
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule228_id1371_at_idx15939
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule229_id1373_at_idx15987
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule229_id1373_at_idx15987
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule230_id1375_at_idx16035
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule230_id1375_at_idx16035
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule231_id1393_at_idx16083
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule231_id1393_at_idx16083
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule232_id1395_at_idx16131
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule232_id1395_at_idx16131
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule233_id1397_at_idx16179
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule233_id1397_at_idx16179
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule234_id1399_at_idx16227
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule234_id1399_at_idx16227
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule235_id1401_at_idx16275
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule235_id1401_at_idx16275
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule236_id1403_at_idx16323
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule236_id1403_at_idx16323
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule237_id1405_at_idx16371
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule237_id1405_at_idx16371
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule238_id1407_at_idx16419
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule238_id1407_at_idx16419
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule239_id1409_at_idx16467
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule239_id1409_at_idx16467
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule240_id1411_at_idx16515
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule240_id1411_at_idx16515
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule241_id1413_at_idx16563
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule241_id1413_at_idx16563
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule242_id1415_at_idx16611
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule242_id1415_at_idx16611
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule243_id2669_at_idx16659
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule243_id2669_at_idx16659
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESIMCrr:%[0-9]+]]:vr128 = VAESIMCrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESIMCrr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesimc), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule244_id2671_at_idx16707
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule244_id2671_at_idx16707
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VAESIMCrr:%[0-9]+]]:vr128 = VAESIMCrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VAESIMCrr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesimc), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule245_id12550_at_idx16755
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule245_id12550_at_idx16755
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[RCPSSr_Int:%[0-9]+]]:vr128 = RCPSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RCPSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rcp.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule246_id12552_at_idx16807
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule246_id12552_at_idx16807
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[RSQRTSSr_Int:%[0-9]+]]:vr128 = RSQRTSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSQRTSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rsqrt.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule247_id12554_at_idx16859
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule247_id12554_at_idx16859
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSDr_Int:%[0-9]+]]:vr128 = SQRTSDr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSDr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule248_id12556_at_idx16911
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule248_id12556_at_idx16911
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSSr_Int:%[0-9]+]]:vr128 = SQRTSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule249_id13332_at_idx16963
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule249_id13332_at_idx16963
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[RCPSSr_Int:%[0-9]+]]:vr128 = RCPSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RCPSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rcp.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule250_id13356_at_idx17015
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule250_id13356_at_idx17015
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[RSQRTSSr_Int:%[0-9]+]]:vr128 = RSQRTSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSQRTSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rsqrt.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule251_id13360_at_idx17067
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule251_id13360_at_idx17067
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSDr_Int:%[0-9]+]]:vr128 = SQRTSDr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSDr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule252_id13364_at_idx17119
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule252_id13364_at_idx17119
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSDr_Int:%[0-9]+]]:vr128 = SQRTSDr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSDr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule253_id13368_at_idx17171
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule253_id13368_at_idx17171
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSSr_Int:%[0-9]+]]:vr128 = SQRTSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule254_id13372_at_idx17223
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule254_id13372_at_idx17223
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[SQRTSSr_Int:%[0-9]+]]:vr128 = SQRTSSr_Int [[COPY]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRTSSr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule255_id15138_at_idx17275
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule255_id15138_at_idx17275
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule256_id15140_at_idx17323
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule256_id15140_at_idx17323
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule257_id15142_at_idx17371
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule257_id15142_at_idx17371
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule258_id15144_at_idx17419
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule258_id15144_at_idx17419
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule259_id15160_at_idx17467
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule259_id15160_at_idx17467
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSS2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule260_id15162_at_idx17515
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule260_id15162_at_idx17515
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSS2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSS2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr_Int]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule261_id15164_at_idx17563
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule261_id15164_at_idx17563
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SIrr_Int:%[0-9]+]]:gr32 = VCVTTSD2SIrr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule262_id15166_at_idx17611
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule262_id15166_at_idx17611
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTSD2SI64rr_Int:%[0-9]+]]:gr64 = VCVTTSD2SI64rr_Int [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr_Int]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule263_id12311_at_idx17659
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule263_id12311_at_idx17659
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[RDSSPD:%[0-9]+]]:gr32 = RDSSPD [[COPY]], implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDSSPD]]
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdsspd), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule264_id12312_at_idx17711
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule264_id12312_at_idx17711
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[RDSSPQ:%[0-9]+]]:gr64 = RDSSPQ [[COPY]], implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDSSPQ]]
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdsspq), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule265_id601_at_idx17763
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule265_id601_at_idx17763
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule266_id602_at_idx17813
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule266_id602_at_idx17813
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule267_id603_at_idx17863
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule267_id603_at_idx17863
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule268_id604_at_idx17913
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule268_id604_at_idx17913
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule269_id15656_at_idx17963
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule269_id15656_at_idx17963
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule270_id15657_at_idx18017
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule270_id15657_at_idx18017
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule271_id15658_at_idx18071
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule271_id15658_at_idx18071
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule272_id15659_at_idx18125
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule272_id15659_at_idx18125
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %1:gpr(s8) = COPY $al
+    %2:gpr(s8) = G_CONSTANT 1
+    %0:gpr(s8) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule273_id1_at_idx18179
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule273_id1_at_idx18179
+    ; SELECTED: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def $esp, implicit $esp
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDFLAGS32_]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule274_id2_at_idx18219
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule274_id2_at_idx18219
+    ; SELECTED: [[RDFLAGS64_:%[0-9]+]]:gr64 = RDFLAGS64 implicit-def $esp, implicit $rsp
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDFLAGS64_]]
+    %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule275_id95_at_idx18259
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule275_id95_at_idx18259
+    ; SELECTED: [[SLWPCB:%[0-9]+]]:gr32 = SLWPCB
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLWPCB]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.slwpcb)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule276_id97_at_idx18299
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule276_id97_at_idx18299
+    ; SELECTED: [[SLWPCB64_:%[0-9]+]]:gr64 = SLWPCB64
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLWPCB64_]]
+    %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.slwpcb)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule277_id12299_at_idx18339
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule277_id12299_at_idx18339
+    ; SELECTED: [[XBEGIN:%[0-9]+]]:gr32 = XBEGIN
+    ; SELECTED: $noreg = PATCHABLE_RET [[XBEGIN]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xbegin)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule278_id12335_at_idx18379
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule278_id12335_at_idx18379
+    ; SELECTED: [[RDPKRU:%[0-9]+]]:gr32 = RDPKRU
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDPKRU]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdpkru)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule279_id12336_at_idx18417
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule279_id12336_at_idx18417
+    ; SELECTED: [[RDFSBASE:%[0-9]+]]:gr32 = RDFSBASE
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDFSBASE]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdfsbase.32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule280_id12337_at_idx18457
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule280_id12337_at_idx18457
+    ; SELECTED: [[RDFSBASE64_:%[0-9]+]]:gr64 = RDFSBASE64
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDFSBASE64_]]
+    %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdfsbase.64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule281_id12338_at_idx18497
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule281_id12338_at_idx18497
+    ; SELECTED: [[RDGSBASE:%[0-9]+]]:gr32 = RDGSBASE
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDGSBASE]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdgsbase.32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule282_id12339_at_idx18537
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule282_id12339_at_idx18537
+    ; SELECTED: [[RDGSBASE64_:%[0-9]+]]:gr64 = RDGSBASE64
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDGSBASE64_]]
+    %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdgsbase.64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule283_id12344_at_idx18577
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule283_id12344_at_idx18577
+    ; SELECTED: [[RDPID32_:%[0-9]+]]:gr32 = RDPID32
+    ; SELECTED: $noreg = PATCHABLE_RET [[RDPID32_]]
+    %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdpid)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule284_id3_at_idx18617
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule284_id3_at_idx18617
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: WRFLAGS32 [[COPY]], implicit-def $esp, implicit-def $eflags, implicit $esp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.write.u32), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule285_id4_at_idx18657
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule285_id4_at_idx18657
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: WRFLAGS64 [[COPY]], implicit-def $rsp, implicit-def $eflags, implicit $rsp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s64) = COPY $rax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.write.u64), %0(s64)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule286_id94_at_idx18697
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule286_id94_at_idx18697
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: LLWPCB [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.llwpcb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule287_id96_at_idx18737
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule287_id96_at_idx18737
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: LLWPCB64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s64) = COPY $rax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.llwpcb), %0(s64)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule288_id12309_at_idx18777
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule288_id12309_at_idx18777
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: INCSSPD [[COPY]], implicit-def $ssp, implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.incsspd), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule289_id12310_at_idx18817
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule289_id12310_at_idx18817
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: INCSSPQ [[COPY]], implicit-def $ssp, implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s64) = COPY $rax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.incsspq), %0(s64)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule290_id12334_at_idx18857
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule290_id12334_at_idx18857
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: WRPKRU [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrpkru), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule291_id12340_at_idx18895
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule291_id12340_at_idx18895
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: WRFSBASE [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrfsbase.32), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule292_id12341_at_idx18935
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule292_id12341_at_idx18935
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: WRFSBASE64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s64) = COPY $rax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrfsbase.64), %0(s64)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule293_id12342_at_idx18975
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule293_id12342_at_idx18975
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: WRGSBASE [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = COPY $eax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrgsbase.32), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule294_id12343_at_idx19015
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule294_id12343_at_idx19015
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: WRGSBASE64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s64) = COPY $rax
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrgsbase.64), %0(s64)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule295_id1819_at_idx19055
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule295_id1819_at_idx19055
+    ; SELECTED: PAUSE
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.pause)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule296_id1820_at_idx19081
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule296_id1820_at_idx19081
+    ; SELECTED: SFENCE
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse.sfence)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule297_id1821_at_idx19109
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule297_id1821_at_idx19109
+    ; SELECTED: LFENCE
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.lfence)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule298_id1822_at_idx19137
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule298_id1822_at_idx19137
+    ; SELECTED: MFENCE
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.mfence)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule299_id2719_at_idx19165
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule299_id2719_at_idx19165
+    ; SELECTED: VZEROALL implicit-def $ymm0, implicit-def $ymm1, implicit-def $ymm2, implicit-def $ymm3, implicit-def $ymm4, implicit-def $ymm5, implicit-def $ymm6, implicit-def $ymm7, implicit-def $ymm8, implicit-def $ymm9, implicit-def $ymm10, implicit-def $ymm11, implicit-def $ymm12, implicit-def $ymm13, implicit-def $ymm14, implicit-def $ymm15
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.avx.vzeroall)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule300_id2720_at_idx19193
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule300_id2720_at_idx19193
+    ; SELECTED: VZEROUPPER implicit-def $ymm0, implicit-def $ymm1, implicit-def $ymm2, implicit-def $ymm3, implicit-def $ymm4, implicit-def $ymm5, implicit-def $ymm6, implicit-def $ymm7, implicit-def $ymm8, implicit-def $ymm9, implicit-def $ymm10, implicit-def $ymm11, implicit-def $ymm12, implicit-def $ymm13, implicit-def $ymm14, implicit-def $ymm15
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.avx.vzeroupper)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule301_id12066_at_idx19221
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule301_id12066_at_idx19221
+    ; SELECTED: MMX_EMMS
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.mmx.emms)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule302_id12285_at_idx19249
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule302_id12285_at_idx19249
+    ; SELECTED: FEMMS
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.mmx.femms)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule303_id12300_at_idx19277
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule303_id12300_at_idx19277
+    ; SELECTED: XEND
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xend)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule304_id12313_at_idx19305
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule304_id12313_at_idx19305
+    ; SELECTED: SAVEPREVSSP implicit-def $ssp, implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.saveprevssp)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule305_id12319_at_idx19333
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule305_id12319_at_idx19333
+    ; SELECTED: SETSSBSY implicit-def $ssp, implicit $ssp
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.setssbsy)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule306_id15730_at_idx19361
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule306_id15730_at_idx19361
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[INC16r:%[0-9]+]]:gr16 = INC16r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC16r]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule307_id15731_at_idx19429
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule307_id15731_at_idx19429
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[INC32r:%[0-9]+]]:gr32 = INC32r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC32r]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule308_id15762_at_idx19497
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule308_id15762_at_idx19497
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[INC64r:%[0-9]+]]:gr64 = INC64r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC64r]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule309_id15763_at_idx19565
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule309_id15763_at_idx19565
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[INC64r:%[0-9]+]]:gr64 = INC64r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC64r]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule310_id15824_at_idx19633
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule310_id15824_at_idx19633
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[AND16ri8_:%[0-9]+]]:gr16 = AND16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule311_id15825_at_idx19701
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule311_id15825_at_idx19701
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule312_id15826_at_idx19769
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule312_id15826_at_idx19769
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule313_id15827_at_idx19837
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule313_id15827_at_idx19837
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule314_id15755_at_idx19905
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule314_id15755_at_idx19905
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[IMUL16rri8_:%[0-9]+]]:gr16 = IMUL16rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL16rri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule315_id15756_at_idx19973
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule315_id15756_at_idx19973
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[IMUL32rri8_:%[0-9]+]]:gr32 = IMUL32rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL32rri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule316_id15771_at_idx20041
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule316_id15771_at_idx20041
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[IMUL64rri8_:%[0-9]+]]:gr64 = IMUL64rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL64rri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule317_id15772_at_idx20109
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule317_id15772_at_idx20109
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[IMUL64rri8_:%[0-9]+]]:gr64 = IMUL64rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL64rri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule318_id15794_at_idx20177
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule318_id15794_at_idx20177
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[OR16ri8_:%[0-9]+]]:gr16 = OR16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule319_id15795_at_idx20245
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule319_id15795_at_idx20245
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[OR32ri8_:%[0-9]+]]:gr32 = OR32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule320_id15796_at_idx20313
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule320_id15796_at_idx20313
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[OR64ri8_:%[0-9]+]]:gr64 = OR64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule321_id15797_at_idx20381
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule321_id15797_at_idx20381
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[OR64ri8_:%[0-9]+]]:gr64 = OR64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule322_id15741_at_idx20449
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule322_id15741_at_idx20449
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[SUB16ri8_:%[0-9]+]]:gr16 = SUB16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule323_id15742_at_idx20517
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule323_id15742_at_idx20517
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[SUB32ri8_:%[0-9]+]]:gr32 = SUB32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule324_id15767_at_idx20585
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule324_id15767_at_idx20585
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[SUB64ri8_:%[0-9]+]]:gr64 = SUB64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule325_id15768_at_idx20653
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule325_id15768_at_idx20653
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[SUB64ri8_:%[0-9]+]]:gr64 = SUB64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule326_id15809_at_idx20721
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule326_id15809_at_idx20721
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[XOR16ri8_:%[0-9]+]]:gr16 = XOR16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule327_id15810_at_idx20789
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule327_id15810_at_idx20789
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[XOR32ri8_:%[0-9]+]]:gr32 = XOR32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule328_id15811_at_idx20857
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule328_id15811_at_idx20857
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule329_id15812_at_idx20925
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule329_id15812_at_idx20925
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR64ri8_]]
+    %2:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule330_id13375_at_idx20993
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+  - { id: 4, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+  - { reg: '$xmm2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule330_id13375_at_idx20993
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSWWrr:%[0-9]+]]:vr128 = VPMACSWWrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSWWrr]]
+    %4:vecr(<8 x s16>) = COPY $xmm2
+    %3:vecr(<8 x s16>) = COPY $xmm1
+    %2:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_MUL %3, %4
+    %1:vecr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule331_id13376_at_idx21081
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+  - { id: 4, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+  - { reg: '$xmm2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule331_id13376_at_idx21081
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSDDrr:%[0-9]+]]:vr128 = VPMACSDDrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSDDrr]]
+    %4:vecr(<4 x s32>) = COPY $xmm2
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_MUL %3, %4
+    %1:vecr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule332_id18122_at_idx21169
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+  - { id: 4, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+  - { reg: '$xmm2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule332_id18122_at_idx21169
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSWWrr:%[0-9]+]]:vr128 = VPMACSWWrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSWWrr]]
+    %4:vecr(<8 x s16>) = COPY $xmm2
+    %3:vecr(<8 x s16>) = COPY $xmm1
+    %2:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_MUL %3, %4
+    %1:vecr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule333_id18123_at_idx21257
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+  - { id: 3, class: vecr }
+  - { id: 4, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%2' }
+  - { reg: '$xmm1', virtual-reg: '%3' }
+  - { reg: '$xmm2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1, $xmm2
+
+    ; SELECTED-LABEL: name: test_rule333_id18123_at_idx21257
+    ; SELECTED: liveins: $xmm0, $xmm1, $xmm2
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm2
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMACSDDrr:%[0-9]+]]:vr128 = VPMACSDDrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMACSDDrr]]
+    %4:vecr(<4 x s32>) = COPY $xmm2
+    %3:vecr(<4 x s32>) = COPY $xmm1
+    %2:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_MUL %3, %4
+    %1:vecr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule334_id15727_at_idx21345
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule334_id15727_at_idx21345
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[INC8r:%[0-9]+]]:gr8 = INC8r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC8r]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule335_id15728_at_idx21410
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule335_id15728_at_idx21410
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[INC16r:%[0-9]+]]:gr16 = INC16r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC16r]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule336_id15729_at_idx21475
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule336_id15729_at_idx21475
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[INC32r:%[0-9]+]]:gr32 = INC32r [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[INC32r]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule337_id15821_at_idx21540
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule337_id15821_at_idx21540
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND8ri]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule338_id15822_at_idx21605
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule338_id15822_at_idx21605
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[AND16ri8_:%[0-9]+]]:gr16 = AND16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule339_id15823_at_idx21670
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule339_id15823_at_idx21670
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule340_id621_at_idx21735
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule340_id621_at_idx21735
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule341_id622_at_idx21800
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule341_id622_at_idx21800
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule342_id623_at_idx21865
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule342_id623_at_idx21865
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule343_id624_at_idx21930
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule343_id624_at_idx21930
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SAR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule344_id597_at_idx21995
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule344_id597_at_idx21995
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule345_id598_at_idx22060
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule345_id598_at_idx22060
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule346_id599_at_idx22125
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule346_id599_at_idx22125
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule347_id600_at_idx22190
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule347_id600_at_idx22190
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SHR8r1_:%[0-9]+]]:gr8 = SHR8r1 [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHR8r1_]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule348_id15753_at_idx22255
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule348_id15753_at_idx22255
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[IMUL16rri8_:%[0-9]+]]:gr16 = IMUL16rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL16rri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule349_id15754_at_idx22320
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule349_id15754_at_idx22320
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[IMUL32rri8_:%[0-9]+]]:gr32 = IMUL32rri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL32rri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule350_id15791_at_idx22385
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule350_id15791_at_idx22385
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[OR8ri:%[0-9]+]]:gr8 = OR8ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR8ri]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule351_id15792_at_idx22450
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule351_id15792_at_idx22450
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[OR16ri8_:%[0-9]+]]:gr16 = OR16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule352_id15793_at_idx22515
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule352_id15793_at_idx22515
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[OR32ri8_:%[0-9]+]]:gr32 = OR32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule353_id577_at_idx22580
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule353_id577_at_idx22580
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule354_id578_at_idx22645
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule354_id578_at_idx22645
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule355_id579_at_idx22710
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule355_id579_at_idx22710
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule356_id580_at_idx22775
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule356_id580_at_idx22775
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule357_id15738_at_idx22840
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule357_id15738_at_idx22840
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SUB8ri:%[0-9]+]]:gr8 = SUB8ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB8ri]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule358_id15739_at_idx22905
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule358_id15739_at_idx22905
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[SUB16ri8_:%[0-9]+]]:gr16 = SUB16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule359_id15740_at_idx22970
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule359_id15740_at_idx22970
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[SUB32ri8_:%[0-9]+]]:gr32 = SUB32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule360_id15806_at_idx23035
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule360_id15806_at_idx23035
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[XOR8ri:%[0-9]+]]:gr8 = XOR8ri [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR8ri]]
+    %2:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_CONSTANT 1
+    %1:gpr(s8) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s8)
+
+...
+---
+name:            test_rule361_id15807_at_idx23100
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule361_id15807_at_idx23100
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[XOR16ri8_:%[0-9]+]]:gr16 = XOR16ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR16ri8_]]
+    %2:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_CONSTANT 1
+    %1:gpr(s16) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule362_id15808_at_idx23165
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule362_id15808_at_idx23165
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[XOR32ri8_:%[0-9]+]]:gr32 = XOR32ri8 [[COPY]], 1, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR32ri8_]]
+    %2:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule363_id14434_at_idx23230
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule363_id14434_at_idx23230
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s16) = G_BITCAST [[COPY]](<16 x s1>)
+    ; SELECTED: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT [[BITCAST]](s16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](s32)
+    %2:gpr(<16 x s1>) = COPY $ax
+    %0:gpr(s16) = G_BITCAST %2(<16 x s1>)
+    %1:gpr(s32) = G_ANYEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule364_id14436_at_idx23294
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule364_id14436_at_idx23294
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s8) = G_BITCAST [[COPY]](<8 x s1>)
+    ; SELECTED: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT [[BITCAST]](s8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](s32)
+    %2:gpr(<8 x s1>) = COPY $al
+    %0:gpr(s8) = G_BITCAST %2(<8 x s1>)
+    %1:gpr(s32) = G_ANYEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule365_id14433_at_idx23358
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule365_id14433_at_idx23358
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s16) = G_BITCAST [[COPY]](<16 x s1>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:gpr(s32) = G_ZEXT [[BITCAST]](s16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](s32)
+    %2:gpr(<16 x s1>) = COPY $ax
+    %0:gpr(s16) = G_BITCAST %2(<16 x s1>)
+    %1:gpr(s32) = G_ZEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule366_id14435_at_idx23420
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule366_id14435_at_idx23420
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s8) = G_BITCAST [[COPY]](<8 x s1>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:gpr(s32) = G_ZEXT [[BITCAST]](s8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](s32)
+    %2:gpr(<8 x s1>) = COPY $al
+    %0:gpr(s8) = G_BITCAST %2(<8 x s1>)
+    %1:gpr(s32) = G_ZEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule367_id16197_at_idx23484
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+  - { reg: '$ecx', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule367_id16197_at_idx23484
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[ANDN32rr:%[0-9]+]]:gr32 = ANDN32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDN32rr]]
+    %3:gpr(s32) = COPY $ecx
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule368_id16198_at_idx23568
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+  - { reg: '$rcx', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule368_id16198_at_idx23568
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[ANDN64rr:%[0-9]+]]:gr64 = ANDN64rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDN64rr]]
+    %3:gpr(s64) = COPY $rcx
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule369_id18384_at_idx23652
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%2' }
+  - { reg: '$ecx', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule369_id18384_at_idx23652
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[ANDN32rr:%[0-9]+]]:gr32 = ANDN32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDN32rr]]
+    %3:gpr(s32) = COPY $ecx
+    %2:gpr(s32) = COPY $eax
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule370_id18385_at_idx23736
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%2' }
+  - { reg: '$rcx', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule370_id18385_at_idx23736
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[ANDN64rr:%[0-9]+]]:gr64 = ANDN64rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDN64rr]]
+    %3:gpr(s64) = COPY $rcx
+    %2:gpr(s64) = COPY $rax
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule371_id22_at_idx23820
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule371_id22_at_idx23820
+    ; SELECTED: [[MOV64ImmSExti8_:%[0-9]+]]:gr64 = MOV64ImmSExti8 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV64ImmSExti8_]]
+    %0:gpr(s64) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule372_id869_at_idx23856
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule372_id869_at_idx23856
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s32) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s32)
+    %0:vecr(s32) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule373_id870_at_idx23891
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule373_id870_at_idx23891
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s32) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s32)
+    %0:vecr(s32) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule374_id871_at_idx23926
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule374_id871_at_idx23926
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s64)
+    %0:vecr(s64) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule375_id872_at_idx23961
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule375_id872_at_idx23961
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s64)
+    %0:vecr(s64) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule376_id873_at_idx23996
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule376_id873_at_idx23996
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s80) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s80)
+    %0:vecr(s80) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule377_id874_at_idx24029
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule377_id874_at_idx24029
+    ; SELECTED: [[C:%[0-9]+]]:vecr(s80) = G_FCONSTANT double 0.000000e+00
+    ; SELECTED: $noreg = PATCHABLE_RET [[C]](s80)
+    %0:vecr(s80) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule380_id1831_at_idx24132
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule380_id1831_at_idx24132
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDBrr:%[0-9]+]]:vr128 = VPADDBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule381_id1833_at_idx24175
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule381_id1833_at_idx24175
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDBrr:%[0-9]+]]:vr128 = VPADDBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule382_id1835_at_idx24218
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule382_id1835_at_idx24218
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDBYrr:%[0-9]+]]:vr256 = VPADDBYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBYrr]]
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule383_id1837_at_idx24261
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule383_id1837_at_idx24261
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDWrr:%[0-9]+]]:vr128 = VPADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule384_id1839_at_idx24304
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule384_id1839_at_idx24304
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDWrr:%[0-9]+]]:vr128 = VPADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule385_id1841_at_idx24347
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule385_id1841_at_idx24347
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDWYrr:%[0-9]+]]:vr256 = VPADDWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule386_id1843_at_idx24390
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule386_id1843_at_idx24390
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDDrr:%[0-9]+]]:vr128 = VPADDDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule387_id1845_at_idx24433
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule387_id1845_at_idx24433
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDDrr:%[0-9]+]]:vr128 = VPADDDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule388_id1847_at_idx24476
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule388_id1847_at_idx24476
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDDYrr:%[0-9]+]]:vr256 = VPADDDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule389_id1849_at_idx24519
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule389_id1849_at_idx24519
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDQrr:%[0-9]+]]:vr128 = VPADDQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule390_id1851_at_idx24562
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule390_id1851_at_idx24562
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDQrr:%[0-9]+]]:vr128 = VPADDQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule391_id1853_at_idx24605
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule391_id1853_at_idx24605
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDQYrr:%[0-9]+]]:vr256 = VPADDQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule392_id3957_at_idx24648
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule392_id3957_at_idx24648
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPADDQZrr:%[0-9]+]]:vr512 = VPADDQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule393_id3966_at_idx24691
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule393_id3966_at_idx24691
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDQYrr:%[0-9]+]]:vr256 = VPADDQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule394_id3975_at_idx24734
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule394_id3975_at_idx24734
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDQrr:%[0-9]+]]:vr128 = VPADDQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule395_id3984_at_idx24777
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule395_id3984_at_idx24777
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPADDDZrr:%[0-9]+]]:vr512 = VPADDDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule396_id3993_at_idx24820
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule396_id3993_at_idx24820
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDDYrr:%[0-9]+]]:vr256 = VPADDDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule397_id4002_at_idx24863
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule397_id4002_at_idx24863
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDDrr:%[0-9]+]]:vr128 = VPADDDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule398_id4011_at_idx24906
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule398_id4011_at_idx24906
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPADDWZrr:%[0-9]+]]:vr512 = VPADDWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule399_id4017_at_idx24949
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule399_id4017_at_idx24949
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDWYrr:%[0-9]+]]:vr256 = VPADDWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule400_id4023_at_idx24992
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule400_id4023_at_idx24992
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDWrr:%[0-9]+]]:vr128 = VPADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule401_id4029_at_idx25035
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule401_id4029_at_idx25035
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPADDBZrr:%[0-9]+]]:vr512 = VPADDBZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBZrr]]
+    %2:vecr(<64 x s8>) = COPY $zmm1
+    %1:vecr(<64 x s8>) = COPY $zmm0
+    %0:vecr(<64 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule402_id4035_at_idx25078
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule402_id4035_at_idx25078
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPADDBYrr:%[0-9]+]]:vr256 = VPADDBYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBYrr]]
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule403_id4041_at_idx25121
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule403_id4041_at_idx25121
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPADDBrr:%[0-9]+]]:vr128 = VPADDBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule404_id15721_at_idx25164
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule404_id15721_at_idx25164
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD8rr]]
+    %2:gpr(s8) = COPY $cl
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule405_id15722_at_idx25208
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule405_id15722_at_idx25208
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule406_id15723_at_idx25252
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule406_id15723_at_idx25252
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule407_id15761_at_idx25296
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule407_id15761_at_idx25296
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule408_id1571_at_idx25340
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule408_id1571_at_idx25340
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPANDrr:%[0-9]+]]:vr128 = VPANDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule409_id1573_at_idx25383
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule409_id1573_at_idx25383
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPANDrr:%[0-9]+]]:vr128 = VPANDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule410_id1575_at_idx25426
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule410_id1575_at_idx25426
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPANDYrr:%[0-9]+]]:vr256 = VPANDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule411_id3743_at_idx25469
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule411_id3743_at_idx25469
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(<8 x s1>) = G_AND [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule412_id3744_at_idx25512
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule412_id3744_at_idx25512
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(<16 x s1>) = G_AND [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<16 x s1>)
+    %2:gpr(<16 x s1>) = COPY $cx
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:gpr(<16 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s1>)
+
+...
+---
+name:            test_rule413_id3745_at_idx25555
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule413_id3745_at_idx25555
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:vecr(<32 x s1>) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<32 x s1>)
+    %1:vecr(<32 x s1>) = IMPLICIT_DEF
+    %2:vecr(<32 x s1>) = IMPLICIT_DEF
+    %0:vecr(<32 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s1>)
+
+...
+---
+name:            test_rule414_id3746_at_idx25598
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule414_id3746_at_idx25598
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:vecr(<64 x s1>) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<64 x s1>)
+    %1:vecr(<64 x s1>) = IMPLICIT_DEF
+    %2:vecr(<64 x s1>) = IMPLICIT_DEF
+    %0:vecr(<64 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<64 x s1>)
+
+...
+---
+name:            test_rule415_id5010_at_idx25641
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule415_id5010_at_idx25641
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPANDQZrr:%[0-9]+]]:vr512 = VPANDQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule416_id5019_at_idx25684
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule416_id5019_at_idx25684
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPANDYrr:%[0-9]+]]:vr256 = VPANDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule417_id5028_at_idx25727
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule417_id5028_at_idx25727
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPANDrr:%[0-9]+]]:vr128 = VPANDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule418_id13527_at_idx25770
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule418_id13527_at_idx25770
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPANDYrr:%[0-9]+]]:vr256 = VPANDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPANDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule419_id14153_at_idx25813
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule419_id14153_at_idx25813
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[ANDPSrr:%[0-9]+]]:vr128 = ANDPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: [[COPY2:%[0-9]+]]:fr128 = COPY [[ANDPSrr]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY2]]
+    %2:vecr(s128) = COPY $xmm1
+    %1:vecr(s128) = COPY $xmm0
+    %0:vecr(s128) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule420_id14473_at_idx25917
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule420_id14473_at_idx25917
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(<8 x s1>) = G_AND [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule421_id14474_at_idx26023
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule421_id14474_at_idx26023
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(s1) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](s1)
+    %1:gpr(s1) = IMPLICIT_DEF
+    %2:gpr(s1) = IMPLICIT_DEF
+    %0:gpr(s1) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s1)
+
+...
+---
+name:            test_rule422_id14475_at_idx26127
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule422_id14475_at_idx26127
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(<2 x s1>) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<2 x s1>)
+    %1:gpr(<2 x s1>) = IMPLICIT_DEF
+    %2:gpr(<2 x s1>) = IMPLICIT_DEF
+    %0:gpr(<2 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s1>)
+
+...
+---
+name:            test_rule423_id14476_at_idx26231
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule423_id14476_at_idx26231
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:gpr(<4 x s1>) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<4 x s1>)
+    %1:gpr(<4 x s1>) = IMPLICIT_DEF
+    %2:gpr(<4 x s1>) = IMPLICIT_DEF
+    %0:gpr(<4 x s1>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s1>)
+
+...
+---
+name:            test_rule424_id15813_at_idx26335
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule424_id15813_at_idx26335
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND8rr]]
+    %2:gpr(s8) = COPY $cl
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule425_id15814_at_idx26379
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule425_id15814_at_idx26379
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[AND16rr:%[0-9]+]]:gr16 = AND16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule426_id15815_at_idx26423
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule426_id15815_at_idx26423
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule427_id15816_at_idx26467
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule427_id15816_at_idx26467
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule428_id2781_at_idx26511
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule428_id2781_at_idx26511
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRAVDrr:%[0-9]+]]:vr128 = VPSRAVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule429_id2783_at_idx26554
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule429_id2783_at_idx26554
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRAVDYrr:%[0-9]+]]:vr256 = VPSRAVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule430_id6566_at_idx26597
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule430_id6566_at_idx26597
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRAVDZrr:%[0-9]+]]:vr512 = VPSRAVDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule431_id6575_at_idx26640
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule431_id6575_at_idx26640
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRAVDYrr:%[0-9]+]]:vr256 = VPSRAVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule432_id6584_at_idx26683
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule432_id6584_at_idx26683
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRAVDrr:%[0-9]+]]:vr128 = VPSRAVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule433_id6593_at_idx26726
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule433_id6593_at_idx26726
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRAVQZrr:%[0-9]+]]:vr512 = VPSRAVQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule434_id6602_at_idx26769
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule434_id6602_at_idx26769
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRAVQZ256rr:%[0-9]+]]:vr256x = VPSRAVQZ256rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVQZ256rr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule435_id6611_at_idx26812
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule435_id6611_at_idx26812
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VPSRAVQZ128rr:%[0-9]+]]:vr128x = VPSRAVQZ128rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVQZ128rr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule436_id6620_at_idx26855
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule436_id6620_at_idx26855
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRAVWZrr:%[0-9]+]]:vr512 = VPSRAVWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule437_id6626_at_idx26898
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule437_id6626_at_idx26898
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRAVWZ256rr:%[0-9]+]]:vr256x = VPSRAVWZ256rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVWZ256rr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule438_id6632_at_idx26941
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule438_id6632_at_idx26941
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VPSRAVWZ128rr:%[0-9]+]]:vr128x = VPSRAVWZ128rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRAVWZ128rr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule439_id722_at_idx26984
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule439_id722_at_idx26984
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](s32)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %2:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule440_id723_at_idx27030
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule440_id723_at_idx27030
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](s64)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %2:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule441_id724_at_idx27076
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule441_id724_at_idx27076
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FADD:%[0-9]+]]:vecr(s80) = G_FADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](s80)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %2:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule442_id1595_at_idx27120
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule442_id1595_at_idx27120
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPSrr:%[0-9]+]]:vr128 = VADDPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule443_id1597_at_idx27163
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule443_id1597_at_idx27163
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPDrr:%[0-9]+]]:vr128 = VADDPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule444_id1599_at_idx27206
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule444_id1599_at_idx27206
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VADDPSYrr:%[0-9]+]]:vr256 = VADDPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule445_id1601_at_idx27249
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule445_id1601_at_idx27249
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VADDPDYrr:%[0-9]+]]:vr256 = VADDPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule446_id1603_at_idx27292
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule446_id1603_at_idx27292
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPSrr:%[0-9]+]]:vr128 = VADDPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule447_id1605_at_idx27335
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule447_id1605_at_idx27335
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPDrr:%[0-9]+]]:vr128 = VADDPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule454_id5342_at_idx27636
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule454_id5342_at_idx27636
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VADDPSZrr:%[0-9]+]]:vr512 = VADDPSZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule455_id5351_at_idx27679
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule455_id5351_at_idx27679
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VADDPDZrr:%[0-9]+]]:vr512 = VADDPDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule456_id5360_at_idx27722
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule456_id5360_at_idx27722
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPSrr:%[0-9]+]]:vr128 = VADDPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule457_id5369_at_idx27765
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule457_id5369_at_idx27765
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VADDPSYrr:%[0-9]+]]:vr256 = VADDPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule458_id5378_at_idx27808
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule458_id5378_at_idx27808
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VADDPDrr:%[0-9]+]]:vr128 = VADDPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule459_id5387_at_idx27851
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule459_id5387_at_idx27851
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VADDPDYrr:%[0-9]+]]:vr256 = VADDPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule460_id731_at_idx27894
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule460_id731_at_idx27894
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIV]](s32)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %2:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule461_id732_at_idx27940
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule461_id732_at_idx27940
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FDIV:%[0-9]+]]:vecr(s64) = G_FDIV [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIV]](s64)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %2:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule462_id733_at_idx27986
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule462_id733_at_idx27986
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FDIV:%[0-9]+]]:vecr(s80) = G_FDIV [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIV]](s80)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %2:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule463_id1655_at_idx28030
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule463_id1655_at_idx28030
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPSrr:%[0-9]+]]:vr128 = VDIVPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule464_id1657_at_idx28073
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule464_id1657_at_idx28073
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPDrr:%[0-9]+]]:vr128 = VDIVPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule465_id1659_at_idx28116
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule465_id1659_at_idx28116
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VDIVPSYrr:%[0-9]+]]:vr256 = VDIVPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule466_id1661_at_idx28159
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule466_id1661_at_idx28159
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VDIVPDYrr:%[0-9]+]]:vr256 = VDIVPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule467_id1663_at_idx28202
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule467_id1663_at_idx28202
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPSrr:%[0-9]+]]:vr128 = VDIVPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule468_id1665_at_idx28245
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule468_id1665_at_idx28245
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPDrr:%[0-9]+]]:vr128 = VDIVPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule475_id5522_at_idx28546
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule475_id5522_at_idx28546
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VDIVPSZrr:%[0-9]+]]:vr512 = VDIVPSZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule476_id5531_at_idx28589
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule476_id5531_at_idx28589
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VDIVPDZrr:%[0-9]+]]:vr512 = VDIVPDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule477_id5540_at_idx28632
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule477_id5540_at_idx28632
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPSrr:%[0-9]+]]:vr128 = VDIVPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule478_id5549_at_idx28675
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule478_id5549_at_idx28675
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VDIVPSYrr:%[0-9]+]]:vr256 = VDIVPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule479_id5558_at_idx28718
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule479_id5558_at_idx28718
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VDIVPDrr:%[0-9]+]]:vr128 = VDIVPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule480_id5567_at_idx28761
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule480_id5567_at_idx28761
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VDIVPDYrr:%[0-9]+]]:vr256 = VDIVPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule481_id728_at_idx28804
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule481_id728_at_idx28804
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](s32)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %2:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule482_id729_at_idx28850
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule482_id729_at_idx28850
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:vecr(s64) = G_FMUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](s64)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %2:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule483_id730_at_idx28896
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule483_id730_at_idx28896
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:vecr(s80) = G_FMUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](s80)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %2:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule484_id1615_at_idx28940
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule484_id1615_at_idx28940
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPSrr:%[0-9]+]]:vr128 = VMULPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule485_id1617_at_idx28983
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule485_id1617_at_idx28983
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPDrr:%[0-9]+]]:vr128 = VMULPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule486_id1619_at_idx29026
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule486_id1619_at_idx29026
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VMULPSYrr:%[0-9]+]]:vr256 = VMULPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule487_id1621_at_idx29069
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule487_id1621_at_idx29069
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VMULPDYrr:%[0-9]+]]:vr256 = VMULPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule488_id1623_at_idx29112
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule488_id1623_at_idx29112
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPSrr:%[0-9]+]]:vr128 = VMULPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule489_id1625_at_idx29155
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule489_id1625_at_idx29155
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPDrr:%[0-9]+]]:vr128 = VMULPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule496_id5402_at_idx29456
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule496_id5402_at_idx29456
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VMULPSZrr:%[0-9]+]]:vr512 = VMULPSZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule497_id5411_at_idx29499
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule497_id5411_at_idx29499
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VMULPDZrr:%[0-9]+]]:vr512 = VMULPDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule498_id5420_at_idx29542
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule498_id5420_at_idx29542
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPSrr:%[0-9]+]]:vr128 = VMULPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule499_id5429_at_idx29585
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule499_id5429_at_idx29585
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VMULPSYrr:%[0-9]+]]:vr256 = VMULPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule500_id5438_at_idx29628
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule500_id5438_at_idx29628
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VMULPDrr:%[0-9]+]]:vr128 = VMULPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule501_id5447_at_idx29671
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule501_id5447_at_idx29671
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VMULPDYrr:%[0-9]+]]:vr256 = VMULPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule502_id725_at_idx29714
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule502_id725_at_idx29714
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](s32)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %2:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule503_id726_at_idx29760
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule503_id726_at_idx29760
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FSUB:%[0-9]+]]:vecr(s64) = G_FSUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](s64)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %2:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule504_id727_at_idx29806
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule504_id727_at_idx29806
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FSUB:%[0-9]+]]:vecr(s80) = G_FSUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](s80)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %2:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule505_id1635_at_idx29850
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule505_id1635_at_idx29850
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPSrr:%[0-9]+]]:vr128 = VSUBPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule506_id1637_at_idx29893
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule506_id1637_at_idx29893
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPDrr:%[0-9]+]]:vr128 = VSUBPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule507_id1639_at_idx29936
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule507_id1639_at_idx29936
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VSUBPSYrr:%[0-9]+]]:vr256 = VSUBPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule508_id1641_at_idx29979
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule508_id1641_at_idx29979
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VSUBPDYrr:%[0-9]+]]:vr256 = VSUBPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule509_id1643_at_idx30022
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule509_id1643_at_idx30022
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPSrr:%[0-9]+]]:vr128 = VSUBPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule510_id1645_at_idx30065
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule510_id1645_at_idx30065
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPDrr:%[0-9]+]]:vr128 = VSUBPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule517_id5462_at_idx30366
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule517_id5462_at_idx30366
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VSUBPSZrr:%[0-9]+]]:vr512 = VSUBPSZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule518_id5471_at_idx30409
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule518_id5471_at_idx30409
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VSUBPDZrr:%[0-9]+]]:vr512 = VSUBPDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule519_id5480_at_idx30452
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule519_id5480_at_idx30452
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPSrr:%[0-9]+]]:vr128 = VSUBPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule520_id5489_at_idx30495
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule520_id5489_at_idx30495
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VSUBPSYrr:%[0-9]+]]:vr256 = VSUBPSYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPSYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule521_id5498_at_idx30538
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule521_id5498_at_idx30538
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VSUBPDrr:%[0-9]+]]:vr128 = VSUBPDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule522_id5507_at_idx30581
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule522_id5507_at_idx30581
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VSUBPDYrr:%[0-9]+]]:vr256 = VSUBPDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBPDYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule523_id2773_at_idx30624
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule523_id2773_at_idx30624
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRLVDrr:%[0-9]+]]:vr128 = VPSRLVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule524_id2775_at_idx30667
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule524_id2775_at_idx30667
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRLVDYrr:%[0-9]+]]:vr256 = VPSRLVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule525_id2777_at_idx30710
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule525_id2777_at_idx30710
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRLVQrr:%[0-9]+]]:vr128 = VPSRLVQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule526_id2779_at_idx30753
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule526_id2779_at_idx30753
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRLVQYrr:%[0-9]+]]:vr256 = VPSRLVQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule527_id6638_at_idx30796
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule527_id6638_at_idx30796
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRLVDZrr:%[0-9]+]]:vr512 = VPSRLVDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule528_id6647_at_idx30839
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule528_id6647_at_idx30839
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRLVDYrr:%[0-9]+]]:vr256 = VPSRLVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule529_id6656_at_idx30882
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule529_id6656_at_idx30882
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRLVDrr:%[0-9]+]]:vr128 = VPSRLVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule530_id6665_at_idx30925
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule530_id6665_at_idx30925
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRLVQZrr:%[0-9]+]]:vr512 = VPSRLVQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule531_id6674_at_idx30968
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule531_id6674_at_idx30968
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRLVQYrr:%[0-9]+]]:vr256 = VPSRLVQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule532_id6683_at_idx31011
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule532_id6683_at_idx31011
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSRLVQrr:%[0-9]+]]:vr128 = VPSRLVQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule533_id6692_at_idx31054
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule533_id6692_at_idx31054
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSRLVWZrr:%[0-9]+]]:vr512 = VPSRLVWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule534_id6698_at_idx31097
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule534_id6698_at_idx31097
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSRLVWZ256rr:%[0-9]+]]:vr256x = VPSRLVWZ256rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVWZ256rr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule535_id6704_at_idx31140
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule535_id6704_at_idx31140
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VPSRLVWZ128rr:%[0-9]+]]:vr128x = VPSRLVWZ128rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSRLVWZ128rr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule536_id1879_at_idx31183
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule536_id1879_at_idx31183
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule537_id1881_at_idx31226
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule537_id1881_at_idx31226
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule538_id1883_at_idx31269
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule538_id1883_at_idx31269
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule539_id2537_at_idx31312
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule539_id2537_at_idx31312
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule540_id2541_at_idx31355
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule540_id2541_at_idx31355
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule541_id2545_at_idx31398
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule541_id2545_at_idx31398
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule542_id4281_at_idx31441
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule542_id4281_at_idx31441
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMULLDZrr:%[0-9]+]]:vr512 = VPMULLDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule543_id4290_at_idx31484
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule543_id4290_at_idx31484
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule544_id4299_at_idx31527
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule544_id4299_at_idx31527
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule545_id4308_at_idx31570
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule545_id4308_at_idx31570
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMULLWZrr:%[0-9]+]]:vr512 = VPMULLWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule546_id4314_at_idx31613
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule546_id4314_at_idx31613
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule547_id4320_at_idx31656
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule547_id4320_at_idx31656
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule548_id4326_at_idx31699
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule548_id4326_at_idx31699
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMULLQZrr:%[0-9]+]]:vr512 = VPMULLQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule549_id4335_at_idx31742
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule549_id4335_at_idx31742
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMULLQZ256rr:%[0-9]+]]:vr256x = VPMULLQZ256rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLQZ256rr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule550_id4344_at_idx31785
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule550_id4344_at_idx31785
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VPMULLQZ128rr:%[0-9]+]]:vr128x = VPMULLQZ128rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMULLQZ128rr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule551_id15749_at_idx31828
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule551_id15749_at_idx31828
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule552_id15750_at_idx31872
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule552_id15750_at_idx31872
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule553_id15769_at_idx31916
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule553_id15769_at_idx31916
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[IMUL64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule554_id1577_at_idx31960
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule554_id1577_at_idx31960
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPORrr:%[0-9]+]]:vr128 = VPORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule555_id1579_at_idx32003
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule555_id1579_at_idx32003
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPORrr:%[0-9]+]]:vr128 = VPORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule556_id1581_at_idx32046
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule556_id1581_at_idx32046
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPORYrr:%[0-9]+]]:vr256 = VPORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule557_id3747_at_idx32089
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule557_id3747_at_idx32089
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(<8 x s1>) = G_OR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule558_id3748_at_idx32132
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule558_id3748_at_idx32132
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(<16 x s1>) = G_OR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<16 x s1>)
+    %2:gpr(<16 x s1>) = COPY $cx
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:gpr(<16 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s1>)
+
+...
+---
+name:            test_rule559_id3749_at_idx32175
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule559_id3749_at_idx32175
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:vecr(<32 x s1>) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<32 x s1>)
+    %1:vecr(<32 x s1>) = IMPLICIT_DEF
+    %2:vecr(<32 x s1>) = IMPLICIT_DEF
+    %0:vecr(<32 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s1>)
+
+...
+---
+name:            test_rule560_id3750_at_idx32218
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule560_id3750_at_idx32218
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:vecr(<64 x s1>) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<64 x s1>)
+    %1:vecr(<64 x s1>) = IMPLICIT_DEF
+    %2:vecr(<64 x s1>) = IMPLICIT_DEF
+    %0:vecr(<64 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<64 x s1>)
+
+...
+---
+name:            test_rule561_id5058_at_idx32261
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule561_id5058_at_idx32261
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPORQZrr:%[0-9]+]]:vr512 = VPORQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule562_id5067_at_idx32304
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule562_id5067_at_idx32304
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPORYrr:%[0-9]+]]:vr256 = VPORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule563_id5076_at_idx32347
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule563_id5076_at_idx32347
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPORrr:%[0-9]+]]:vr128 = VPORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule564_id13528_at_idx32390
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule564_id13528_at_idx32390
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPORYrr:%[0-9]+]]:vr256 = VPORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule565_id14156_at_idx32433
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule565_id14156_at_idx32433
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[ORPSrr:%[0-9]+]]:vr128 = ORPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: [[COPY2:%[0-9]+]]:fr128 = COPY [[ORPSrr]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY2]]
+    %2:vecr(s128) = COPY $xmm1
+    %1:vecr(s128) = COPY $xmm0
+    %0:vecr(s128) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule566_id14481_at_idx32537
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule566_id14481_at_idx32537
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(<8 x s1>) = G_OR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule567_id14482_at_idx32643
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule567_id14482_at_idx32643
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(s1) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](s1)
+    %1:gpr(s1) = IMPLICIT_DEF
+    %2:gpr(s1) = IMPLICIT_DEF
+    %0:gpr(s1) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s1)
+
+...
+---
+name:            test_rule568_id14483_at_idx32747
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule568_id14483_at_idx32747
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(<2 x s1>) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<2 x s1>)
+    %1:gpr(<2 x s1>) = IMPLICIT_DEF
+    %2:gpr(<2 x s1>) = IMPLICIT_DEF
+    %0:gpr(<2 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s1>)
+
+...
+---
+name:            test_rule569_id14484_at_idx32851
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule569_id14484_at_idx32851
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:gpr(<4 x s1>) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<4 x s1>)
+    %1:gpr(<4 x s1>) = IMPLICIT_DEF
+    %2:gpr(<4 x s1>) = IMPLICIT_DEF
+    %0:gpr(<4 x s1>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s1>)
+
+...
+---
+name:            test_rule570_id15783_at_idx32955
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule570_id15783_at_idx32955
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR8rr]]
+    %2:gpr(s8) = COPY $cl
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule571_id15784_at_idx32999
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule571_id15784_at_idx32999
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[OR16rr:%[0-9]+]]:gr16 = OR16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule572_id15785_at_idx33043
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule572_id15785_at_idx33043
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule573_id15786_at_idx33087
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule573_id15786_at_idx33087
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[OR64rr:%[0-9]+]]:gr64 = OR64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule574_id2765_at_idx33131
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule574_id2765_at_idx33131
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSLLVDrr:%[0-9]+]]:vr128 = VPSLLVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule575_id2767_at_idx33174
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule575_id2767_at_idx33174
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSLLVDYrr:%[0-9]+]]:vr256 = VPSLLVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule576_id2769_at_idx33217
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule576_id2769_at_idx33217
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSLLVQrr:%[0-9]+]]:vr128 = VPSLLVQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule577_id2771_at_idx33260
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule577_id2771_at_idx33260
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSLLVQYrr:%[0-9]+]]:vr256 = VPSLLVQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule578_id6494_at_idx33303
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule578_id6494_at_idx33303
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSLLVDZrr:%[0-9]+]]:vr512 = VPSLLVDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule579_id6503_at_idx33346
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule579_id6503_at_idx33346
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSLLVDYrr:%[0-9]+]]:vr256 = VPSLLVDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule580_id6512_at_idx33389
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule580_id6512_at_idx33389
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSLLVDrr:%[0-9]+]]:vr128 = VPSLLVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule581_id6521_at_idx33432
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule581_id6521_at_idx33432
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSLLVQZrr:%[0-9]+]]:vr512 = VPSLLVQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule582_id6530_at_idx33475
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule582_id6530_at_idx33475
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSLLVQYrr:%[0-9]+]]:vr256 = VPSLLVQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule583_id6539_at_idx33518
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule583_id6539_at_idx33518
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSLLVQrr:%[0-9]+]]:vr128 = VPSLLVQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule584_id6548_at_idx33561
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule584_id6548_at_idx33561
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSLLVWZrr:%[0-9]+]]:vr512 = VPSLLVWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule585_id6554_at_idx33604
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule585_id6554_at_idx33604
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSLLVWZ256rr:%[0-9]+]]:vr256x = VPSLLVWZ256rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVWZ256rr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule586_id6560_at_idx33647
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule586_id6560_at_idx33647
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VPSLLVWZ128rr:%[0-9]+]]:vr128x = VPSLLVWZ128rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSLLVWZ128rr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule587_id1897_at_idx33690
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule587_id1897_at_idx33690
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBBrr:%[0-9]+]]:vr128 = VPSUBBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule588_id1899_at_idx33733
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule588_id1899_at_idx33733
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBBrr:%[0-9]+]]:vr128 = VPSUBBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule589_id1901_at_idx33776
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule589_id1901_at_idx33776
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBBYrr:%[0-9]+]]:vr256 = VPSUBBYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBYrr]]
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule590_id1903_at_idx33819
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule590_id1903_at_idx33819
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBWrr:%[0-9]+]]:vr128 = VPSUBWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule591_id1905_at_idx33862
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule591_id1905_at_idx33862
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBWrr:%[0-9]+]]:vr128 = VPSUBWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule592_id1907_at_idx33905
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule592_id1907_at_idx33905
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBWYrr:%[0-9]+]]:vr256 = VPSUBWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule593_id1909_at_idx33948
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule593_id1909_at_idx33948
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBDrr:%[0-9]+]]:vr128 = VPSUBDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule594_id1911_at_idx33991
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule594_id1911_at_idx33991
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBDrr:%[0-9]+]]:vr128 = VPSUBDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule595_id1913_at_idx34034
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule595_id1913_at_idx34034
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBDYrr:%[0-9]+]]:vr256 = VPSUBDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule596_id1915_at_idx34077
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule596_id1915_at_idx34077
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBQrr:%[0-9]+]]:vr128 = VPSUBQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule597_id1917_at_idx34120
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule597_id1917_at_idx34120
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBQrr:%[0-9]+]]:vr128 = VPSUBQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule598_id1919_at_idx34163
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule598_id1919_at_idx34163
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBQYrr:%[0-9]+]]:vr256 = VPSUBQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule599_id4047_at_idx34206
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule599_id4047_at_idx34206
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule600_id4056_at_idx34249
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule600_id4056_at_idx34249
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBQYrr:%[0-9]+]]:vr256 = VPSUBQYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule601_id4065_at_idx34292
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule601_id4065_at_idx34292
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBQrr:%[0-9]+]]:vr128 = VPSUBQrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBQrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule602_id4074_at_idx34335
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule602_id4074_at_idx34335
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDZrr]]
+    %2:vecr(<16 x s32>) = COPY $zmm1
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule603_id4083_at_idx34378
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule603_id4083_at_idx34378
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBDYrr:%[0-9]+]]:vr256 = VPSUBDYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDYrr]]
+    %2:vecr(<8 x s32>) = COPY $ymm1
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule604_id4092_at_idx34421
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule604_id4092_at_idx34421
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBDrr:%[0-9]+]]:vr128 = VPSUBDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBDrr]]
+    %2:vecr(<4 x s32>) = COPY $xmm1
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule605_id4101_at_idx34464
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule605_id4101_at_idx34464
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWZrr]]
+    %2:vecr(<32 x s16>) = COPY $zmm1
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule606_id4107_at_idx34507
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule606_id4107_at_idx34507
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBWYrr:%[0-9]+]]:vr256 = VPSUBWYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWYrr]]
+    %2:vecr(<16 x s16>) = COPY $ymm1
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule607_id4113_at_idx34550
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule607_id4113_at_idx34550
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBWrr:%[0-9]+]]:vr128 = VPSUBWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBWrr]]
+    %2:vecr(<8 x s16>) = COPY $xmm1
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule608_id4119_at_idx34593
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule608_id4119_at_idx34593
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBZrr]]
+    %2:vecr(<64 x s8>) = COPY $zmm1
+    %1:vecr(<64 x s8>) = COPY $zmm0
+    %0:vecr(<64 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule609_id4125_at_idx34636
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule609_id4125_at_idx34636
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPSUBBYrr:%[0-9]+]]:vr256 = VPSUBBYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBYrr]]
+    %2:vecr(<32 x s8>) = COPY $ymm1
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule610_id4131_at_idx34679
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule610_id4131_at_idx34679
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPSUBBrr:%[0-9]+]]:vr128 = VPSUBBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPSUBBrr]]
+    %2:vecr(<16 x s8>) = COPY $xmm1
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule611_id15732_at_idx34722
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule611_id15732_at_idx34722
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[SUB8rr:%[0-9]+]]:gr8 = SUB8rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB8rr]]
+    %2:gpr(s8) = COPY $cl
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule612_id15733_at_idx34766
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule612_id15733_at_idx34766
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[SUB16rr:%[0-9]+]]:gr16 = SUB16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule613_id15734_at_idx34810
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule613_id15734_at_idx34810
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule614_id15765_at_idx34854
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule614_id15765_at_idx34854
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule615_id1583_at_idx34898
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule615_id1583_at_idx34898
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPXORrr:%[0-9]+]]:vr128 = VPXORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule616_id1585_at_idx34941
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule616_id1585_at_idx34941
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPXORrr:%[0-9]+]]:vr128 = VPXORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule617_id1587_at_idx34984
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule617_id1587_at_idx34984
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPXORYrr:%[0-9]+]]:vr256 = VPXORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule618_id3755_at_idx35027
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule618_id3755_at_idx35027
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(<8 x s1>) = G_XOR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule619_id3756_at_idx35070
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule619_id3756_at_idx35070
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(<16 x s1>) = G_XOR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<16 x s1>)
+    %2:gpr(<16 x s1>) = COPY $cx
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:gpr(<16 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s1>)
+
+...
+---
+name:            test_rule620_id3757_at_idx35113
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule620_id3757_at_idx35113
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:vecr(<32 x s1>) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<32 x s1>)
+    %1:vecr(<32 x s1>) = IMPLICIT_DEF
+    %2:vecr(<32 x s1>) = IMPLICIT_DEF
+    %0:vecr(<32 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<32 x s1>)
+
+...
+---
+name:            test_rule621_id3758_at_idx35156
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule621_id3758_at_idx35156
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:vecr(<64 x s1>) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<64 x s1>)
+    %1:vecr(<64 x s1>) = IMPLICIT_DEF
+    %2:vecr(<64 x s1>) = IMPLICIT_DEF
+    %0:vecr(<64 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<64 x s1>)
+
+...
+---
+name:            test_rule622_id5106_at_idx35199
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+  - { reg: '$zmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0, $zmm1
+
+    ; SELECTED-LABEL: name: test_rule622_id5106_at_idx35199
+    ; SELECTED: liveins: $zmm0, $zmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPXORQZrr:%[0-9]+]]:vr512 = VPXORQZrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORQZrr]]
+    %2:vecr(<8 x s64>) = COPY $zmm1
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule623_id5115_at_idx35242
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule623_id5115_at_idx35242
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPXORYrr:%[0-9]+]]:vr256 = VPXORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule624_id5124_at_idx35285
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule624_id5124_at_idx35285
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VPXORrr:%[0-9]+]]:vr128 = VPXORrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORrr]]
+    %2:vecr(<2 x s64>) = COPY $xmm1
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule625_id13529_at_idx35328
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+  - { reg: '$ymm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0, $ymm1
+
+    ; SELECTED-LABEL: name: test_rule625_id13529_at_idx35328
+    ; SELECTED: liveins: $ymm0, $ymm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPXORYrr:%[0-9]+]]:vr256 = VPXORYrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPXORYrr]]
+    %2:vecr(<4 x s64>) = COPY $ymm1
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule626_id14159_at_idx35371
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+  - { reg: '$xmm1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0, $xmm1
+
+    ; SELECTED-LABEL: name: test_rule626_id14159_at_idx35371
+    ; SELECTED: liveins: $xmm0, $xmm1
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
+    ; SELECTED: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[XORPSrr:%[0-9]+]]:vr128 = XORPSrr [[COPY1]], [[COPY]]
+    ; SELECTED: [[COPY2:%[0-9]+]]:fr128 = COPY [[XORPSrr]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY2]]
+    %2:vecr(s128) = COPY $xmm1
+    %1:vecr(s128) = COPY $xmm0
+    %0:vecr(s128) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule627_id14489_at_idx35475
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule627_id14489_at_idx35475
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(<8 x s1>) = G_XOR [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<8 x s1>)
+    %2:gpr(<8 x s1>) = COPY $cl
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:gpr(<8 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s1>)
+
+...
+---
+name:            test_rule628_id14490_at_idx35581
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule628_id14490_at_idx35581
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(s1) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(s1) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](s1)
+    %1:gpr(s1) = IMPLICIT_DEF
+    %2:gpr(s1) = IMPLICIT_DEF
+    %0:gpr(s1) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s1)
+
+...
+---
+name:            test_rule629_id14491_at_idx35685
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule629_id14491_at_idx35685
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(<2 x s1>) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<2 x s1>)
+    %1:gpr(<2 x s1>) = IMPLICIT_DEF
+    %2:gpr(<2 x s1>) = IMPLICIT_DEF
+    %0:gpr(<2 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s1>)
+
+...
+---
+name:            test_rule630_id14492_at_idx35789
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule630_id14492_at_idx35789
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:gpr(<4 x s1>) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<4 x s1>)
+    %1:gpr(<4 x s1>) = IMPLICIT_DEF
+    %2:gpr(<4 x s1>) = IMPLICIT_DEF
+    %0:gpr(<4 x s1>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s1>)
+
+...
+---
+name:            test_rule631_id15798_at_idx35893
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+  - { reg: '$cl', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $al, $cl
+
+    ; SELECTED-LABEL: name: test_rule631_id15798_at_idx35893
+    ; SELECTED: liveins: $al, $cl
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $cl
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[XOR8rr:%[0-9]+]]:gr8 = XOR8rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR8rr]]
+    %2:gpr(s8) = COPY $cl
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s8) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule632_id15799_at_idx35937
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+  - { reg: '$cx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $ax, $cx
+
+    ; SELECTED-LABEL: name: test_rule632_id15799_at_idx35937
+    ; SELECTED: liveins: $ax, $cx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $cx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[XOR16rr:%[0-9]+]]:gr16 = XOR16rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR16rr]]
+    %2:gpr(s16) = COPY $cx
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule633_id15800_at_idx35981
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+  - { reg: '$ecx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $eax, $ecx
+
+    ; SELECTED-LABEL: name: test_rule633_id15800_at_idx35981
+    ; SELECTED: liveins: $eax, $ecx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR32rr]]
+    %2:gpr(s32) = COPY $ecx
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule634_id15801_at_idx36025
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+  - { reg: '$rcx', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $rax, $rcx
+
+    ; SELECTED-LABEL: name: test_rule634_id15801_at_idx36025
+    ; SELECTED: liveins: $rax, $rcx
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[XOR64rr:%[0-9]+]]:gr64 = XOR64rr [[COPY1]], [[COPY]], implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR64rr]]
+    %2:gpr(s64) = COPY $rcx
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule635_id15599_at_idx36069
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule635_id15599_at_idx36069
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVZX32rr8_]]
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s32) = G_ANYEXT %1(s8)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule636_id2219_at_idx36102
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule636_id2219_at_idx36102
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[VMOV64toSDrr:%[0-9]+]]:fr64 = VMOV64toSDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOV64toSDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule637_id2223_at_idx36137
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule637_id2223_at_idx36137
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[VMOV64toSDrr:%[0-9]+]]:fr64 = VMOV64toSDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOV64toSDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule638_id2224_at_idx36172
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule638_id2224_at_idx36172
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[VMOVDI2SSrr:%[0-9]+]]:fr32 = VMOVDI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVDI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule639_id2226_at_idx36207
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule639_id2226_at_idx36207
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[VMOVDI2SSrr:%[0-9]+]]:fr32 = VMOVDI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVDI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule640_id2235_at_idx36242
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule640_id2235_at_idx36242
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSDto64rr:%[0-9]+]]:gr64 = VMOVSDto64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSDto64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule641_id2238_at_idx36277
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule641_id2238_at_idx36277
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSDto64rr:%[0-9]+]]:gr64 = VMOVSDto64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSDto64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule642_id2240_at_idx36312
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule642_id2240_at_idx36312
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSS2DIrr:%[0-9]+]]:gr32 = VMOVSS2DIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSS2DIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule643_id2242_at_idx36347
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule643_id2242_at_idx36347
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSS2DIrr:%[0-9]+]]:gr32 = VMOVSS2DIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSS2DIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule644_id3924_at_idx36382
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule644_id3924_at_idx36382
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[VMOV64toSDrr:%[0-9]+]]:fr64 = VMOV64toSDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOV64toSDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule645_id3926_at_idx36417
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule645_id3926_at_idx36417
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSDto64rr:%[0-9]+]]:gr64 = VMOVSDto64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSDto64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule646_id3928_at_idx36452
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule646_id3928_at_idx36452
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[VMOVDI2SSrr:%[0-9]+]]:fr32 = VMOVDI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVDI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule647_id3934_at_idx36487
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule647_id3934_at_idx36487
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VMOVSS2DIrr:%[0-9]+]]:gr32 = VMOVSS2DIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSS2DIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule648_id14437_at_idx36522
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule648_id14437_at_idx36522
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(s32) = COPY $eax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(<32 x s1>) = G_BITCAST [[COPY]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<32 x s1>)
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(<32 x s1>) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(<32 x s1>)
+
+...
+---
+name:            test_rule649_id14438_at_idx36557
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule649_id14438_at_idx36557
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<32 x s1>) = COPY $eax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s32) = G_BITCAST [[COPY]](<32 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](s32)
+    %1:gpr(<32 x s1>) = COPY $eax
+    %0:gpr(s32) = G_BITCAST %1(<32 x s1>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule650_id14439_at_idx36592
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule650_id14439_at_idx36592
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(<64 x s1>) = G_BITCAST [[COPY]](s64)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<64 x s1>)
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(<64 x s1>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<64 x s1>)
+
+...
+---
+name:            test_rule651_id14440_at_idx36627
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule651_id14440_at_idx36627
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<64 x s1>) = COPY $rax
+    ; SELECTED: [[BITCAST:%[0-9]+]]:gpr(s64) = G_BITCAST [[COPY]](<64 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](s64)
+    %1:gpr(<64 x s1>) = COPY $rax
+    %0:gpr(s64) = G_BITCAST %1(<64 x s1>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule652_id15843_at_idx36662
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule652_id15843_at_idx36662
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule653_id15844_at_idx36706
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule653_id15844_at_idx36706
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule654_id15845_at_idx36750
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule654_id15845_at_idx36750
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule655_id15846_at_idx36794
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule655_id15846_at_idx36794
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule657_id15848_at_idx36882
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule657_id15848_at_idx36882
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule658_id15849_at_idx36926
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule658_id15849_at_idx36926
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule659_id15850_at_idx36970
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule659_id15850_at_idx36970
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule661_id15852_at_idx37058
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule661_id15852_at_idx37058
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule662_id15853_at_idx37102
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule662_id15853_at_idx37102
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule663_id15854_at_idx37146
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule663_id15854_at_idx37146
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule664_id15855_at_idx37190
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule664_id15855_at_idx37190
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s8>) = COPY $xmm0
+    %0:vecr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule667_id15858_at_idx37322
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule667_id15858_at_idx37322
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule668_id15859_at_idx37366
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule668_id15859_at_idx37366
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule669_id15860_at_idx37410
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule669_id15860_at_idx37410
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s16>) = COPY $xmm0
+    %0:vecr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule682_id15873_at_idx37982
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule682_id15873_at_idx37982
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fr128 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:vecr(s128) = COPY $xmm0
+    %0:vecr(s128) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule684_id15875_at_idx38070
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule684_id15875_at_idx38070
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_BITCAST %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule685_id15876_at_idx38114
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule685_id15876_at_idx38114
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_BITCAST %1(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule686_id15877_at_idx38158
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule686_id15877_at_idx38158
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_BITCAST %1(<32 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule688_id15879_at_idx38246
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule688_id15879_at_idx38246
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_BITCAST %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule689_id15880_at_idx38290
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule689_id15880_at_idx38290
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_BITCAST %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule690_id15881_at_idx38334
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule690_id15881_at_idx38334
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_BITCAST %1(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule691_id15882_at_idx38378
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule691_id15882_at_idx38378
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_BITCAST %1(<32 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule693_id15884_at_idx38466
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule693_id15884_at_idx38466
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_BITCAST %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule694_id15885_at_idx38510
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule694_id15885_at_idx38510
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_BITCAST %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule695_id15886_at_idx38554
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule695_id15886_at_idx38554
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_BITCAST %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule696_id15887_at_idx38598
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule696_id15887_at_idx38598
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s8>) = COPY $ymm0
+    %0:vecr(<16 x s16>) = G_BITCAST %1(<32 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule699_id15890_at_idx38730
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule699_id15890_at_idx38730
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_BITCAST %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule700_id15891_at_idx38774
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule700_id15891_at_idx38774
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_BITCAST %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule701_id15892_at_idx38818
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule701_id15892_at_idx38818
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<32 x s8>) = G_BITCAST %1(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule714_id15905_at_idx39390
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule714_id15905_at_idx39390
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_BITCAST %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule715_id15906_at_idx39434
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule715_id15906_at_idx39434
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_BITCAST %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule716_id15907_at_idx39478
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule716_id15907_at_idx39478
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_BITCAST %1(<32 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule717_id15908_at_idx39522
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule717_id15908_at_idx39522
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<64 x s8>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_BITCAST %1(<64 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule719_id15910_at_idx39610
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule719_id15910_at_idx39610
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_BITCAST %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule720_id15911_at_idx39654
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule720_id15911_at_idx39654
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_BITCAST %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule721_id15912_at_idx39698
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule721_id15912_at_idx39698
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_BITCAST %1(<32 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule722_id15913_at_idx39742
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule722_id15913_at_idx39742
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<64 x s8>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_BITCAST %1(<64 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule734_id15925_at_idx40270
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule734_id15925_at_idx40270
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_BITCAST %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule735_id15926_at_idx40314
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule735_id15926_at_idx40314
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_BITCAST %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule736_id15927_at_idx40358
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule736_id15927_at_idx40358
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<64 x s8>) = COPY $zmm0
+    %0:vecr(<32 x s16>) = G_BITCAST %1(<64 x s8>)
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule740_id15931_at_idx40534
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule740_id15931_at_idx40534
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<64 x s8>) = G_BITCAST %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule741_id15932_at_idx40578
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule741_id15932_at_idx40578
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<64 x s8>) = G_BITCAST %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule742_id15933_at_idx40622
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule742_id15933_at_idx40622
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<64 x s8>) = G_BITCAST %1(<32 x s16>)
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule745_id5_at_idx40754
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule745_id5_at_idx40754
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[BSWAP32r:%[0-9]+]]:gr32 = BSWAP32r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BSWAP32r]]
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s32) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule746_id6_at_idx40787
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule746_id6_at_idx40787
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[BSWAP64r:%[0-9]+]]:gr64 = BSWAP64r [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BSWAP64r]]
+    %1:gpr(s64) = COPY $rax
+    %0:gpr(s64) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule747_id15834_at_idx40820
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule747_id15834_at_idx40820
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[ROL16ri:%[0-9]+]]:gr16 = ROL16ri [[COPY]], 8, implicit-def $eflags
+    ; SELECTED: $noreg = PATCHABLE_RET [[ROL16ri]]
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s16) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule748_id19_at_idx40867
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule748_id19_at_idx40867
+    ; SELECTED: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV8ri]]
+    %0:gpr(s8) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule749_id20_at_idx40900
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule749_id20_at_idx40900
+    ; SELECTED: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOV16ri]]
+    %0:gpr(s16) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule750_id800_at_idx40933
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule750_id800_at_idx40933
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:vecr(s32) = G_FNEG [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](s32)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule751_id801_at_idx40971
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule751_id801_at_idx40971
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:vecr(s64) = G_FNEG [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](s64)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule752_id802_at_idx41009
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule752_id802_at_idx41009
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:vecr(s80) = G_FNEG [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](s80)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule753_id1429_at_idx41045
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule753_id1429_at_idx41045
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSS2SDrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule754_id1461_at_idx41080
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule754_id1461_at_idx41080
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTPS2PDYrr:%[0-9]+]]:vr256 = VCVTPS2PDYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPS2PDYrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_FPEXT %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule755_id8438_at_idx41115
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule755_id8438_at_idx41115
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTPS2PDZrr:%[0-9]+]]:vr512 = VCVTPS2PDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPS2PDZrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s64>) = G_FPEXT %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule756_id8459_at_idx41150
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule756_id8459_at_idx41150
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTPS2PDYrr:%[0-9]+]]:vr256 = VCVTPS2PDYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPS2PDYrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_FPEXT %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule757_id13475_at_idx41185
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule757_id13475_at_idx41185
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSS2SDrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule758_id15168_at_idx41245
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule758_id15168_at_idx41245
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSS2SDrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule759_id16241_at_idx41305
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule759_id16241_at_idx41305
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[DEF]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPEXT]](s64)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule760_id16242_at_idx41342
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule760_id16242_at_idx41342
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s32) = IMPLICIT_DEF
+    ; SELECTED: [[FPEXT:%[0-9]+]]:vecr(s80) = G_FPEXT [[DEF]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPEXT]](s80)
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule761_id16243_at_idx41379
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule761_id16243_at_idx41379
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FPEXT:%[0-9]+]]:vecr(s80) = G_FPEXT [[DEF]](s64)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPEXT]](s80)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s80) = G_FPEXT %1(s64)
+    $noreg = PATCHABLE_RET %0(s80)
+
+...
+---
+name:            test_rule762_id1345_at_idx41416
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule762_id1345_at_idx41416
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SIrr:%[0-9]+]]:gr32 = VCVTTSS2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule763_id1347_at_idx41451
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule763_id1347_at_idx41451
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SI64rr:%[0-9]+]]:gr64 = VCVTTSS2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule764_id1349_at_idx41486
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule764_id1349_at_idx41486
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SIrr:%[0-9]+]]:gr32 = VCVTTSD2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule765_id1351_at_idx41521
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule765_id1351_at_idx41521
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SI64rr:%[0-9]+]]:gr64 = VCVTTSD2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule766_id1353_at_idx41556
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule766_id1353_at_idx41556
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SIrr:%[0-9]+]]:gr32 = VCVTTSS2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule767_id1355_at_idx41591
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule767_id1355_at_idx41591
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SI64rr:%[0-9]+]]:gr64 = VCVTTSS2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule768_id1357_at_idx41626
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule768_id1357_at_idx41626
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SIrr:%[0-9]+]]:gr32 = VCVTTSD2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule769_id1359_at_idx41661
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule769_id1359_at_idx41661
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SI64rr:%[0-9]+]]:gr64 = VCVTTSD2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule770_id1447_at_idx41696
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule770_id1447_at_idx41696
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2DQrr:%[0-9]+]]:vr128 = VCVTTPS2DQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule771_id1449_at_idx41731
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule771_id1449_at_idx41731
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPS2DQYrr:%[0-9]+]]:vr256 = VCVTTPS2DQYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQYrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule772_id1451_at_idx41766
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule772_id1451_at_idx41766
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2DQrr:%[0-9]+]]:vr128 = VCVTTPS2DQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule773_id1455_at_idx41801
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule773_id1455_at_idx41801
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPD2DQYrr:%[0-9]+]]:vr128 = VCVTTPD2DQYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2DQYrr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule774_id8350_at_idx41836
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule774_id8350_at_idx41836
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SIrr:%[0-9]+]]:gr32 = VCVTTSS2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SIrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule775_id8355_at_idx41871
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule775_id8355_at_idx41871
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2SI64rr:%[0-9]+]]:gr64 = VCVTTSS2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2SI64rr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule776_id8360_at_idx41906
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule776_id8360_at_idx41906
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SIrr:%[0-9]+]]:gr32 = VCVTTSD2SIrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SIrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule777_id8365_at_idx41941
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule777_id8365_at_idx41941
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2SI64rr:%[0-9]+]]:gr64 = VCVTTSD2SI64rr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2SI64rr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule778_id8525_at_idx41976
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule778_id8525_at_idx41976
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPS2DQZrr:%[0-9]+]]:vr512 = VCVTTPS2DQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FPTOSI %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule779_id8537_at_idx42011
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule779_id8537_at_idx42011
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2DQrr:%[0-9]+]]:vr128 = VCVTTPS2DQrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule780_id8546_at_idx42046
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule780_id8546_at_idx42046
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPS2DQYrr:%[0-9]+]]:vr256 = VCVTTPS2DQYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2DQYrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule781_id8555_at_idx42081
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule781_id8555_at_idx42081
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPD2DQZrr:%[0-9]+]]:vr256x = VCVTTPD2DQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2DQZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule782_id8576_at_idx42116
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule782_id8576_at_idx42116
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPD2DQYrr:%[0-9]+]]:vr128 = VCVTTPD2DQYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2DQYrr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule783_id8942_at_idx42151
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule783_id8942_at_idx42151
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPD2QQZrr:%[0-9]+]]:vr512 = VCVTTPD2QQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2QQZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FPTOSI %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule784_id8954_at_idx42186
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule784_id8954_at_idx42186
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPD2QQZ128rr:%[0-9]+]]:vr128x = VCVTTPD2QQZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2QQZ128rr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule785_id8963_at_idx42221
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule785_id8963_at_idx42221
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPD2QQZ256rr:%[0-9]+]]:vr256x = VCVTTPD2QQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2QQZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FPTOSI %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule786_id8972_at_idx42256
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule786_id8972_at_idx42256
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPS2QQZrr:%[0-9]+]]:vr512 = VCVTTPS2QQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2QQZrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s64>) = G_FPTOSI %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule787_id8993_at_idx42291
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule787_id8993_at_idx42291
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2QQZ256rr:%[0-9]+]]:vr256x = VCVTTPS2QQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2QQZ256rr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule788_id8370_at_idx42326
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule788_id8370_at_idx42326
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2USIZrr:%[0-9]+]]:gr32 = VCVTTSS2USIZrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2USIZrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOUI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule789_id8375_at_idx42361
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule789_id8375_at_idx42361
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSS2USI64Zrr:%[0-9]+]]:gr64 = VCVTTSS2USI64Zrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSS2USI64Zrr]]
+    %1:vecr(s32) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOUI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule790_id8380_at_idx42396
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule790_id8380_at_idx42396
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2USIZrr:%[0-9]+]]:gr32 = VCVTTSD2USIZrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2USIZrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s32) = G_FPTOUI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule791_id8385_at_idx42431
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule791_id8385_at_idx42431
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTTSD2USI64Zrr:%[0-9]+]]:gr64 = VCVTTSD2USI64Zrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTSD2USI64Zrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:gpr(s64) = G_FPTOUI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule792_id8585_at_idx42466
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule792_id8585_at_idx42466
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPS2UDQZrr:%[0-9]+]]:vr512 = VCVTTPS2UDQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2UDQZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_FPTOUI %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule793_id8597_at_idx42501
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule793_id8597_at_idx42501
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2UDQZ128rr:%[0-9]+]]:vr128x = VCVTTPS2UDQZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2UDQZ128rr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule794_id8606_at_idx42536
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule794_id8606_at_idx42536
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPS2UDQZ256rr:%[0-9]+]]:vr256x = VCVTTPS2UDQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2UDQZ256rr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_FPTOUI %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule795_id8615_at_idx42571
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule795_id8615_at_idx42571
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPD2UDQZrr:%[0-9]+]]:vr256x = VCVTTPD2UDQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2UDQZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_FPTOUI %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule796_id8636_at_idx42606
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule796_id8636_at_idx42606
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPD2UDQZ256rr:%[0-9]+]]:vr128x = VCVTTPD2UDQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2UDQZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_FPTOUI %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule797_id9002_at_idx42641
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule797_id9002_at_idx42641
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTTPD2UQQZrr:%[0-9]+]]:vr512 = VCVTTPD2UQQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2UQQZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_FPTOUI %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule798_id9014_at_idx42676
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule798_id9014_at_idx42676
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPD2UQQZ128rr:%[0-9]+]]:vr128x = VCVTTPD2UQQZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2UQQZ128rr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule799_id9023_at_idx42711
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule799_id9023_at_idx42711
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPD2UQQZ256rr:%[0-9]+]]:vr256x = VCVTTPD2UQQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPD2UQQZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_FPTOUI %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule800_id9032_at_idx42746
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule800_id9032_at_idx42746
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTTPS2UQQZrr:%[0-9]+]]:vr512 = VCVTTPS2UQQZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2UQQZrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s64>) = G_FPTOUI %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule801_id9053_at_idx42781
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule801_id9053_at_idx42781
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTTPS2UQQZ256rr:%[0-9]+]]:vr256x = VCVTTPS2UQQZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTTPS2UQQZ256rr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_FPTOUI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule802_id1423_at_idx42816
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule802_id1423_at_idx42816
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSD2SSrr:%[0-9]+]]:fr32 = CVTSD2SSrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSD2SSrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule803_id1473_at_idx42851
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule803_id1473_at_idx42851
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTPD2PSYrr:%[0-9]+]]:vr128 = VCVTPD2PSYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPD2PSYrr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_FPTRUNC %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule804_id8408_at_idx42886
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule804_id8408_at_idx42886
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTPD2PSZrr:%[0-9]+]]:vr256x = VCVTPD2PSZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPD2PSZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_FPTRUNC %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule805_id8429_at_idx42921
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule805_id8429_at_idx42921
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTPD2PSYrr:%[0-9]+]]:vr128 = VCVTPD2PSYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPD2PSYrr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_FPTRUNC %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule806_id13474_at_idx42956
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule806_id13474_at_idx42956
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSD2SSrr:%[0-9]+]]:fr32 = CVTSD2SSrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSD2SSrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule807_id15172_at_idx43016
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule807_id15172_at_idx43016
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64 = IMPLICIT_DEF
+    ; SELECTED: [[CVTSD2SSrr:%[0-9]+]]:fr32 = CVTSD2SSrr [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSD2SSrr]]
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule808_id16244_at_idx43076
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule808_id16244_at_idx43076
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s64) = IMPLICIT_DEF
+    ; SELECTED: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[DEF]](s64)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTRUNC]](s32)
+    %1:vecr(s64) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule809_id16245_at_idx43113
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule809_id16245_at_idx43113
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[DEF]](s80)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTRUNC]](s32)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s32) = G_FPTRUNC %1(s80)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule810_id16246_at_idx43150
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule810_id16246_at_idx43150
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(s80) = IMPLICIT_DEF
+    ; SELECTED: [[FPTRUNC:%[0-9]+]]:vecr(s64) = G_FPTRUNC [[DEF]](s80)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTRUNC]](s64)
+    %1:vecr(s80) = IMPLICIT_DEF
+    %0:vecr(s64) = G_FPTRUNC %1(s80)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule811_id526_at_idx43187
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule811_id526_at_idx43187
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[MOVSX32rr8_:%[0-9]+]]:gr32 = MOVSX32rr8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVSX32rr8_]]
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s32) = G_SEXT %1(s8)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule812_id528_at_idx43220
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule812_id528_at_idx43220
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[MOVSX32rr16_:%[0-9]+]]:gr32 = MOVSX32rr16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVSX32rr16_]]
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s32) = G_SEXT %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule813_id534_at_idx43253
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule813_id534_at_idx43253
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVSX64rr8_]]
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s64) = G_SEXT %1(s8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule814_id536_at_idx43286
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule814_id536_at_idx43286
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVSX64rr16_]]
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s64) = G_SEXT %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule815_id538_at_idx43319
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule815_id538_at_idx43319
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[MOVSX64rr32_:%[0-9]+]]:gr64 = MOVSX64rr32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVSX64rr32_]]
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s64) = G_SEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule816_id10064_at_idx43354
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule816_id10064_at_idx43354
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<64 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<64 x s8>) = G_SEXT [[DEF]](<64 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<64 x s8>)
+    %1:vecr(<64 x s1>) = IMPLICIT_DEF
+    %0:vecr(<64 x s8>) = G_SEXT %1(<64 x s1>)
+    $noreg = PATCHABLE_RET %0(<64 x s8>)
+
+...
+---
+name:            test_rule817_id10065_at_idx43389
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule817_id10065_at_idx43389
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<32 x s8>) = G_SEXT [[DEF]](<32 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<32 x s8>)
+    %1:vecr(<32 x s1>) = IMPLICIT_DEF
+    %0:vecr(<32 x s8>) = G_SEXT %1(<32 x s1>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule818_id10066_at_idx43424
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule818_id10066_at_idx43424
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<16 x s8>) = G_SEXT [[COPY]](<16 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<16 x s8>)
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:vecr(<16 x s8>) = G_SEXT %1(<16 x s1>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule819_id10067_at_idx43459
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule819_id10067_at_idx43459
+    ; SELECTED: [[DEF:%[0-9]+]]:vecr(<32 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<32 x s16>) = G_SEXT [[DEF]](<32 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<32 x s16>)
+    %1:vecr(<32 x s1>) = IMPLICIT_DEF
+    %0:vecr(<32 x s16>) = G_SEXT %1(<32 x s1>)
+    $noreg = PATCHABLE_RET %0(<32 x s16>)
+
+...
+---
+name:            test_rule820_id10068_at_idx43494
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule820_id10068_at_idx43494
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<16 x s16>) = G_SEXT [[COPY]](<16 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<16 x s16>)
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:vecr(<16 x s16>) = G_SEXT %1(<16 x s1>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule821_id10069_at_idx43529
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule821_id10069_at_idx43529
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<8 x s16>) = G_SEXT [[COPY]](<8 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<8 x s16>)
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:vecr(<8 x s16>) = G_SEXT %1(<8 x s1>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule822_id10070_at_idx43564
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule822_id10070_at_idx43564
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<16 x s32>) = G_SEXT [[COPY]](<16 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<16 x s32>)
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:vecr(<16 x s32>) = G_SEXT %1(<16 x s1>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule823_id10071_at_idx43599
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule823_id10071_at_idx43599
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<8 x s32>) = G_SEXT [[COPY]](<8 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<8 x s32>)
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:vecr(<8 x s32>) = G_SEXT %1(<8 x s1>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule824_id10072_at_idx43634
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule824_id10072_at_idx43634
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<4 x s32>) = G_SEXT [[DEF]](<4 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<4 x s32>)
+    %1:gpr(<4 x s1>) = IMPLICIT_DEF
+    %0:vecr(<4 x s32>) = G_SEXT %1(<4 x s1>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule825_id10073_at_idx43669
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule825_id10073_at_idx43669
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<8 x s1>) = COPY $al
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<8 x s64>) = G_SEXT [[COPY]](<8 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<8 x s64>)
+    %1:gpr(<8 x s1>) = COPY $al
+    %0:vecr(<8 x s64>) = G_SEXT %1(<8 x s1>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule826_id10074_at_idx43704
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule826_id10074_at_idx43704
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<4 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<4 x s64>) = G_SEXT [[DEF]](<4 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<4 x s64>)
+    %1:gpr(<4 x s1>) = IMPLICIT_DEF
+    %0:vecr(<4 x s64>) = G_SEXT %1(<4 x s1>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule827_id10075_at_idx43739
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule827_id10075_at_idx43739
+    ; SELECTED: [[DEF:%[0-9]+]]:gpr(<2 x s1>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<2 x s64>) = G_SEXT [[DEF]](<2 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<2 x s64>)
+    %1:gpr(<2 x s1>) = IMPLICIT_DEF
+    %0:vecr(<2 x s64>) = G_SEXT %1(<2 x s1>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule828_id15336_at_idx43774
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule828_id15336_at_idx43774
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<16 x s8>) = G_SEXT [[COPY]](<16 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<16 x s8>)
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:vecr(<16 x s8>) = G_SEXT %1(<16 x s1>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule829_id15337_at_idx43834
+alignment:       4
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule829_id15337_at_idx43834
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr(<16 x s1>) = COPY $ax
+    ; SELECTED: [[SEXT:%[0-9]+]]:vecr(<16 x s16>) = G_SEXT [[COPY]](<16 x s1>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<16 x s16>)
+    %1:gpr(<16 x s1>) = COPY $ax
+    %0:vecr(<16 x s16>) = G_SEXT %1(<16 x s1>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule830_id1361_at_idx43894
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule830_id1361_at_idx43894
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule831_id1363_at_idx43929
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule831_id1363_at_idx43929
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SSrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s32) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule832_id1365_at_idx43964
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule832_id1365_at_idx43964
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SDrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s64) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule833_id1367_at_idx43999
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule833_id1367_at_idx43999
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule834_id1417_at_idx44034
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule834_id1417_at_idx44034
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTDQ2PSrr:%[0-9]+]]:vr128 = VCVTDQ2PSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule835_id1419_at_idx44069
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule835_id1419_at_idx44069
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTDQ2PSYrr:%[0-9]+]]:vr256 = VCVTDQ2PSYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSYrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule836_id1421_at_idx44104
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule836_id1421_at_idx44104
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTDQ2PSrr:%[0-9]+]]:vr128 = VCVTDQ2PSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule837_id1468_at_idx44139
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule837_id1468_at_idx44139
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTDQ2PDYrr:%[0-9]+]]:vr256 = VCVTDQ2PDYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PDYrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule838_id8468_at_idx44174
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule838_id8468_at_idx44174
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTDQ2PDZrr:%[0-9]+]]:vr512 = VCVTDQ2PDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PDZrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s64>) = G_SITOFP %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule839_id8486_at_idx44209
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule839_id8486_at_idx44209
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTDQ2PDYrr:%[0-9]+]]:vr256 = VCVTDQ2PDYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PDYrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule840_id8495_at_idx44244
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule840_id8495_at_idx44244
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTDQ2PSZrr:%[0-9]+]]:vr512 = VCVTDQ2PSZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_SITOFP %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule841_id8507_at_idx44279
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule841_id8507_at_idx44279
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+    ; SELECTED: [[VCVTDQ2PSrr:%[0-9]+]]:vr128 = VCVTDQ2PSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSrr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule842_id8516_at_idx44314
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule842_id8516_at_idx44314
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTDQ2PSYrr:%[0-9]+]]:vr256 = VCVTDQ2PSYrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDQ2PSYrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule843_id9062_at_idx44349
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule843_id9062_at_idx44349
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTQQ2PDZrr:%[0-9]+]]:vr512 = VCVTQQ2PDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTQQ2PDZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_SITOFP %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule844_id9074_at_idx44384
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule844_id9074_at_idx44384
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTQQ2PDZ128rr:%[0-9]+]]:vr128x = VCVTQQ2PDZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTQQ2PDZ128rr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule845_id9083_at_idx44419
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule845_id9083_at_idx44419
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTQQ2PDZ256rr:%[0-9]+]]:vr256x = VCVTQQ2PDZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTQQ2PDZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule846_id9122_at_idx44454
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule846_id9122_at_idx44454
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTQQ2PSZrr:%[0-9]+]]:vr256x = VCVTQQ2PSZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTQQ2PSZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule847_id9143_at_idx44489
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule847_id9143_at_idx44489
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTQQ2PSZ256rr:%[0-9]+]]:vr128x = VCVTQQ2PSZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTQQ2PSZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule848_id13470_at_idx44524
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule848_id13470_at_idx44524
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule849_id13471_at_idx44584
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule849_id13471_at_idx44584
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SSrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s32) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule850_id13472_at_idx44644
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule850_id13472_at_idx44644
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SDrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s64) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule851_id13473_at_idx44704
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule851_id13473_at_idx44704
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule852_id15126_at_idx44764
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule852_id15126_at_idx44764
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SSrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule853_id15127_at_idx44824
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule853_id15127_at_idx44824
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SSrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s32) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule854_id15128_at_idx44884
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule854_id15128_at_idx44884
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI2SDrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s64) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule855_id15129_at_idx44944
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule855_id15129_at_idx44944
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CVTSI642SDrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule856_id9671_at_idx45004
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule856_id9671_at_idx45004
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMOVQWZrr:%[0-9]+]]:vr128x = VPMOVQWZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVQWZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s16>) = G_TRUNC %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule857_id9695_at_idx45039
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule857_id9695_at_idx45039
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMOVQDZ256rr:%[0-9]+]]:vr128x = VPMOVQDZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVQDZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_TRUNC %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule858_id9698_at_idx45074
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule858_id9698_at_idx45074
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMOVQDZrr:%[0-9]+]]:vr256x = VPMOVQDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVQDZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_TRUNC %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule859_id9725_at_idx45109
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule859_id9725_at_idx45109
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMOVDBZrr:%[0-9]+]]:vr128x = VPMOVDBZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVDBZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s8>) = G_TRUNC %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule860_id9749_at_idx45144
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule860_id9749_at_idx45144
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMOVDWZ256rr:%[0-9]+]]:vr128x = VPMOVDWZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVDWZ256rr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s16>) = G_TRUNC %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule861_id9752_at_idx45179
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule861_id9752_at_idx45179
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMOVDWZrr:%[0-9]+]]:vr256x = VPMOVDWZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVDWZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s16>) = G_TRUNC %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s16>)
+
+...
+---
+name:            test_rule862_id9776_at_idx45214
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule862_id9776_at_idx45214
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VPMOVWBZ256rr:%[0-9]+]]:vr128x = VPMOVWBZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVWBZ256rr]]
+    %1:vecr(<16 x s16>) = COPY $ymm0
+    %0:vecr(<16 x s8>) = G_TRUNC %1(<16 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule863_id9779_at_idx45249
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule863_id9779_at_idx45249
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VPMOVWBZrr:%[0-9]+]]:vr256x = VPMOVWBZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMOVWBZrr]]
+    %1:vecr(<32 x s16>) = COPY $zmm0
+    %0:vecr(<32 x s8>) = G_TRUNC %1(<32 x s16>)
+    $noreg = PATCHABLE_RET %0(<32 x s8>)
+
+...
+---
+name:            test_rule864_id15634_at_idx45284
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule864_id15634_at_idx45284
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s16) = G_TRUNC %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule865_id15640_at_idx45333
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule865_id15640_at_idx45333
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s32) = COPY $eax
+    %0:gpr(s8) = G_TRUNC %1(s32)
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule866_id15641_at_idx45384
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule866_id15641_at_idx45384
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s8) = G_TRUNC %1(s16)
+    $noreg = PATCHABLE_RET %0(s8)
+
+...
+---
+name:            test_rule867_id8645_at_idx45435
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule867_id8645_at_idx45435
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTUDQ2PDZrr:%[0-9]+]]:vr512 = VCVTUDQ2PDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUDQ2PDZrr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s64>) = G_UITOFP %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule868_id8663_at_idx45470
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule868_id8663_at_idx45470
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTUDQ2PDZ256rr:%[0-9]+]]:vr256x = VCVTUDQ2PDZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUDQ2PDZ256rr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s64>) = G_UITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule869_id8672_at_idx45505
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule869_id8672_at_idx45505
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTUDQ2PSZrr:%[0-9]+]]:vr512 = VCVTUDQ2PSZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUDQ2PSZrr]]
+    %1:vecr(<16 x s32>) = COPY $zmm0
+    %0:vecr(<16 x s32>) = G_UITOFP %1(<16 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s32>)
+
+...
+---
+name:            test_rule870_id8684_at_idx45540
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule870_id8684_at_idx45540
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTUDQ2PSZ128rr:%[0-9]+]]:vr128x = VCVTUDQ2PSZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUDQ2PSZ128rr]]
+    %1:vecr(<4 x s32>) = COPY $xmm0
+    %0:vecr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule871_id8693_at_idx45575
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule871_id8693_at_idx45575
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTUDQ2PSZ256rr:%[0-9]+]]:vr256x = VCVTUDQ2PSZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUDQ2PSZ256rr]]
+    %1:vecr(<8 x s32>) = COPY $ymm0
+    %0:vecr(<8 x s32>) = G_UITOFP %1(<8 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule872_id9092_at_idx45610
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule872_id9092_at_idx45610
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTUQQ2PDZrr:%[0-9]+]]:vr512 = VCVTUQQ2PDZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUQQ2PDZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s64>) = G_UITOFP %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s64>)
+
+...
+---
+name:            test_rule873_id9104_at_idx45645
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$xmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $xmm0
+
+    ; SELECTED-LABEL: name: test_rule873_id9104_at_idx45645
+    ; SELECTED: liveins: $xmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:fr128 = COPY $xmm0
+    ; SELECTED: [[VCVTUQQ2PDZ128rr:%[0-9]+]]:vr128x = VCVTUQQ2PDZ128rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUQQ2PDZ128rr]]
+    %1:vecr(<2 x s64>) = COPY $xmm0
+    %0:vecr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule874_id9113_at_idx45680
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule874_id9113_at_idx45680
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTUQQ2PDZ256rr:%[0-9]+]]:vr256x = VCVTUQQ2PDZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUQQ2PDZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s64>) = G_UITOFP %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s64>)
+
+...
+---
+name:            test_rule875_id9152_at_idx45715
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$zmm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $zmm0
+
+    ; SELECTED-LABEL: name: test_rule875_id9152_at_idx45715
+    ; SELECTED: liveins: $zmm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+    ; SELECTED: [[VCVTUQQ2PSZrr:%[0-9]+]]:vr256x = VCVTUQQ2PSZrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUQQ2PSZrr]]
+    %1:vecr(<8 x s64>) = COPY $zmm0
+    %0:vecr(<8 x s32>) = G_UITOFP %1(<8 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s32>)
+
+...
+---
+name:            test_rule876_id9173_at_idx45750
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+liveins:
+  - { reg: '$ymm0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ymm0
+
+    ; SELECTED-LABEL: name: test_rule876_id9173_at_idx45750
+    ; SELECTED: liveins: $ymm0
+    ; SELECTED: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+    ; SELECTED: [[VCVTUQQ2PSZ256rr:%[0-9]+]]:vr128x = VCVTUQQ2PSZ256rr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUQQ2PSZ256rr]]
+    %1:vecr(<4 x s64>) = COPY $ymm0
+    %0:vecr(<4 x s32>) = G_UITOFP %1(<4 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule877_id15134_at_idx45785
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule877_id15134_at_idx45785
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTUSI2SSZrr:%[0-9]+]]:fr32x = VCVTUSI2SSZrr [[DEF]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUSI2SSZrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s32) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule878_id15135_at_idx45845
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule878_id15135_at_idx45845
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[DEF:%[0-9]+]]:fr32x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTUSI642SSZrr:%[0-9]+]]:fr32x = VCVTUSI642SSZrr [[DEF]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUSI642SSZrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s32) = G_UITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule879_id15136_at_idx45905
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$eax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $eax
+
+    ; SELECTED-LABEL: name: test_rule879_id15136_at_idx45905
+    ; SELECTED: liveins: $eax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTUSI2SDZrr:%[0-9]+]]:fr64x = VCVTUSI2SDZrr [[DEF]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUSI2SDZrr]]
+    %1:gpr(s32) = COPY $eax
+    %0:vecr(s64) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule880_id15137_at_idx45965
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$rax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $rax
+
+    ; SELECTED-LABEL: name: test_rule880_id15137_at_idx45965
+    ; SELECTED: liveins: $rax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr64 = COPY $rax
+    ; SELECTED: [[DEF:%[0-9]+]]:fr64x = IMPLICIT_DEF
+    ; SELECTED: [[VCVTUSI642SDZrr:%[0-9]+]]:fr64x = VCVTUSI642SDZrr [[DEF]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTUSI642SDZrr]]
+    %1:gpr(s64) = COPY $rax
+    %0:vecr(s64) = G_UITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule881_id530_at_idx46025
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$al', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $al
+
+    ; SELECTED-LABEL: name: test_rule881_id530_at_idx46025
+    ; SELECTED: liveins: $al
+    ; SELECTED: [[COPY:%[0-9]+]]:gr8 = COPY $al
+    ; SELECTED: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVZX32rr8_]]
+    %1:gpr(s8) = COPY $al
+    %0:gpr(s32) = G_ZEXT %1(s8)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule882_id532_at_idx46058
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$ax', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $ax
+
+    ; SELECTED-LABEL: name: test_rule882_id532_at_idx46058
+    ; SELECTED: liveins: $ax
+    ; SELECTED: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; SELECTED: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVZX32rr16_]]
+    %1:gpr(s16) = COPY $ax
+    %0:gpr(s32) = G_ZEXT %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule883_id542_at_idx46091
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors:
+
+    ; SELECTED-LABEL: name: test_rule883_id542_at_idx46091
+    ; SELECTED: successors:
+    ; SELECTED: JMP_1 %bb.0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_BR %bb.0
+    $noreg = PATCHABLE_RET
+
+...
Index: test/CodeGen/X86/GlobalISel/x86_64-instruction-select-testgen-testgend.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/GlobalISel/x86_64-instruction-select-testgen-testgend.mir
@@ -0,0 +1,17337 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+# RUN: llc -mtriple x86_64-- -run-pass instruction-select-testgen \
+# RUN:     -testgen-exclude-rules=0,378,379,448,449,450,451,452,453,469,470,471,472,473,474,490,491,492,493,494,495,511,512,513,514,515,516 \
+# RUN:     -testgen-set-all-features -verify-machineinstrs -simplify-mir %s \
+# RUN:     -o - 2>&1 | FileCheck %s --check-prefix=TESTGEND
+#
+# TESTGEND:       ---
+# TESTGEND:       name:            test_return
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s8) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule2
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %2:gpr(s16) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s16) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule3
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule4
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule7
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s32) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s32) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule8
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s64) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s64) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule9
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s32) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s32) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule10
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s64) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s64) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule11
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s32) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule12
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s64) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule13
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s32) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule14
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s64) = G_AND %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule15
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s32) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule16
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s64) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule17
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s32) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule18
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_XOR %5, %6
+# TESTGEND:           %0:gpr(s64) = G_ADD %5, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule19
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_ADD %3, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule20
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ADD %3, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule21
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule22
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule23
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s32) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule24
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %1:gpr(s64) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %5, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule25
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %5:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %6:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gpr(s32) = G_OR %5, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule26
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %5:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %6:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ADD %5, %6
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %4
+# TESTGEND:           %2:gpr(s64) = G_OR %5, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule27
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule28
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule29
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule30
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 3
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.int), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule31
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.tbm.bextri.u64), %2(s64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule32
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cmp.ss), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule33
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cmp.sd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule34
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cmp.ss), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule35
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cmp.sd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule36
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.mpsadbw), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule37
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dpps), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule38
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dppd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule39
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %3:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx.dp.ps.256), %2(<8 x s32>), %3(<8 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule40
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %3:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.mpsadbw), %2(<32 x s8>), %3(<32 x s8>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule41
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.mpsadbw), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule42
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dpps), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule43
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.dppd), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule44
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse42.pcmpistrm128), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule45
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse42.pcmpistrm128), %2(<16 x s8>), %3(<16 x s8>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule46
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1rnds4), %2(<4 x s32>), %3(<4 x s32>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule47
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule48
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule49
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %3:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.256), %2(<4 x s64>), %3(<4 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule50
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %3:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.512), %2(<8 x s64>), %3(<8 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule51
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq), %2(<2 x s64>), %3(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule52
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %3:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.pclmulqdq.256), %2(<4 x s64>), %3(<4 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule53
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.tbm.bextri.u32), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule54
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aeskeygenassist), %2(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule55
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aeskeygenassist), %2(<2 x s64>), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule56
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.lwpval32), %1(s32), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule57
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.lwpval64), %1(s64), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule58
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule59
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule60
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule61
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule62
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %2
+# TESTGEND:           %1:gpr(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule63
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %2
+# TESTGEND:           %1:gpr(s64) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule64
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %3:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %4:gpr(s1) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s1) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s1) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule65
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule66
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule67
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule68
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule69
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %4:gpr(s32) = COPY $eax
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule70
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %4:gpr(s64) = COPY $rax
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule71
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %3:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %4:gpr(s1) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s1) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s1) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule72
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule73
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule74
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule75
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule76
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT -2
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %2
+# TESTGEND:           %1:gpr(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule77
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT -2
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %2
+# TESTGEND:           %1:gpr(s64) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule78
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule79
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule80
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule81
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule82
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %4:gpr(s32) = COPY $eax
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT -2
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule83
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %4:gpr(s64) = COPY $rax
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT -2
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule84
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule85
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule86
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule87
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %2, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule88
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %3:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %4:gpr(s1) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s1) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s1) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule89
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %3:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %4:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(s1) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s1) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s1) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule90
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule91
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule92
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %3:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule93
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %3, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule94
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %3:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %4:gpr(s1) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s1) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s1) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule95
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xabort), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule96
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.int), %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule97
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gpr(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule98
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gpr(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule99
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule100
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule101
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmadcswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule102
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmadcsswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule103
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<8 x s16>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsww), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule104
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule105
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<8 x s16>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssww), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule106
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsswd), %1(<8 x s16>), %2(<8 x s16>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule107
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdql), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule108
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdqh), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule109
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacssdd), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule110
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdql), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule111
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdqh), %1(<4 x s32>), %2(<4 x s32>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule112
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vpmacsdd), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule113
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<2 x s64>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.blendvpd), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule114
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1, $ymm2
+#
+# TESTGEND:           %3:vecr(<4 x s64>) = COPY $ymm2
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.avx.blendv.pd.256), %1(<4 x s64>), %2(<4 x s64>), %3(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule115
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.blendvps), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule116
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1, $ymm2
+#
+# TESTGEND:           %3:vecr(<8 x s32>) = COPY $ymm2
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx.blendv.ps.256), %1(<8 x s32>), %2(<8 x s32>), %3(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule117
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %3:vecr(<16 x s8>) = COPY $xmm2
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.sse41.pblendvb), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule118
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ymm2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1, $ymm2
+#
+# TESTGEND:           %3:vecr(<32 x s8>) = COPY $ymm2
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.pblendvb), %1(<32 x s8>), %2(<32 x s8>), %3(<32 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule119
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pdep.32), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule120
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pdep.64), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule121
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pext.32), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule122
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.bmi.pext.64), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule123
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule124
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule125
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule126
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule127
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule128
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule129
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule130
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule131
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2ss), %1(<4 x s32>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule132
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2ss), %1(<4 x s32>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule133
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtss2sd), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule134
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtss2sd), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule135
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.b.128), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule136
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.w.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule137
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.d.128), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule138
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phadd.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule139
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phsub.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule140
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.b), %1(<32 x s8>), %2(<32 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule141
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.w), %1(<16 x s16>), %2(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule142
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.psign.d), %1(<8 x s32>), %2(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule143
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.phadd.sw), %1(<16 x s16>), %2(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule144
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.avx2.phsub.sw), %1(<16 x s16>), %2(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule145
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.b.128), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule146
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.w.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule147
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.psign.d.128), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule148
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phadd.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule149
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.ssse3.phsub.sw.128), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule150
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.8), %1(s32), %2(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule151
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.16), %1(s32), %2(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule152
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.32.32), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule153
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse42.crc32.64.64), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule154
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1nexte), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule155
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1msg1), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule156
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha1msg2), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule157
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha256msg1), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule158
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sha256msg2), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule159
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule160
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule161
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule162
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule163
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule164
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule165
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule166
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule167
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule168
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule169
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule170
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule171
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse4a.extrq), %1(<2 x s64>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule172
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse4a.insertq), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule173
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule174
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule175
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenc.512), %1(<8 x s64>), %2(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule176
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule177
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule178
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesenclast.512), %1(<8 x s64>), %2(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule179
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule180
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule181
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdec.512), %1(<8 x s64>), %2(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule182
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule183
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.256), %1(<4 x s64>), %2(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule184
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesdeclast.512), %1(<8 x s64>), %2(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule185
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi2ss), %1(<4 x s32>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule186
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtsi642ss), %1(<4 x s32>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule187
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi2sd), %1(<2 x s64>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule188
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsi642sd), %1(<2 x s64>), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule189
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.avx512.cvtusi2sd), %1(<2 x s64>), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule190
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %2:gpr(s16) = G_CONSTANT 128
+# TESTGEND:           %0:gpr(s16) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule191
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT 128
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule192
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 128
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule193
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 2147483648
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule194
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule195
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %2:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s16) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule196
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule197
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule198
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s8) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule199
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %2:gpr(s16) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s16) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule200
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule201
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule202
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule203
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule204
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule205
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule206
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubwd), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule207
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubdq), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule208
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphsubbw), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule209
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddwq), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule210
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddwd), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule211
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadduwq), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule212
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadduwd), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule213
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddudq), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule214
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubw), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule215
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubq), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule216
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddubd), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule217
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphadddq), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule218
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbw), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule219
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbq), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule220
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vphaddbd), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule221
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule222
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ps), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule223
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.ps.256), %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule224
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.sd), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule225
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.pd), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule226
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.xop.vfrcz.pd.256), %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule227
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule228
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule229
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule230
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule231
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule232
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule233
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule234
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule235
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule236
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule237
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule238
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule239
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule240
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule241
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule242
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule243
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesimc), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule244
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.aesni.aesimc), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule245
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rcp.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule246
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rsqrt.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule247
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule248
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule249
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rcp.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule250
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.rsqrt.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule251
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule252
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.x86.sse2.sqrt.sd), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule253
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule254
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.x86.sse.sqrt.ss), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule255
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule256
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvtss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule257
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule258
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvtsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule259
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule260
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse.cvttss2si64), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule261
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule262
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.x86.sse2.cvttsd2si64), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule263
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdsspd), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule264
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdsspq), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule265
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule266
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule267
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule268
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule269
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule270
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule271
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule272
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %2:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s8) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule273
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule274
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule275
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.slwpcb)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule276
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.slwpcb)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule277
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xbegin)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule278
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdpkru)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule279
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdfsbase.32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule280
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdfsbase.64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule281
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdgsbase.32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule282
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdgsbase.64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule283
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.rdpid)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule284
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.write.u32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule285
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %0:gpr(s64) = COPY $rax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.write.u64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule286
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.llwpcb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule287
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %0:gpr(s64) = COPY $rax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.llwpcb), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule288
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.incsspd), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule289
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %0:gpr(s64) = COPY $rax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.incsspq), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule290
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrpkru), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule291
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrfsbase.32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule292
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %0:gpr(s64) = COPY $rax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrfsbase.64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule293
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %0:gpr(s32) = COPY $eax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrgsbase.32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule294
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %0:gpr(s64) = COPY $rax
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.wrgsbase.64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule295
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.pause)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule296
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse.sfence)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule297
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.lfence)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule298
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.sse2.mfence)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule299
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.avx.vzeroall)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule300
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.avx.vzeroupper)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule301
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.mmx.emms)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule302
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.mmx.femms)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule303
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.xend)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule304
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.saveprevssp)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule305
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.setssbsy)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule306
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule307
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule308
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule309
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule310
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule311
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule312
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule313
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule314
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule315
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule316
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule317
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule318
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule319
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule320
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule321
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule322
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule323
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule324
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule325
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule326
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule327
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule328
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule329
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule330
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:         - { id: 4, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %4:vecr(<8 x s16>) = COPY $xmm2
+# TESTGEND:           %3:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:vecr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule331
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:         - { id: 4, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %4:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:vecr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule332
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:         - { id: 4, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %4:vecr(<8 x s16>) = COPY $xmm2
+# TESTGEND:           %3:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:vecr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule333
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:         - { id: 3, class: vecr }
+# TESTGEND:         - { id: 4, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$xmm2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1, $xmm2
+#
+# TESTGEND:           %4:vecr(<4 x s32>) = COPY $xmm2
+# TESTGEND:           %3:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:vecr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule334
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule335
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule336
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule337
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule338
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule339
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule340
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule341
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule342
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule343
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule344
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule345
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule346
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule347
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule348
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule349
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule350
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule351
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule352
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule353
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule354
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule355
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule356
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule357
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule358
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule359
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule360
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s8) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule361
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s16) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule362
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s32) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule363
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_BITCAST %2(<16 x s1>)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule364
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_BITCAST %2(<8 x s1>)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule365
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %2:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_BITCAST %2(<16 x s1>)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule366
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_BITCAST %2(<8 x s1>)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule367
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %3:gpr(s32) = COPY $ecx
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule368
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rcx
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule369
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %3:gpr(s32) = COPY $ecx
+# TESTGEND:           %2:gpr(s32) = COPY $eax
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule370
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %3:gpr(s64) = COPY $rcx
+# TESTGEND:           %2:gpr(s64) = COPY $rax
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule371
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule372
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s32) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule373
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s32) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule374
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s64) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule375
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s64) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule376
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s80) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule377
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:vecr(s80) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule380
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule381
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule382
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule383
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule384
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule385
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule386
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule387
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule388
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule389
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule390
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule391
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule392
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule393
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule394
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule395
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule396
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule397
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule398
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule399
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule400
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule401
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<64 x s8>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<64 x s8>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<64 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule402
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule403
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule404
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(s8) = COPY $cl
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule405
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule406
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule407
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule408
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule409
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule410
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule411
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule412
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(<16 x s1>) = COPY $cx
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:gpr(<16 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule413
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<32 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule414
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<64 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule415
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule416
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule417
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule418
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule419
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(s128) = COPY $xmm1
+# TESTGEND:           %1:vecr(s128) = COPY $xmm0
+# TESTGEND:           %0:vecr(s128) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule420
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule421
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s1) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule422
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<2 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule423
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<4 x s1>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule424
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(s8) = COPY $cl
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule425
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule426
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule427
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule428
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule429
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule430
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule431
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule432
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule433
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule434
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule435
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule436
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule437
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule438
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule439
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule440
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule441
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule442
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule443
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule444
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule445
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule446
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule447
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule454
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule455
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule456
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule457
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule458
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule459
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule460
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule461
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule462
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule463
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule464
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule465
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule466
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule467
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule468
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule475
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule476
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule477
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule478
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule479
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule480
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule481
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule482
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule483
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule484
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule485
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule486
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule487
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule488
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule489
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule496
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule497
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule498
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule499
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule500
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule501
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule502
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule503
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule504
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule505
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule506
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule507
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule508
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule509
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule510
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule517
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule518
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule519
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule520
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule521
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule522
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule523
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule524
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule525
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule526
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule527
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule528
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule529
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule530
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule531
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule532
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule533
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule534
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule535
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule536
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule537
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule538
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule539
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule540
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule541
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule542
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule543
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule544
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule545
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule546
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule547
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule548
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule549
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule550
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule551
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule552
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule553
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule554
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule555
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule556
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule557
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule558
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(<16 x s1>) = COPY $cx
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:gpr(<16 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule559
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<32 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule560
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<64 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule561
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule562
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule563
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule564
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule565
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(s128) = COPY $xmm1
+# TESTGEND:           %1:vecr(s128) = COPY $xmm0
+# TESTGEND:           %0:vecr(s128) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule566
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule567
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s1) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule568
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<2 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule569
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<4 x s1>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule570
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(s8) = COPY $cl
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule571
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule572
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule573
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule574
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule575
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule576
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule577
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule578
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule579
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule580
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule581
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule582
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule583
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule584
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule585
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule586
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule587
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule588
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule589
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule590
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule591
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule592
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule593
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule594
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule595
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule596
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule597
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule598
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule599
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule600
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule601
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule602
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<16 x s32>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule603
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<8 x s32>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule604
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<4 x s32>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule605
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<32 x s16>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule606
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<16 x s16>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule607
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<8 x s16>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule608
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<64 x s8>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<64 x s8>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<64 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule609
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<32 x s8>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule610
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<16 x s8>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule611
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(s8) = COPY $cl
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule612
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule613
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule614
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule615
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule616
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule617
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule618
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule619
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(<16 x s1>) = COPY $cx
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:gpr(<16 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule620
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<32 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule621
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<64 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule622
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$zmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0, $zmm1
+#
+# TESTGEND:           %2:vecr(<8 x s64>) = COPY $zmm1
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule623
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule624
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(<2 x s64>) = COPY $xmm1
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule625
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ymm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0, $ymm1
+#
+# TESTGEND:           %2:vecr(<4 x s64>) = COPY $ymm1
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule626
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:         - { id: 2, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$xmm1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0, $xmm1
+#
+# TESTGEND:           %2:vecr(s128) = COPY $xmm1
+# TESTGEND:           %1:vecr(s128) = COPY $xmm0
+# TESTGEND:           %0:vecr(s128) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule627
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(<8 x s1>) = COPY $cl
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:gpr(<8 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule628
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(s1) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s1) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s1)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule629
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<2 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule630
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %2:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(<4 x s1>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule631
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cl', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al, $cl
+#
+# TESTGEND:           %2:gpr(s8) = COPY $cl
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s8) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule632
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$cx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax, $cx
+#
+# TESTGEND:           %2:gpr(s16) = COPY $cx
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule633
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$ecx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax, $ecx
+#
+# TESTGEND:           %2:gpr(s32) = COPY $ecx
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule634
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$rcx', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax, $rcx
+#
+# TESTGEND:           %2:gpr(s64) = COPY $rcx
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule635
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s32) = G_ANYEXT %1(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule636
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule637
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule638
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule639
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule640
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule641
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule642
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule643
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule644
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule645
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule646
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule647
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule648
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(<32 x s1>) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule649
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(<32 x s1>) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_BITCAST %1(<32 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule650
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(<64 x s1>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s1>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule651
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(<64 x s1>) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(<64 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule652
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule653
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule654
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule655
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule657
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule658
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule659
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule661
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule662
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule663
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule664
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<16 x s8>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule667
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule668
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule669
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<8 x s16>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule682
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(s128) = COPY $xmm0
+# TESTGEND:           %0:vecr(s128) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule684
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_BITCAST %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule685
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_BITCAST %1(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule686
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_BITCAST %1(<32 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule688
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_BITCAST %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule689
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_BITCAST %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule690
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_BITCAST %1(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule691
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_BITCAST %1(<32 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule693
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_BITCAST %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule694
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_BITCAST %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule695
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_BITCAST %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule696
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<32 x s8>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_BITCAST %1(<32 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule699
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_BITCAST %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule700
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_BITCAST %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule701
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_BITCAST %1(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule714
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_BITCAST %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule715
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_BITCAST %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule716
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_BITCAST %1(<32 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule717
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<64 x s8>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_BITCAST %1(<64 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule719
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_BITCAST %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule720
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_BITCAST %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule721
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_BITCAST %1(<32 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule722
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<64 x s8>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_BITCAST %1(<64 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule734
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_BITCAST %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule735
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_BITCAST %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule736
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<64 x s8>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s16>) = G_BITCAST %1(<64 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule740
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<64 x s8>) = G_BITCAST %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule741
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<64 x s8>) = G_BITCAST %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule742
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<64 x s8>) = G_BITCAST %1(<32 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule745
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s32) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule746
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:gpr(s64) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule747
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s16) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule748
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s8) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule749
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s16) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule750
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule751
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule752
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule753
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule754
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPEXT %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule755
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FPEXT %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule756
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPEXT %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule757
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule758
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule759
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule760
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule761
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s80) = G_FPEXT %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s80)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule762
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule763
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule764
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule765
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule766
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule767
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule768
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule769
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule770
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule771
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule772
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule773
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule774
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule775
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule776
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule777
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule778
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FPTOSI %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule779
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule780
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule781
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTOSI %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule782
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOSI %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule783
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FPTOSI %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule784
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule785
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPTOSI %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule786
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FPTOSI %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule787
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule788
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOUI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule789
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s32) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOUI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule790
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s32) = G_FPTOUI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule791
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:gpr(s64) = G_FPTOUI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule792
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_FPTOUI %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule793
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule794
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTOUI %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule795
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTOUI %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule796
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTOUI %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule797
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FPTOUI %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule798
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule799
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPTOUI %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule800
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_FPTOUI %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule801
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_FPTOUI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule802
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule803
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTRUNC %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule804
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_FPTRUNC %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule805
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_FPTRUNC %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule806
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule807
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule808
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s64) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule809
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s32) = G_FPTRUNC %1(s80)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule810
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(s80) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(s64) = G_FPTRUNC %1(s80)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule811
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s32) = G_SEXT %1(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule812
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s32) = G_SEXT %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule813
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s64) = G_SEXT %1(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule814
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s64) = G_SEXT %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule815
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s64) = G_SEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule816
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<64 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<64 x s8>) = G_SEXT %1(<64 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<64 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule817
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<32 x s8>) = G_SEXT %1(<32 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule818
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:vecr(<16 x s8>) = G_SEXT %1(<16 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule819
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:vecr(<32 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<32 x s16>) = G_SEXT %1(<32 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule820
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:vecr(<16 x s16>) = G_SEXT %1(<16 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule821
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:vecr(<8 x s16>) = G_SEXT %1(<8 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule822
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:vecr(<16 x s32>) = G_SEXT %1(<16 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule823
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SEXT %1(<8 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule824
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SEXT %1(<4 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule825
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(<8 x s1>) = COPY $al
+# TESTGEND:           %0:vecr(<8 x s64>) = G_SEXT %1(<8 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule826
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<4 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SEXT %1(<4 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule827
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:gpr(<2 x s1>) = IMPLICIT_DEF
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SEXT %1(<2 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule828
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:vecr(<16 x s8>) = G_SEXT %1(<16 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule829
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(<16 x s1>) = COPY $ax
+# TESTGEND:           %0:vecr(<16 x s16>) = G_SEXT %1(<16 x s1>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule830
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule831
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule832
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule833
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule834
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule835
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule836
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule837
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule838
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_SITOFP %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule839
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule840
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_SITOFP %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule841
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule842
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule843
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_SITOFP %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule844
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule845
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_SITOFP %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule846
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_SITOFP %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule847
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_SITOFP %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule848
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule849
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule850
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule851
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule852
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule853
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s32) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule854
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule855
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule856
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_TRUNC %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule857
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_TRUNC %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule858
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_TRUNC %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule859
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_TRUNC %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule860
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s16>) = G_TRUNC %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule861
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s16>) = G_TRUNC %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule862
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<16 x s16>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<16 x s8>) = G_TRUNC %1(<16 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule863
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<32 x s16>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<32 x s8>) = G_TRUNC %1(<32 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<32 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule864
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s16) = G_TRUNC %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule865
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:gpr(s8) = G_TRUNC %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule866
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s8) = G_TRUNC %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s8)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule867
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_UITOFP %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule868
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_UITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule869
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<16 x s32>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<16 x s32>) = G_UITOFP %1(<16 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule870
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<4 x s32>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule871
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<8 x s32>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_UITOFP %1(<8 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule872
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s64>) = G_UITOFP %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule873
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$xmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $xmm0
+#
+# TESTGEND:           %1:vecr(<2 x s64>) = COPY $xmm0
+# TESTGEND:           %0:vecr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule874
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s64>) = G_UITOFP %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule875
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$zmm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $zmm0
+#
+# TESTGEND:           %1:vecr(<8 x s64>) = COPY $zmm0
+# TESTGEND:           %0:vecr(<8 x s32>) = G_UITOFP %1(<8 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule876
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: vecr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ymm0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ymm0
+#
+# TESTGEND:           %1:vecr(<4 x s64>) = COPY $ymm0
+# TESTGEND:           %0:vecr(<4 x s32>) = G_UITOFP %1(<4 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule877
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s32) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule878
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s32) = G_UITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule879
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$eax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $eax
+#
+# TESTGEND:           %1:gpr(s32) = COPY $eax
+# TESTGEND:           %0:vecr(s64) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule880
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: vecr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$rax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $rax
+#
+# TESTGEND:           %1:gpr(s64) = COPY $rax
+# TESTGEND:           %0:vecr(s64) = G_UITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule881
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$al', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $al
+#
+# TESTGEND:           %1:gpr(s8) = COPY $al
+# TESTGEND:           %0:gpr(s32) = G_ZEXT %1(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule882
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$ax', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $ax
+#
+# TESTGEND:           %1:gpr(s16) = COPY $ax
+# TESTGEND:           %0:gpr(s32) = G_ZEXT %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule883
+# TESTGEND:       alignment:       4
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           successors:
+#
+# TESTGEND:           G_BR %bb.0
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...