Index: lib/Target/ARM/ARMInstructionSelector.cpp =================================================================== --- lib/Target/ARM/ARMInstructionSelector.cpp +++ lib/Target/ARM/ARMInstructionSelector.cpp @@ -134,6 +134,8 @@ return &ARM::SPRRegClass; else if (Size == 64) return &ARM::DPRRegClass; + else if (Size == 128) + return &ARM::QPRRegClass; else llvm_unreachable("Unsupported destination size"); } Index: lib/Target/ARM/ARMRegisterBankInfo.cpp =================================================================== --- lib/Target/ARM/ARMRegisterBankInfo.cpp +++ lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -175,15 +175,20 @@ switch (RC.getID()) { case GPRRegClassID: + case GPRwithAPSRRegClassID: case GPRnopcRegClassID: + case rGPRRegClassID: case GPRspRegClassID: case tGPR_and_tcGPRRegClassID: + case tcGPRRegClassID: case tGPRRegClassID: return getRegBank(ARM::GPRRegBankID); + case HPRRegClassID: case SPR_8RegClassID: case SPRRegClassID: case DPR_8RegClassID: case DPRRegClassID: + case QPRRegClassID: return getRegBank(ARM::FPRRegBankID); default: llvm_unreachable("Unsupported register kind"); Index: lib/Target/ARM/ARMRegisterBanks.td =================================================================== --- lib/Target/ARM/ARMRegisterBanks.td +++ lib/Target/ARM/ARMRegisterBanks.td @@ -11,4 +11,4 @@ //===----------------------------------------------------------------------===// def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>; -def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>; +def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;