Index: lib/Target/ARM/ARMInstructionSelector.cpp
===================================================================
--- lib/Target/ARM/ARMInstructionSelector.cpp
+++ lib/Target/ARM/ARMInstructionSelector.cpp
@@ -134,6 +134,8 @@
       return &ARM::SPRRegClass;
     else if (Size == 64)
       return &ARM::DPRRegClass;
+    else if (Size == 128)
+      return &ARM::QPRRegClass;
     else
       llvm_unreachable("Unsupported destination size");
   }
Index: lib/Target/ARM/ARMRegisterBankInfo.cpp
===================================================================
--- lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -175,15 +175,20 @@
 
   switch (RC.getID()) {
   case GPRRegClassID:
+  case GPRwithAPSRRegClassID:
   case GPRnopcRegClassID:
+  case rGPRRegClassID:
   case GPRspRegClassID:
   case tGPR_and_tcGPRRegClassID:
+  case tcGPRRegClassID:
   case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);
+  case HPRRegClassID:
   case SPR_8RegClassID:
   case SPRRegClassID:
   case DPR_8RegClassID:
   case DPRRegClassID:
+  case QPRRegClassID:
     return getRegBank(ARM::FPRRegBankID);
   default:
     llvm_unreachable("Unsupported register kind");
Index: lib/Target/ARM/ARMRegisterBanks.td
===================================================================
--- lib/Target/ARM/ARMRegisterBanks.td
+++ lib/Target/ARM/ARMRegisterBanks.td
@@ -11,4 +11,4 @@
 //===----------------------------------------------------------------------===//
 
 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
-def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>;
+def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
+++ test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
@@ -30,6 +30,16 @@
     unreachable
   }
 
+  define void @test_rule2_id1749_at_idx334() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule3_id1969_at_idx501() {
+  entry:
+    unreachable
+  }
+
   define void @test_rule4_id1713_at_idx668() {
   entry:
     unreachable
@@ -100,4005 +110,11844 @@
     unreachable
   }
 
-  define void @test_rule31_id1816_at_idx4333() {
+  define void @test_rule18_id2493_at_idx2296() {
   entry:
     unreachable
   }
 
-  define void @test_rule32_id1817_at_idx4394() {
+  define void @test_rule19_id2530_at_idx2460() {
   entry:
     unreachable
   }
 
-  define void @test_rule33_id1818_at_idx4455() {
+  define void @test_rule20_id2698_at_idx2624() {
   entry:
     unreachable
   }
 
-  define void @test_rule34_id1996_at_idx4516() {
+  define void @test_rule21_id2729_at_idx2788() {
   entry:
     unreachable
   }
 
-  define void @test_rule35_id1997_at_idx4577() {
+  define void @test_rule22_id2492_at_idx2952() {
   entry:
     unreachable
   }
 
-  define void @test_rule36_id1998_at_idx4638() {
+  define void @test_rule23_id2529_at_idx3116() {
   entry:
     unreachable
   }
 
-  define void @test_rule37_id1714_at_idx4699() {
+  define void @test_rule24_id205_at_idx3280() {
   entry:
     unreachable
   }
 
-  define void @test_rule38_id1911_at_idx4756() {
+  define void @test_rule25_id544_at_idx3444() {
   entry:
     unreachable
   }
 
-  define void @test_rule43_id265_at_idx5471() {
+  define void @test_rule26_id1754_at_idx3608() {
   entry:
     unreachable
   }
 
-  define void @test_rule44_id266_at_idx5637() {
+  define void @test_rule27_id1974_at_idx3772() {
   entry:
     unreachable
   }
 
-  define void @test_rule45_id606_at_idx5797() {
+  define void @test_rule28_id204_at_idx3936() {
   entry:
     unreachable
   }
 
-  define void @test_rule46_id607_at_idx5963() {
+  define void @test_rule29_id543_at_idx4100() {
   entry:
     unreachable
   }
 
-  define void @test_rule51_id188_at_idx6729() {
+  define void @test_rule30_id1917_at_idx4264() {
   entry:
     unreachable
   }
 
-  define void @test_rule52_id519_at_idx6847() {
+  define void @test_rule31_id1816_at_idx4333() {
   entry:
     unreachable
   }
 
-  define void @test_rule69_id267_at_idx9081() {
+  define void @test_rule32_id1817_at_idx4394() {
   entry:
     unreachable
   }
 
-  define void @test_rule70_id268_at_idx9211() {
+  define void @test_rule33_id1818_at_idx4455() {
   entry:
     unreachable
   }
 
-  define void @test_rule71_id608_at_idx9335() {
+  define void @test_rule34_id1996_at_idx4516() {
   entry:
     unreachable
   }
 
-  define void @test_rule72_id609_at_idx9465() {
+  define void @test_rule35_id1997_at_idx4577() {
   entry:
     unreachable
   }
 
-  define void @test_rule73_id2758_at_idx9595() {
+  define void @test_rule36_id1998_at_idx4638() {
   entry:
     unreachable
   }
 
-  define void @test_rule74_id2759_at_idx9697() {
+  define void @test_rule37_id1714_at_idx4699() {
   entry:
     unreachable
   }
 
-  define void @test_rule75_id2760_at_idx9799() {
+  define void @test_rule38_id1911_at_idx4756() {
   entry:
     unreachable
   }
 
-  define void @test_rule76_id2761_at_idx9901() {
+  define void @test_rule39_id1771_at_idx4813() {
   entry:
     unreachable
   }
 
-  define void @test_rule77_id2778_at_idx10003() {
+  define void @test_rule40_id1772_at_idx4979() {
   entry:
     unreachable
   }
 
-  define void @test_rule78_id2779_at_idx10103() {
+  define void @test_rule41_id1994_at_idx5139() {
   entry:
     unreachable
   }
 
-  define void @test_rule81_id2145_at_idx10393() {
+  define void @test_rule42_id1995_at_idx5305() {
   entry:
     unreachable
   }
 
-  define void @test_rule82_id2146_at_idx10495() {
+  define void @test_rule43_id265_at_idx5471() {
   entry:
     unreachable
   }
 
-  define void @test_rule83_id2147_at_idx10597() {
+  define void @test_rule44_id266_at_idx5637() {
   entry:
     unreachable
   }
 
-  define void @test_rule84_id2148_at_idx10699() {
+  define void @test_rule45_id606_at_idx5797() {
   entry:
     unreachable
   }
 
-  define void @test_rule85_id2153_at_idx10801() {
+  define void @test_rule46_id607_at_idx5963() {
   entry:
     unreachable
   }
 
-  define void @test_rule86_id2154_at_idx10903() {
+  define void @test_rule47_id2489_at_idx6129() {
   entry:
     unreachable
   }
 
-  define void @test_rule87_id2155_at_idx11005() {
+  define void @test_rule48_id2526_at_idx6279() {
   entry:
     unreachable
   }
 
-  define void @test_rule88_id2156_at_idx11107() {
+  define void @test_rule49_id194_at_idx6429() {
   entry:
     unreachable
   }
 
-  define void @test_rule89_id2161_at_idx11209() {
+  define void @test_rule50_id525_at_idx6579() {
   entry:
     unreachable
   }
 
-  define void @test_rule90_id2162_at_idx11309() {
+  define void @test_rule51_id188_at_idx6729() {
   entry:
     unreachable
   }
 
-  define void @test_rule91_id2168_at_idx11409() {
+  define void @test_rule52_id519_at_idx6847() {
   entry:
     unreachable
   }
 
-  define void @test_rule92_id2169_at_idx11509() {
+  define void @test_rule53_id1750_at_idx6965() {
   entry:
     unreachable
   }
 
-  define void @test_rule97_id203_at_idx11989() {
+  define void @test_rule54_id1970_at_idx7086() {
   entry:
     unreachable
   }
 
-  define void @test_rule110_id2651_at_idx13351() {
+  define void @test_rule55_id2694_at_idx7207() {
   entry:
     unreachable
   }
 
-  define void @test_rule111_id2652_at_idx13469() {
+  define void @test_rule56_id2725_at_idx7328() {
   entry:
     unreachable
   }
 
-  define void @test_rule112_id2653_at_idx13587() {
+  define void @test_rule57_id1753_at_idx7449() {
   entry:
     unreachable
   }
 
-  define void @test_rule113_id2654_at_idx13705() {
+  define void @test_rule58_id1973_at_idx7585() {
   entry:
     unreachable
   }
 
-  define void @test_rule114_id2655_at_idx13823() {
+  define void @test_rule59_id1752_at_idx7721() {
   entry:
     unreachable
   }
 
-  define void @test_rule115_id2656_at_idx13941() {
+  define void @test_rule60_id1972_at_idx7857() {
   entry:
     unreachable
   }
 
-  define void @test_rule116_id1150_at_idx14059() {
+  define void @test_rule61_id1751_at_idx7993() {
   entry:
     unreachable
   }
 
-  define void @test_rule117_id1151_at_idx14177() {
+  define void @test_rule62_id1971_at_idx8129() {
   entry:
     unreachable
   }
 
-  define void @test_rule118_id1152_at_idx14295() {
+  define void @test_rule63_id2697_at_idx8265() {
   entry:
     unreachable
   }
 
-  define void @test_rule119_id1153_at_idx14413() {
+  define void @test_rule64_id2728_at_idx8401() {
   entry:
     unreachable
   }
 
-  define void @test_rule120_id1154_at_idx14531() {
+  define void @test_rule65_id2696_at_idx8537() {
   entry:
     unreachable
   }
 
-  define void @test_rule121_id1155_at_idx14649() {
+  define void @test_rule66_id2727_at_idx8673() {
   entry:
     unreachable
   }
 
-  define void @test_rule124_id350_at_idx14917() {
+  define void @test_rule67_id2695_at_idx8809() {
   entry:
     unreachable
   }
 
-  define void @test_rule129_id2_at_idx15279() {
+  define void @test_rule68_id2726_at_idx8945() {
   entry:
     unreachable
   }
 
-  define void @test_rule130_id10_at_idx15340() {
+  define void @test_rule69_id267_at_idx9081() {
   entry:
     unreachable
   }
 
-  define void @test_rule131_id11_at_idx15401() {
+  define void @test_rule70_id268_at_idx9211() {
   entry:
     unreachable
   }
 
-  define void @test_rule132_id237_at_idx15456() {
+  define void @test_rule71_id608_at_idx9335() {
   entry:
     unreachable
   }
 
-  define void @test_rule133_id238_at_idx15511() {
+  define void @test_rule72_id609_at_idx9465() {
   entry:
     unreachable
   }
 
-  define void @test_rule134_id239_at_idx15566() {
+  define void @test_rule73_id2758_at_idx9595() {
   entry:
     unreachable
   }
 
-  define void @test_rule135_id285_at_idx15621() {
+  define void @test_rule74_id2759_at_idx9697() {
   entry:
     unreachable
   }
 
-  define void @test_rule136_id349_at_idx15682() {
+  define void @test_rule75_id2760_at_idx9799() {
   entry:
     unreachable
   }
 
-  define void @test_rule137_id498_at_idx15737() {
+  define void @test_rule76_id2761_at_idx9901() {
   entry:
     unreachable
   }
 
-  define void @test_rule138_id572_at_idx15792() {
+  define void @test_rule77_id2778_at_idx10003() {
   entry:
     unreachable
   }
 
-  define void @test_rule139_id573_at_idx15853() {
+  define void @test_rule78_id2779_at_idx10103() {
   entry:
     unreachable
   }
 
-  define void @test_rule140_id574_at_idx15914() {
+  define void @test_rule79_id111_at_idx10203() {
   entry:
     unreachable
   }
 
-  define void @test_rule141_id592_at_idx15975() {
+  define void @test_rule80_id1930_at_idx10298() {
   entry:
     unreachable
   }
 
-  define void @test_rule142_id593_at_idx16036() {
+  define void @test_rule81_id2145_at_idx10393() {
   entry:
     unreachable
   }
 
-  define void @test_rule143_id1611_at_idx16097() {
+  define void @test_rule82_id2146_at_idx10495() {
   entry:
     unreachable
   }
 
-  define void @test_rule144_id1612_at_idx16174() {
+  define void @test_rule83_id2147_at_idx10597() {
   entry:
     unreachable
   }
 
-  define void @test_rule145_id1613_at_idx16251() {
+  define void @test_rule84_id2148_at_idx10699() {
   entry:
     unreachable
   }
 
-  define void @test_rule146_id1614_at_idx16328() {
+  define void @test_rule85_id2153_at_idx10801() {
   entry:
     unreachable
   }
 
-  define void @test_rule147_id1615_at_idx16405() {
+  define void @test_rule86_id2154_at_idx10903() {
   entry:
     unreachable
   }
 
-  define void @test_rule148_id1616_at_idx16482() {
+  define void @test_rule87_id2155_at_idx11005() {
   entry:
     unreachable
   }
 
-  define void @test_rule149_id1617_at_idx16559() {
+  define void @test_rule88_id2156_at_idx11107() {
   entry:
     unreachable
   }
 
-  define void @test_rule150_id1618_at_idx16636() {
+  define void @test_rule89_id2161_at_idx11209() {
   entry:
     unreachable
   }
 
-  define void @test_rule151_id1619_at_idx16713() {
+  define void @test_rule90_id2162_at_idx11309() {
   entry:
     unreachable
   }
 
-  define void @test_rule152_id1620_at_idx16790() {
+  define void @test_rule91_id2168_at_idx11409() {
   entry:
     unreachable
   }
 
-  define void @test_rule153_id1621_at_idx16867() {
+  define void @test_rule92_id2169_at_idx11509() {
   entry:
     unreachable
   }
 
-  define void @test_rule154_id1622_at_idx16944() {
+  define void @test_rule93_id112_at_idx11609() {
   entry:
     unreachable
   }
 
-  define void @test_rule155_id1623_at_idx17021() {
+  define void @test_rule94_id1931_at_idx11704() {
   entry:
     unreachable
   }
 
-  define void @test_rule156_id1624_at_idx17098() {
+  define void @test_rule95_id2470_at_idx11799() {
   entry:
     unreachable
   }
 
-  define void @test_rule157_id1625_at_idx17175() {
+  define void @test_rule96_id2720_at_idx11894() {
   entry:
     unreachable
   }
 
-  define void @test_rule158_id1626_at_idx17252() {
+  define void @test_rule97_id203_at_idx11989() {
   entry:
     unreachable
   }
 
-  define void @test_rule159_id1684_at_idx17329() {
+  define void @test_rule98_id2479_at_idx12067() {
   entry:
     unreachable
   }
 
-  define void @test_rule160_id2639_at_idx17403() {
+  define void @test_rule99_id2512_at_idx12174() {
   entry:
     unreachable
   }
 
-  define void @test_rule161_id2640_at_idx17501() {
+  define void @test_rule100_id2478_at_idx12281() {
   entry:
     unreachable
   }
 
-  define void @test_rule162_id2641_at_idx17599() {
+  define void @test_rule101_id2511_at_idx12388() {
   entry:
     unreachable
   }
 
-  define void @test_rule163_id2642_at_idx17697() {
+  define void @test_rule102_id2477_at_idx12495() {
   entry:
     unreachable
   }
 
-  define void @test_rule164_id2643_at_idx17795() {
+  define void @test_rule103_id2510_at_idx12602() {
   entry:
     unreachable
   }
 
-  define void @test_rule165_id2644_at_idx17893() {
+  define void @test_rule104_id161_at_idx12709() {
   entry:
     unreachable
   }
 
-  define void @test_rule166_id2645_at_idx17991() {
+  define void @test_rule105_id494_at_idx12816() {
   entry:
     unreachable
   }
 
-  define void @test_rule167_id2646_at_idx18089() {
+  define void @test_rule106_id2517_at_idx12923() {
   entry:
     unreachable
   }
 
-  define void @test_rule168_id2647_at_idx18187() {
+  define void @test_rule107_id2516_at_idx13030() {
   entry:
     unreachable
   }
 
-  define void @test_rule169_id2648_at_idx18285() {
+  define void @test_rule108_id2515_at_idx13137() {
   entry:
     unreachable
   }
 
-  define void @test_rule170_id2649_at_idx18383() {
+  define void @test_rule109_id500_at_idx13244() {
   entry:
     unreachable
   }
 
-  define void @test_rule171_id2650_at_idx18481() {
+  define void @test_rule110_id2651_at_idx13351() {
   entry:
     unreachable
   }
 
-  define void @test_rule172_id1138_at_idx18579() {
+  define void @test_rule111_id2652_at_idx13469() {
   entry:
     unreachable
   }
 
-  define void @test_rule173_id1139_at_idx18677() {
+  define void @test_rule112_id2653_at_idx13587() {
   entry:
     unreachable
   }
 
-  define void @test_rule174_id1140_at_idx18775() {
+  define void @test_rule113_id2654_at_idx13705() {
   entry:
     unreachable
   }
 
-  define void @test_rule175_id1141_at_idx18873() {
+  define void @test_rule114_id2655_at_idx13823() {
   entry:
     unreachable
   }
 
-  define void @test_rule176_id1142_at_idx18971() {
+  define void @test_rule115_id2656_at_idx13941() {
   entry:
     unreachable
   }
 
-  define void @test_rule177_id1143_at_idx19069() {
+  define void @test_rule116_id1150_at_idx14059() {
   entry:
     unreachable
   }
 
-  define void @test_rule178_id1144_at_idx19167() {
+  define void @test_rule117_id1151_at_idx14177() {
   entry:
     unreachable
   }
 
-  define void @test_rule179_id1145_at_idx19265() {
+  define void @test_rule118_id1152_at_idx14295() {
   entry:
     unreachable
   }
 
-  define void @test_rule180_id1146_at_idx19363() {
+  define void @test_rule119_id1153_at_idx14413() {
   entry:
     unreachable
   }
 
-  define void @test_rule181_id1147_at_idx19461() {
+  define void @test_rule120_id1154_at_idx14531() {
   entry:
     unreachable
   }
 
-  define void @test_rule182_id1148_at_idx19559() {
+  define void @test_rule121_id1155_at_idx14649() {
   entry:
     unreachable
   }
 
-  define void @test_rule183_id1149_at_idx19657() {
+  define void @test_rule122_id2520_at_idx14767() {
   entry:
     unreachable
   }
 
-  define void @test_rule188_id336_at_idx20127() {
+  define void @test_rule123_id503_at_idx14842() {
   entry:
     unreachable
   }
 
-  define void @test_rule189_id542_at_idx20205() {
+  define void @test_rule124_id350_at_idx14917() {
   entry:
     unreachable
   }
 
-  define void @test_rule192_id1132_at_idx20469() {
+  define void @test_rule125_id1725_at_idx14953() {
   entry:
     unreachable
   }
 
-  define void @test_rule193_id1133_at_idx20555() {
+  define void @test_rule126_id1729_at_idx15036() {
   entry:
     unreachable
   }
 
-  define void @test_rule194_id1134_at_idx20641() {
+  define void @test_rule127_id1935_at_idx15116() {
   entry:
     unreachable
   }
 
-  define void @test_rule195_id1135_at_idx20727() {
+  define void @test_rule128_id1937_at_idx15199() {
   entry:
     unreachable
   }
 
-  define void @test_rule196_id1136_at_idx20813() {
+  define void @test_rule129_id2_at_idx15279() {
   entry:
     unreachable
   }
 
-  define void @test_rule197_id1137_at_idx20899() {
+  define void @test_rule130_id10_at_idx15340() {
   entry:
     unreachable
   }
 
-  define void @test_rule198_id2094_at_idx20985() {
+  define void @test_rule131_id11_at_idx15401() {
   entry:
     unreachable
   }
 
-  define void @test_rule199_id2095_at_idx21099() {
+  define void @test_rule132_id237_at_idx15456() {
   entry:
     unreachable
   }
 
-  define void @test_rule200_id758_at_idx21213() {
+  define void @test_rule133_id238_at_idx15511() {
   entry:
     unreachable
   }
 
-  define void @test_rule201_id759_at_idx21315() {
+  define void @test_rule134_id239_at_idx15566() {
   entry:
     unreachable
   }
 
-  define void @test_rule202_id760_at_idx21417() {
+  define void @test_rule135_id285_at_idx15621() {
   entry:
     unreachable
   }
 
-  define void @test_rule203_id761_at_idx21519() {
+  define void @test_rule136_id349_at_idx15682() {
   entry:
     unreachable
   }
 
-  define void @test_rule204_id762_at_idx21621() {
+  define void @test_rule137_id498_at_idx15737() {
   entry:
     unreachable
   }
 
-  define void @test_rule205_id763_at_idx21723() {
+  define void @test_rule138_id572_at_idx15792() {
   entry:
     unreachable
   }
 
-  define void @test_rule206_id941_at_idx21825() {
+  define void @test_rule139_id573_at_idx15853() {
   entry:
     unreachable
   }
 
-  define void @test_rule207_id942_at_idx21927() {
+  define void @test_rule140_id574_at_idx15914() {
   entry:
     unreachable
   }
 
-  define void @test_rule208_id943_at_idx22029() {
+  define void @test_rule141_id592_at_idx15975() {
   entry:
     unreachable
   }
 
-  define void @test_rule209_id944_at_idx22131() {
+  define void @test_rule142_id593_at_idx16036() {
   entry:
     unreachable
   }
 
-  define void @test_rule210_id945_at_idx22233() {
+  define void @test_rule143_id1611_at_idx16097() {
   entry:
     unreachable
   }
 
-  define void @test_rule211_id946_at_idx22335() {
+  define void @test_rule144_id1612_at_idx16174() {
   entry:
     unreachable
   }
 
-  define void @test_rule213_id2100_at_idx22498() {
+  define void @test_rule145_id1613_at_idx16251() {
   entry:
     unreachable
   }
 
-  define void @test_rule214_id2101_at_idx22612() {
+  define void @test_rule146_id1614_at_idx16328() {
   entry:
     unreachable
   }
 
-  define void @test_rule215_id2102_at_idx22726() {
+  define void @test_rule147_id1615_at_idx16405() {
   entry:
     unreachable
   }
 
-  define void @test_rule216_id2103_at_idx22840() {
+  define void @test_rule148_id1616_at_idx16482() {
   entry:
     unreachable
   }
 
-  define void @test_rule217_id148_at_idx22954() {
+  define void @test_rule149_id1617_at_idx16559() {
   entry:
     unreachable
   }
 
-  define void @test_rule218_id473_at_idx23032() {
+  define void @test_rule150_id1618_at_idx16636() {
   entry:
     unreachable
   }
 
-  define void @test_rule223_id1649_at_idx23422() {
+  define void @test_rule151_id1619_at_idx16713() {
   entry:
     unreachable
   }
 
-  define void @test_rule224_id1680_at_idx23500() {
+  define void @test_rule152_id1620_at_idx16790() {
   entry:
     unreachable
   }
 
-  define void @test_rule225_id1681_at_idx23572() {
+  define void @test_rule153_id1621_at_idx16867() {
   entry:
     unreachable
   }
 
-  define void @test_rule226_id1682_at_idx23644() {
+  define void @test_rule154_id1622_at_idx16944() {
   entry:
     unreachable
   }
 
-  define void @test_rule227_id1683_at_idx23716() {
+  define void @test_rule155_id1623_at_idx17021() {
   entry:
     unreachable
   }
 
-  define void @test_rule244_id2181_at_idx25036() {
+  define void @test_rule156_id1624_at_idx17098() {
   entry:
     unreachable
   }
 
-  define void @test_rule245_id2182_at_idx25114() {
+  define void @test_rule157_id1625_at_idx17175() {
   entry:
     unreachable
   }
 
-  define void @test_rule246_id2183_at_idx25192() {
+  define void @test_rule158_id1626_at_idx17252() {
   entry:
     unreachable
   }
 
-  define void @test_rule248_id2185_at_idx25348() {
+  define void @test_rule159_id1684_at_idx17329() {
   entry:
     unreachable
   }
 
-  define void @test_rule249_id2188_at_idx25426() {
+  define void @test_rule160_id2639_at_idx17403() {
   entry:
     unreachable
   }
 
-  define void @test_rule250_id2189_at_idx25504() {
+  define void @test_rule161_id2640_at_idx17501() {
   entry:
     unreachable
   }
 
-  define void @test_rule251_id2190_at_idx25582() {
+  define void @test_rule162_id2641_at_idx17599() {
   entry:
     unreachable
   }
 
-  define void @test_rule253_id2192_at_idx25738() {
+  define void @test_rule163_id2642_at_idx17697() {
   entry:
     unreachable
   }
 
-  define void @test_rule322_id770_at_idx30232() {
+  define void @test_rule164_id2643_at_idx17795() {
   entry:
     unreachable
   }
 
-  define void @test_rule323_id771_at_idx30298() {
+  define void @test_rule165_id2644_at_idx17893() {
   entry:
     unreachable
   }
 
-  define void @test_rule324_id772_at_idx30364() {
+  define void @test_rule166_id2645_at_idx17991() {
   entry:
     unreachable
   }
 
-  define void @test_rule325_id773_at_idx30430() {
+  define void @test_rule167_id2646_at_idx18089() {
   entry:
     unreachable
   }
 
-  define void @test_rule326_id774_at_idx30496() {
+  define void @test_rule168_id2647_at_idx18187() {
   entry:
     unreachable
   }
 
-  define void @test_rule327_id775_at_idx30562() {
+  define void @test_rule169_id2648_at_idx18285() {
   entry:
     unreachable
   }
 
-  define void @test_rule328_id776_at_idx30628() {
+  define void @test_rule170_id2649_at_idx18383() {
   entry:
     unreachable
   }
 
-  define void @test_rule329_id777_at_idx30694() {
+  define void @test_rule171_id2650_at_idx18481() {
   entry:
     unreachable
   }
 
-  define void @test_rule330_id778_at_idx30760() {
+  define void @test_rule172_id1138_at_idx18579() {
   entry:
     unreachable
   }
 
-  define void @test_rule331_id779_at_idx30826() {
+  define void @test_rule173_id1139_at_idx18677() {
   entry:
     unreachable
   }
 
-  define void @test_rule332_id780_at_idx30892() {
+  define void @test_rule174_id1140_at_idx18775() {
   entry:
     unreachable
   }
 
-  define void @test_rule333_id781_at_idx30958() {
+  define void @test_rule175_id1141_at_idx18873() {
   entry:
     unreachable
   }
 
-  define void @test_rule334_id782_at_idx31024() {
+  define void @test_rule176_id1142_at_idx18971() {
   entry:
     unreachable
   }
 
-  define void @test_rule335_id783_at_idx31090() {
+  define void @test_rule177_id1143_at_idx19069() {
   entry:
     unreachable
   }
 
-  define void @test_rule336_id784_at_idx31156() {
+  define void @test_rule178_id1144_at_idx19167() {
   entry:
     unreachable
   }
 
-  define void @test_rule337_id785_at_idx31222() {
+  define void @test_rule179_id1145_at_idx19265() {
   entry:
     unreachable
   }
 
-  define void @test_rule338_id786_at_idx31288() {
+  define void @test_rule180_id1146_at_idx19363() {
   entry:
     unreachable
   }
 
-  define void @test_rule339_id787_at_idx31354() {
+  define void @test_rule181_id1147_at_idx19461() {
   entry:
     unreachable
   }
 
-  define void @test_rule340_id788_at_idx31420() {
+  define void @test_rule182_id1148_at_idx19559() {
   entry:
     unreachable
   }
 
-  define void @test_rule341_id789_at_idx31486() {
+  define void @test_rule183_id1149_at_idx19657() {
   entry:
     unreachable
   }
 
-  define void @test_rule342_id790_at_idx31552() {
+  define void @test_rule184_id2480_at_idx19755() {
   entry:
     unreachable
   }
 
-  define void @test_rule343_id791_at_idx31618() {
+  define void @test_rule185_id2513_at_idx19848() {
   entry:
     unreachable
   }
 
-  define void @test_rule344_id792_at_idx31684() {
+  define void @test_rule186_id162_at_idx19941() {
   entry:
     unreachable
   }
 
-  define void @test_rule345_id793_at_idx31750() {
+  define void @test_rule187_id495_at_idx20034() {
   entry:
     unreachable
   }
 
-  define void @test_rule346_id794_at_idx31816() {
+  define void @test_rule188_id336_at_idx20127() {
   entry:
     unreachable
   }
 
-  define void @test_rule347_id795_at_idx31882() {
+  define void @test_rule189_id542_at_idx20205() {
   entry:
     unreachable
   }
 
-  define void @test_rule348_id796_at_idx31948() {
+  define void @test_rule190_id2518_at_idx20283() {
   entry:
     unreachable
   }
 
-  define void @test_rule349_id797_at_idx32014() {
+  define void @test_rule191_id501_at_idx20376() {
   entry:
     unreachable
   }
 
-  define void @test_rule350_id798_at_idx32080() {
+  define void @test_rule192_id1132_at_idx20469() {
   entry:
     unreachable
   }
 
-  define void @test_rule351_id799_at_idx32146() {
+  define void @test_rule193_id1133_at_idx20555() {
   entry:
     unreachable
   }
 
-  define void @test_rule352_id800_at_idx32212() {
+  define void @test_rule194_id1134_at_idx20641() {
   entry:
     unreachable
   }
 
-  define void @test_rule353_id801_at_idx32278() {
+  define void @test_rule195_id1135_at_idx20727() {
   entry:
     unreachable
   }
 
-  define void @test_rule354_id802_at_idx32344() {
+  define void @test_rule196_id1136_at_idx20813() {
   entry:
     unreachable
   }
 
-  define void @test_rule355_id803_at_idx32410() {
+  define void @test_rule197_id1137_at_idx20899() {
   entry:
     unreachable
   }
 
-  define void @test_rule356_id804_at_idx32476() {
+  define void @test_rule198_id2094_at_idx20985() {
   entry:
     unreachable
   }
 
-  define void @test_rule357_id805_at_idx32542() {
+  define void @test_rule199_id2095_at_idx21099() {
   entry:
     unreachable
   }
 
-  define void @test_rule358_id806_at_idx32608() {
+  define void @test_rule200_id758_at_idx21213() {
   entry:
     unreachable
   }
 
-  define void @test_rule359_id807_at_idx32674() {
+  define void @test_rule201_id759_at_idx21315() {
   entry:
     unreachable
   }
 
-  define void @test_rule360_id808_at_idx32740() {
+  define void @test_rule202_id760_at_idx21417() {
   entry:
     unreachable
   }
 
-  define void @test_rule361_id809_at_idx32806() {
+  define void @test_rule203_id761_at_idx21519() {
   entry:
     unreachable
   }
 
-  define void @test_rule362_id810_at_idx32872() {
+  define void @test_rule204_id762_at_idx21621() {
   entry:
     unreachable
   }
 
-  define void @test_rule363_id811_at_idx32938() {
+  define void @test_rule205_id763_at_idx21723() {
   entry:
     unreachable
   }
 
-  define void @test_rule364_id812_at_idx33004() {
+  define void @test_rule206_id941_at_idx21825() {
   entry:
     unreachable
   }
 
-  define void @test_rule365_id819_at_idx33070() {
+  define void @test_rule207_id942_at_idx21927() {
   entry:
     unreachable
   }
 
-  define void @test_rule366_id820_at_idx33136() {
+  define void @test_rule208_id943_at_idx22029() {
   entry:
     unreachable
   }
 
-  define void @test_rule367_id833_at_idx33202() {
+  define void @test_rule209_id944_at_idx22131() {
   entry:
     unreachable
   }
 
-  define void @test_rule368_id834_at_idx33268() {
+  define void @test_rule210_id945_at_idx22233() {
   entry:
     unreachable
   }
 
-  define void @test_rule369_id835_at_idx33334() {
+  define void @test_rule211_id946_at_idx22335() {
   entry:
     unreachable
   }
 
-  define void @test_rule370_id836_at_idx33400() {
+  define void @test_rule212_id504_at_idx22437() {
   entry:
     unreachable
   }
 
-  define void @test_rule371_id841_at_idx33466() {
+  define void @test_rule213_id2100_at_idx22498() {
   entry:
     unreachable
   }
 
-  define void @test_rule372_id842_at_idx33532() {
+  define void @test_rule214_id2101_at_idx22612() {
   entry:
     unreachable
   }
 
-  define void @test_rule373_id843_at_idx33598() {
+  define void @test_rule215_id2102_at_idx22726() {
   entry:
     unreachable
   }
 
-  define void @test_rule374_id844_at_idx33664() {
+  define void @test_rule216_id2103_at_idx22840() {
   entry:
     unreachable
   }
 
-  define void @test_rule375_id855_at_idx33730() {
+  define void @test_rule217_id148_at_idx22954() {
   entry:
     unreachable
   }
 
-  define void @test_rule376_id856_at_idx33796() {
+  define void @test_rule218_id473_at_idx23032() {
   entry:
     unreachable
   }
 
-  define void @test_rule377_id861_at_idx33856() {
+  define void @test_rule219_id532_at_idx23110() {
   entry:
     unreachable
   }
 
-  define void @test_rule378_id862_at_idx33922() {
+  define void @test_rule220_id533_at_idx23188() {
   entry:
     unreachable
   }
 
-  define void @test_rule379_id953_at_idx33988() {
+  define void @test_rule221_id534_at_idx23266() {
   entry:
     unreachable
   }
 
-  define void @test_rule380_id954_at_idx34054() {
+  define void @test_rule222_id535_at_idx23344() {
   entry:
     unreachable
   }
 
-  define void @test_rule381_id955_at_idx34120() {
+  define void @test_rule223_id1649_at_idx23422() {
   entry:
     unreachable
   }
 
-  define void @test_rule382_id956_at_idx34186() {
+  define void @test_rule224_id1680_at_idx23500() {
   entry:
     unreachable
   }
 
-  define void @test_rule383_id957_at_idx34252() {
+  define void @test_rule225_id1681_at_idx23572() {
   entry:
     unreachable
   }
 
-  define void @test_rule384_id958_at_idx34318() {
+  define void @test_rule226_id1682_at_idx23644() {
   entry:
     unreachable
   }
 
-  define void @test_rule385_id959_at_idx34384() {
+  define void @test_rule227_id1683_at_idx23716() {
   entry:
     unreachable
   }
 
-  define void @test_rule386_id960_at_idx34450() {
+  define void @test_rule228_id1735_at_idx23788() {
   entry:
     unreachable
   }
 
-  define void @test_rule387_id961_at_idx34516() {
+  define void @test_rule229_id1736_at_idx23866() {
   entry:
     unreachable
   }
 
-  define void @test_rule388_id962_at_idx34582() {
+  define void @test_rule230_id1737_at_idx23944() {
   entry:
     unreachable
   }
 
-  define void @test_rule389_id963_at_idx34648() {
+  define void @test_rule231_id1738_at_idx24022() {
   entry:
     unreachable
   }
 
-  define void @test_rule390_id964_at_idx34714() {
+  define void @test_rule232_id1809_at_idx24100() {
   entry:
     unreachable
   }
 
-  define void @test_rule391_id965_at_idx34780() {
+  define void @test_rule233_id1810_at_idx24178() {
   entry:
     unreachable
   }
 
-  define void @test_rule392_id966_at_idx34846() {
+  define void @test_rule234_id1811_at_idx24256() {
   entry:
     unreachable
   }
 
-  define void @test_rule393_id967_at_idx34912() {
+  define void @test_rule235_id1812_at_idx24334() {
   entry:
     unreachable
   }
 
-  define void @test_rule394_id968_at_idx34978() {
+  define void @test_rule236_id1813_at_idx24412() {
   entry:
     unreachable
   }
 
-  define void @test_rule395_id969_at_idx35044() {
+  define void @test_rule237_id1814_at_idx24490() {
   entry:
     unreachable
   }
 
-  define void @test_rule396_id970_at_idx35110() {
+  define void @test_rule238_id1955_at_idx24568() {
   entry:
     unreachable
   }
 
-  define void @test_rule397_id971_at_idx35176() {
+  define void @test_rule239_id1956_at_idx24646() {
   entry:
     unreachable
   }
 
-  define void @test_rule398_id972_at_idx35242() {
+  define void @test_rule240_id1957_at_idx24724() {
   entry:
     unreachable
   }
 
-  define void @test_rule399_id973_at_idx35308() {
+  define void @test_rule241_id1958_at_idx24802() {
   entry:
     unreachable
   }
 
-  define void @test_rule400_id974_at_idx35374() {
+  define void @test_rule242_id1959_at_idx24880() {
   entry:
     unreachable
   }
 
-  define void @test_rule401_id975_at_idx35440() {
+  define void @test_rule243_id1960_at_idx24958() {
   entry:
     unreachable
   }
 
-  define void @test_rule402_id976_at_idx35506() {
+  define void @test_rule244_id2181_at_idx25036() {
   entry:
     unreachable
   }
 
-  define void @test_rule403_id977_at_idx35572() {
+  define void @test_rule245_id2182_at_idx25114() {
   entry:
     unreachable
   }
 
-  define void @test_rule404_id978_at_idx35638() {
+  define void @test_rule246_id2183_at_idx25192() {
   entry:
     unreachable
   }
 
-  define void @test_rule405_id979_at_idx35704() {
+  define void @test_rule248_id2185_at_idx25348() {
   entry:
     unreachable
   }
 
-  define void @test_rule406_id980_at_idx35770() {
+  define void @test_rule249_id2188_at_idx25426() {
   entry:
     unreachable
   }
 
-  define void @test_rule407_id981_at_idx35836() {
+  define void @test_rule250_id2189_at_idx25504() {
   entry:
     unreachable
   }
 
-  define void @test_rule408_id982_at_idx35902() {
+  define void @test_rule251_id2190_at_idx25582() {
   entry:
     unreachable
   }
 
-  define void @test_rule409_id983_at_idx35968() {
+  define void @test_rule253_id2192_at_idx25738() {
   entry:
     unreachable
   }
 
-  define void @test_rule410_id1076_at_idx36034() {
+  define void @test_rule254_id107_at_idx25816() {
   entry:
     unreachable
   }
 
-  define void @test_rule411_id1077_at_idx36100() {
+  define void @test_rule255_id108_at_idx25882() {
   entry:
     unreachable
   }
 
-  define void @test_rule412_id1078_at_idx36166() {
+  define void @test_rule256_id109_at_idx25948() {
   entry:
     unreachable
   }
 
-  define void @test_rule413_id1079_at_idx36232() {
+  define void @test_rule257_id110_at_idx26014() {
   entry:
     unreachable
   }
 
-  define void @test_rule414_id1080_at_idx36298() {
+  define void @test_rule258_id113_at_idx26080() {
   entry:
     unreachable
   }
 
-  define void @test_rule415_id1081_at_idx36364() {
+  define void @test_rule259_id114_at_idx26146() {
   entry:
     unreachable
   }
 
-  define void @test_rule416_id1082_at_idx36430() {
+  define void @test_rule260_id115_at_idx26212() {
   entry:
     unreachable
   }
 
-  define void @test_rule417_id1083_at_idx36496() {
+  define void @test_rule261_id116_at_idx26278() {
   entry:
     unreachable
   }
 
-  define void @test_rule418_id1116_at_idx36562() {
+  define void @test_rule262_id117_at_idx26344() {
   entry:
     unreachable
   }
 
-  define void @test_rule419_id1117_at_idx36628() {
+  define void @test_rule263_id118_at_idx26410() {
   entry:
     unreachable
   }
 
-  define void @test_rule420_id1118_at_idx36694() {
+  define void @test_rule264_id119_at_idx26476() {
   entry:
     unreachable
   }
 
-  define void @test_rule421_id1119_at_idx36760() {
+  define void @test_rule265_id120_at_idx26542() {
   entry:
     unreachable
   }
 
-  define void @test_rule422_id1120_at_idx36826() {
+  define void @test_rule266_id121_at_idx26608() {
   entry:
     unreachable
   }
 
-  define void @test_rule423_id1121_at_idx36892() {
+  define void @test_rule267_id122_at_idx26674() {
   entry:
     unreachable
   }
 
-  define void @test_rule424_id1122_at_idx36958() {
+  define void @test_rule268_id135_at_idx26740() {
   entry:
     unreachable
   }
 
-  define void @test_rule425_id1123_at_idx37024() {
+  define void @test_rule269_id136_at_idx26806() {
   entry:
     unreachable
   }
 
-  define void @test_rule426_id1124_at_idx37090() {
+  define void @test_rule270_id137_at_idx26872() {
   entry:
     unreachable
   }
 
-  define void @test_rule427_id1125_at_idx37156() {
+  define void @test_rule271_id138_at_idx26938() {
   entry:
     unreachable
   }
 
-  define void @test_rule428_id1126_at_idx37222() {
+  define void @test_rule272_id139_at_idx27004() {
   entry:
     unreachable
   }
 
-  define void @test_rule429_id1127_at_idx37288() {
+  define void @test_rule273_id140_at_idx27070() {
   entry:
     unreachable
   }
 
-  define void @test_rule430_id1128_at_idx37354() {
+  define void @test_rule274_id141_at_idx27136() {
   entry:
     unreachable
   }
 
-  define void @test_rule431_id1129_at_idx37420() {
+  define void @test_rule275_id142_at_idx27202() {
   entry:
     unreachable
   }
 
-  define void @test_rule432_id1130_at_idx37486() {
+  define void @test_rule276_id143_at_idx27268() {
   entry:
     unreachable
   }
 
-  define void @test_rule433_id1131_at_idx37552() {
+  define void @test_rule277_id144_at_idx27334() {
   entry:
     unreachable
   }
 
-  define void @test_rule434_id1196_at_idx37618() {
+  define void @test_rule278_id145_at_idx27400() {
   entry:
     unreachable
   }
 
-  define void @test_rule435_id1197_at_idx37684() {
+  define void @test_rule279_id146_at_idx27466() {
   entry:
     unreachable
   }
 
-  define void @test_rule436_id1198_at_idx37750() {
+  define void @test_rule280_id147_at_idx27532() {
   entry:
     unreachable
   }
 
-  define void @test_rule437_id1199_at_idx37816() {
+  define void @test_rule281_id206_at_idx27598() {
   entry:
     unreachable
   }
 
-  define void @test_rule438_id1200_at_idx37882() {
+  define void @test_rule282_id207_at_idx27658() {
   entry:
     unreachable
   }
 
-  define void @test_rule439_id1213_at_idx37948() {
+  define void @test_rule283_id208_at_idx27718() {
   entry:
     unreachable
   }
 
-  define void @test_rule440_id1214_at_idx38014() {
+  define void @test_rule284_id209_at_idx27778() {
   entry:
     unreachable
   }
 
-  define void @test_rule441_id1215_at_idx38080() {
+  define void @test_rule285_id210_at_idx27838() {
   entry:
     unreachable
   }
 
-  define void @test_rule442_id1216_at_idx38146() {
+  define void @test_rule286_id211_at_idx27898() {
   entry:
     unreachable
   }
 
-  define void @test_rule443_id1217_at_idx38212() {
+  define void @test_rule287_id436_at_idx27958() {
   entry:
     unreachable
   }
 
-  define void @test_rule444_id1218_at_idx38278() {
+  define void @test_rule288_id437_at_idx28024() {
   entry:
     unreachable
   }
 
-  define void @test_rule445_id1219_at_idx38344() {
+  define void @test_rule289_id438_at_idx28090() {
   entry:
     unreachable
   }
 
-  define void @test_rule446_id1220_at_idx38410() {
+  define void @test_rule290_id439_at_idx28156() {
   entry:
     unreachable
   }
 
-  define void @test_rule447_id1221_at_idx38476() {
+  define void @test_rule291_id440_at_idx28222() {
   entry:
     unreachable
   }
 
-  define void @test_rule448_id1222_at_idx38542() {
+  define void @test_rule292_id441_at_idx28288() {
   entry:
     unreachable
   }
 
-  define void @test_rule449_id1223_at_idx38608() {
+  define void @test_rule293_id442_at_idx28354() {
   entry:
     unreachable
   }
 
-  define void @test_rule450_id1224_at_idx38674() {
+  define void @test_rule294_id443_at_idx28420() {
   entry:
     unreachable
   }
 
-  define void @test_rule451_id1225_at_idx38740() {
+  define void @test_rule295_id444_at_idx28486() {
   entry:
     unreachable
   }
 
-  define void @test_rule452_id1226_at_idx38806() {
+  define void @test_rule296_id445_at_idx28552() {
   entry:
     unreachable
   }
 
-  define void @test_rule453_id1227_at_idx38872() {
+  define void @test_rule297_id446_at_idx28618() {
   entry:
     unreachable
   }
 
-  define void @test_rule454_id1228_at_idx38938() {
+  define void @test_rule298_id447_at_idx28684() {
   entry:
     unreachable
   }
 
-  define void @test_rule455_id1229_at_idx39004() {
+  define void @test_rule299_id460_at_idx28750() {
   entry:
     unreachable
   }
 
-  define void @test_rule456_id1230_at_idx39070() {
+  define void @test_rule300_id461_at_idx28816() {
   entry:
     unreachable
   }
 
-  define void @test_rule457_id1231_at_idx39136() {
+  define void @test_rule301_id462_at_idx28882() {
   entry:
     unreachable
   }
 
-  define void @test_rule458_id1232_at_idx39202() {
+  define void @test_rule302_id463_at_idx28948() {
   entry:
     unreachable
   }
 
-  define void @test_rule459_id1233_at_idx39268() {
+  define void @test_rule303_id464_at_idx29014() {
   entry:
     unreachable
   }
 
-  define void @test_rule460_id1234_at_idx39334() {
+  define void @test_rule304_id465_at_idx29080() {
   entry:
     unreachable
   }
 
-  define void @test_rule461_id1235_at_idx39400() {
+  define void @test_rule305_id466_at_idx29146() {
   entry:
     unreachable
   }
 
-  define void @test_rule462_id1236_at_idx39466() {
+  define void @test_rule306_id467_at_idx29212() {
   entry:
     unreachable
   }
 
-  define void @test_rule463_id1237_at_idx39532() {
+  define void @test_rule307_id468_at_idx29278() {
   entry:
     unreachable
   }
 
-  define void @test_rule464_id1238_at_idx39598() {
+  define void @test_rule308_id469_at_idx29344() {
   entry:
     unreachable
   }
 
-  define void @test_rule465_id1239_at_idx39664() {
+  define void @test_rule309_id470_at_idx29410() {
   entry:
     unreachable
   }
 
-  define void @test_rule466_id1240_at_idx39730() {
+  define void @test_rule310_id471_at_idx29476() {
   entry:
     unreachable
   }
 
-  define void @test_rule467_id1247_at_idx39796() {
+  define void @test_rule311_id472_at_idx29542() {
   entry:
     unreachable
   }
 
-  define void @test_rule468_id1248_at_idx39862() {
+  define void @test_rule312_id528_at_idx29608() {
   entry:
     unreachable
   }
 
-  define void @test_rule469_id1249_at_idx39928() {
+  define void @test_rule313_id529_at_idx29674() {
   entry:
     unreachable
   }
 
-  define void @test_rule470_id1250_at_idx39994() {
+  define void @test_rule314_id530_at_idx29740() {
   entry:
     unreachable
   }
 
-  define void @test_rule471_id1257_at_idx40060() {
+  define void @test_rule315_id531_at_idx29806() {
   entry:
     unreachable
   }
 
-  define void @test_rule472_id1258_at_idx40126() {
+  define void @test_rule316_id545_at_idx29872() {
   entry:
     unreachable
   }
 
-  define void @test_rule473_id1259_at_idx40192() {
+  define void @test_rule317_id546_at_idx29932() {
   entry:
     unreachable
   }
 
-  define void @test_rule474_id1260_at_idx40258() {
+  define void @test_rule318_id547_at_idx29992() {
   entry:
     unreachable
   }
 
-  define void @test_rule475_id1261_at_idx40324() {
+  define void @test_rule319_id548_at_idx30052() {
   entry:
     unreachable
   }
 
-  define void @test_rule476_id1262_at_idx40390() {
+  define void @test_rule320_id549_at_idx30112() {
   entry:
     unreachable
   }
 
-  define void @test_rule477_id1263_at_idx40456() {
+  define void @test_rule321_id550_at_idx30172() {
   entry:
     unreachable
   }
 
-  define void @test_rule478_id1264_at_idx40522() {
+  define void @test_rule322_id770_at_idx30232() {
   entry:
     unreachable
   }
 
-  define void @test_rule479_id1265_at_idx40588() {
+  define void @test_rule323_id771_at_idx30298() {
   entry:
     unreachable
   }
 
-  define void @test_rule480_id1266_at_idx40654() {
+  define void @test_rule324_id772_at_idx30364() {
   entry:
     unreachable
   }
 
-  define void @test_rule481_id1267_at_idx40720() {
+  define void @test_rule325_id773_at_idx30430() {
   entry:
     unreachable
   }
 
-  define void @test_rule482_id1268_at_idx40786() {
+  define void @test_rule326_id774_at_idx30496() {
   entry:
     unreachable
   }
 
-  define void @test_rule483_id1269_at_idx40852() {
+  define void @test_rule327_id775_at_idx30562() {
   entry:
     unreachable
   }
 
-  define void @test_rule484_id1270_at_idx40918() {
+  define void @test_rule328_id776_at_idx30628() {
   entry:
     unreachable
   }
 
-  define void @test_rule485_id1271_at_idx40984() {
+  define void @test_rule329_id777_at_idx30694() {
   entry:
     unreachable
   }
 
-  define void @test_rule486_id1272_at_idx41050() {
+  define void @test_rule330_id778_at_idx30760() {
   entry:
     unreachable
   }
 
-  define void @test_rule487_id1273_at_idx41116() {
+  define void @test_rule331_id779_at_idx30826() {
   entry:
     unreachable
   }
 
-  define void @test_rule488_id1274_at_idx41182() {
+  define void @test_rule332_id780_at_idx30892() {
   entry:
     unreachable
   }
 
-  define void @test_rule489_id1275_at_idx41248() {
+  define void @test_rule333_id781_at_idx30958() {
   entry:
     unreachable
   }
 
-  define void @test_rule490_id1276_at_idx41314() {
+  define void @test_rule334_id782_at_idx31024() {
   entry:
     unreachable
   }
 
-  define void @test_rule491_id1310_at_idx41380() {
+  define void @test_rule335_id783_at_idx31090() {
   entry:
     unreachable
   }
 
-  define void @test_rule492_id1311_at_idx41446() {
+  define void @test_rule336_id784_at_idx31156() {
   entry:
     unreachable
   }
 
-  define void @test_rule493_id1312_at_idx41512() {
+  define void @test_rule337_id785_at_idx31222() {
   entry:
     unreachable
   }
 
-  define void @test_rule494_id1313_at_idx41578() {
+  define void @test_rule338_id786_at_idx31288() {
   entry:
     unreachable
   }
 
-  define void @test_rule495_id1314_at_idx41644() {
+  define void @test_rule339_id787_at_idx31354() {
   entry:
     unreachable
   }
 
-  define void @test_rule496_id1315_at_idx41710() {
+  define void @test_rule340_id788_at_idx31420() {
   entry:
     unreachable
   }
 
-  define void @test_rule497_id1316_at_idx41776() {
+  define void @test_rule341_id789_at_idx31486() {
   entry:
     unreachable
   }
 
-  define void @test_rule498_id1317_at_idx41842() {
+  define void @test_rule342_id790_at_idx31552() {
   entry:
     unreachable
   }
 
-  define void @test_rule499_id1318_at_idx41908() {
+  define void @test_rule343_id791_at_idx31618() {
   entry:
     unreachable
   }
 
-  define void @test_rule500_id1319_at_idx41974() {
+  define void @test_rule344_id792_at_idx31684() {
   entry:
     unreachable
   }
 
-  define void @test_rule501_id1320_at_idx42040() {
+  define void @test_rule345_id793_at_idx31750() {
   entry:
     unreachable
   }
 
-  define void @test_rule502_id1321_at_idx42106() {
+  define void @test_rule346_id794_at_idx31816() {
   entry:
     unreachable
   }
 
-  define void @test_rule503_id1322_at_idx42172() {
+  define void @test_rule347_id795_at_idx31882() {
   entry:
     unreachable
   }
 
-  define void @test_rule504_id1323_at_idx42238() {
+  define void @test_rule348_id796_at_idx31948() {
   entry:
     unreachable
   }
 
-  define void @test_rule505_id1324_at_idx42304() {
+  define void @test_rule349_id797_at_idx32014() {
   entry:
     unreachable
   }
 
-  define void @test_rule506_id1325_at_idx42370() {
+  define void @test_rule350_id798_at_idx32080() {
   entry:
     unreachable
   }
 
-  define void @test_rule507_id1345_at_idx42436() {
+  define void @test_rule351_id799_at_idx32146() {
   entry:
     unreachable
   }
 
-  define void @test_rule508_id1346_at_idx42502() {
+  define void @test_rule352_id800_at_idx32212() {
   entry:
     unreachable
   }
 
-  define void @test_rule509_id1347_at_idx42568() {
+  define void @test_rule353_id801_at_idx32278() {
   entry:
     unreachable
   }
 
-  define void @test_rule510_id1348_at_idx42634() {
+  define void @test_rule354_id802_at_idx32344() {
   entry:
     unreachable
   }
 
-  define void @test_rule511_id1349_at_idx42700() {
+  define void @test_rule355_id803_at_idx32410() {
   entry:
     unreachable
   }
 
-  define void @test_rule512_id1350_at_idx42766() {
+  define void @test_rule356_id804_at_idx32476() {
   entry:
     unreachable
   }
 
-  define void @test_rule513_id1351_at_idx42832() {
+  define void @test_rule357_id805_at_idx32542() {
   entry:
     unreachable
   }
 
-  define void @test_rule514_id1352_at_idx42898() {
+  define void @test_rule358_id806_at_idx32608() {
   entry:
     unreachable
   }
 
-  define void @test_rule515_id1353_at_idx42964() {
+  define void @test_rule359_id807_at_idx32674() {
   entry:
     unreachable
   }
 
-  define void @test_rule516_id1354_at_idx43030() {
+  define void @test_rule360_id808_at_idx32740() {
   entry:
     unreachable
   }
 
-  define void @test_rule517_id1355_at_idx43096() {
+  define void @test_rule361_id809_at_idx32806() {
   entry:
     unreachable
   }
 
-  define void @test_rule518_id1356_at_idx43162() {
+  define void @test_rule362_id810_at_idx32872() {
   entry:
     unreachable
   }
 
-  define void @test_rule519_id1357_at_idx43228() {
+  define void @test_rule363_id811_at_idx32938() {
   entry:
     unreachable
   }
 
-  define void @test_rule520_id1358_at_idx43294() {
+  define void @test_rule364_id812_at_idx33004() {
   entry:
     unreachable
   }
 
-  define void @test_rule521_id1359_at_idx43360() {
+  define void @test_rule365_id819_at_idx33070() {
   entry:
     unreachable
   }
 
-  define void @test_rule522_id1360_at_idx43426() {
+  define void @test_rule366_id820_at_idx33136() {
   entry:
     unreachable
   }
 
-  define void @test_rule523_id1394_at_idx43492() {
+  define void @test_rule367_id833_at_idx33202() {
   entry:
     unreachable
   }
 
-  define void @test_rule524_id1395_at_idx43558() {
+  define void @test_rule368_id834_at_idx33268() {
   entry:
     unreachable
   }
 
-  define void @test_rule525_id1396_at_idx43624() {
+  define void @test_rule369_id835_at_idx33334() {
   entry:
     unreachable
   }
 
-  define void @test_rule526_id1397_at_idx43690() {
+  define void @test_rule370_id836_at_idx33400() {
   entry:
     unreachable
   }
 
-  define void @test_rule527_id1398_at_idx43756() {
+  define void @test_rule371_id841_at_idx33466() {
   entry:
     unreachable
   }
 
-  define void @test_rule528_id1399_at_idx43822() {
+  define void @test_rule372_id842_at_idx33532() {
   entry:
     unreachable
   }
 
-  define void @test_rule529_id1400_at_idx43888() {
+  define void @test_rule373_id843_at_idx33598() {
   entry:
     unreachable
   }
 
-  define void @test_rule530_id1401_at_idx43954() {
+  define void @test_rule374_id844_at_idx33664() {
   entry:
     unreachable
   }
 
-  define void @test_rule531_id1402_at_idx44020() {
+  define void @test_rule375_id855_at_idx33730() {
   entry:
     unreachable
   }
 
-  define void @test_rule532_id1403_at_idx44086() {
+  define void @test_rule376_id856_at_idx33796() {
   entry:
     unreachable
   }
 
-  define void @test_rule533_id1404_at_idx44152() {
+  define void @test_rule377_id861_at_idx33856() {
   entry:
     unreachable
   }
 
-  define void @test_rule534_id1405_at_idx44218() {
+  define void @test_rule378_id862_at_idx33922() {
   entry:
     unreachable
   }
 
-  define void @test_rule535_id1406_at_idx44284() {
+  define void @test_rule379_id953_at_idx33988() {
   entry:
     unreachable
   }
 
-  define void @test_rule536_id1407_at_idx44350() {
+  define void @test_rule380_id954_at_idx34054() {
   entry:
     unreachable
   }
 
-  define void @test_rule537_id1408_at_idx44416() {
+  define void @test_rule381_id955_at_idx34120() {
   entry:
     unreachable
   }
 
-  define void @test_rule538_id1409_at_idx44482() {
+  define void @test_rule382_id956_at_idx34186() {
   entry:
     unreachable
   }
 
-  define void @test_rule539_id1674_at_idx44548() {
+  define void @test_rule383_id957_at_idx34252() {
   entry:
     unreachable
   }
 
-  define void @test_rule540_id1675_at_idx44608() {
+  define void @test_rule384_id958_at_idx34318() {
   entry:
     unreachable
   }
 
-  define void @test_rule541_id1678_at_idx44668() {
+  define void @test_rule385_id959_at_idx34384() {
   entry:
     unreachable
   }
 
-  define void @test_rule542_id1679_at_idx44728() {
+  define void @test_rule386_id960_at_idx34450() {
   entry:
     unreachable
   }
 
-  define void @test_rule564_id3_at_idx46183() {
+  define void @test_rule387_id961_at_idx34516() {
   entry:
     unreachable
   }
 
-  define void @test_rule565_id123_at_idx46253() {
+  define void @test_rule388_id962_at_idx34582() {
   entry:
     unreachable
   }
 
-  define void @test_rule566_id124_at_idx46323() {
+  define void @test_rule389_id963_at_idx34648() {
   entry:
     unreachable
   }
 
-  define void @test_rule567_id125_at_idx46393() {
+  define void @test_rule390_id964_at_idx34714() {
   entry:
     unreachable
   }
 
-  define void @test_rule568_id126_at_idx46463() {
+  define void @test_rule391_id965_at_idx34780() {
   entry:
     unreachable
   }
 
-  define void @test_rule569_id127_at_idx46533() {
+  define void @test_rule392_id966_at_idx34846() {
   entry:
     unreachable
   }
 
-  define void @test_rule570_id128_at_idx46603() {
+  define void @test_rule393_id967_at_idx34912() {
   entry:
     unreachable
   }
 
-  define void @test_rule571_id129_at_idx46673() {
+  define void @test_rule394_id968_at_idx34978() {
   entry:
     unreachable
   }
 
-  define void @test_rule572_id130_at_idx46743() {
+  define void @test_rule395_id969_at_idx35044() {
   entry:
     unreachable
   }
 
-  define void @test_rule573_id131_at_idx46813() {
+  define void @test_rule396_id970_at_idx35110() {
   entry:
     unreachable
   }
 
-  define void @test_rule574_id132_at_idx46883() {
+  define void @test_rule397_id971_at_idx35176() {
   entry:
     unreachable
   }
 
-  define void @test_rule575_id133_at_idx46953() {
+  define void @test_rule398_id972_at_idx35242() {
   entry:
     unreachable
   }
 
-  define void @test_rule576_id134_at_idx47023() {
+  define void @test_rule399_id973_at_idx35308() {
   entry:
     unreachable
   }
 
-  define void @test_rule577_id435_at_idx47093() {
+  define void @test_rule400_id974_at_idx35374() {
   entry:
     unreachable
   }
 
-  define void @test_rule578_id448_at_idx47163() {
+  define void @test_rule401_id975_at_idx35440() {
   entry:
     unreachable
   }
 
-  define void @test_rule579_id449_at_idx47233() {
+  define void @test_rule402_id976_at_idx35506() {
   entry:
     unreachable
   }
 
-  define void @test_rule580_id450_at_idx47303() {
+  define void @test_rule403_id977_at_idx35572() {
   entry:
     unreachable
   }
 
-  define void @test_rule581_id451_at_idx47373() {
+  define void @test_rule404_id978_at_idx35638() {
   entry:
     unreachable
   }
 
-  define void @test_rule582_id452_at_idx47443() {
+  define void @test_rule405_id979_at_idx35704() {
   entry:
     unreachable
   }
 
-  define void @test_rule583_id453_at_idx47513() {
+  define void @test_rule406_id980_at_idx35770() {
   entry:
     unreachable
   }
 
-  define void @test_rule584_id454_at_idx47583() {
+  define void @test_rule407_id981_at_idx35836() {
   entry:
     unreachable
   }
 
-  define void @test_rule585_id455_at_idx47653() {
+  define void @test_rule408_id982_at_idx35902() {
   entry:
     unreachable
   }
 
-  define void @test_rule586_id456_at_idx47723() {
+  define void @test_rule409_id983_at_idx35968() {
   entry:
     unreachable
   }
 
-  define void @test_rule587_id457_at_idx47793() {
+  define void @test_rule410_id1076_at_idx36034() {
   entry:
     unreachable
   }
 
-  define void @test_rule588_id458_at_idx47863() {
+  define void @test_rule411_id1077_at_idx36100() {
   entry:
     unreachable
   }
 
-  define void @test_rule589_id459_at_idx47933() {
+  define void @test_rule412_id1078_at_idx36166() {
   entry:
     unreachable
   }
 
-  define void @test_rule590_id351_at_idx48003() {
+  define void @test_rule413_id1079_at_idx36232() {
   entry:
     unreachable
   }
 
-  define void @test_rule591_id352_at_idx48061() {
+  define void @test_rule414_id1080_at_idx36298() {
   entry:
     unreachable
   }
 
-  define void @test_rule596_id1201_at_idx48335() {
+  define void @test_rule415_id1081_at_idx36364() {
   entry:
     unreachable
   }
 
-  define void @test_rule597_id1202_at_idx48389() {
+  define void @test_rule416_id1082_at_idx36430() {
   entry:
     unreachable
   }
 
-  define void @test_rule598_id1203_at_idx48443() {
+  define void @test_rule417_id1083_at_idx36496() {
   entry:
     unreachable
   }
 
-  define void @test_rule599_id1204_at_idx48497() {
+  define void @test_rule418_id1116_at_idx36562() {
   entry:
     unreachable
   }
 
-  define void @test_rule600_id1205_at_idx48551() {
+  define void @test_rule419_id1117_at_idx36628() {
   entry:
     unreachable
   }
 
-  define void @test_rule601_id1206_at_idx48605() {
+  define void @test_rule420_id1118_at_idx36694() {
   entry:
     unreachable
   }
 
-  define void @test_rule602_id1207_at_idx48659() {
+  define void @test_rule421_id1119_at_idx36760() {
   entry:
     unreachable
   }
 
-  define void @test_rule603_id1208_at_idx48713() {
+  define void @test_rule422_id1120_at_idx36826() {
   entry:
     unreachable
   }
 
-  define void @test_rule604_id1209_at_idx48767() {
+  define void @test_rule423_id1121_at_idx36892() {
   entry:
     unreachable
   }
 
-  define void @test_rule605_id1210_at_idx48821() {
+  define void @test_rule424_id1122_at_idx36958() {
   entry:
     unreachable
   }
 
-  define void @test_rule606_id1211_at_idx48875() {
+  define void @test_rule425_id1123_at_idx37024() {
   entry:
     unreachable
   }
 
-  define void @test_rule607_id1212_at_idx48929() {
+  define void @test_rule426_id1124_at_idx37090() {
   entry:
     unreachable
   }
 
-  define void @test_rule608_id1241_at_idx48983() {
+  define void @test_rule427_id1125_at_idx37156() {
   entry:
     unreachable
   }
 
-  define void @test_rule609_id1242_at_idx49037() {
+  define void @test_rule428_id1126_at_idx37222() {
   entry:
     unreachable
   }
 
-  define void @test_rule610_id1243_at_idx49091() {
+  define void @test_rule429_id1127_at_idx37288() {
   entry:
     unreachable
   }
 
-  define void @test_rule611_id1244_at_idx49145() {
+  define void @test_rule430_id1128_at_idx37354() {
   entry:
     unreachable
   }
 
-  define void @test_rule612_id1245_at_idx49199() {
+  define void @test_rule431_id1129_at_idx37420() {
   entry:
     unreachable
   }
 
-  define void @test_rule613_id1246_at_idx49253() {
+  define void @test_rule432_id1130_at_idx37486() {
   entry:
     unreachable
   }
 
-  define void @test_rule614_id1251_at_idx49307() {
+  define void @test_rule433_id1131_at_idx37552() {
   entry:
     unreachable
   }
 
-  define void @test_rule615_id1252_at_idx49361() {
+  define void @test_rule434_id1196_at_idx37618() {
   entry:
     unreachable
   }
 
-  define void @test_rule616_id1253_at_idx49415() {
+  define void @test_rule435_id1197_at_idx37684() {
   entry:
     unreachable
   }
 
-  define void @test_rule617_id1254_at_idx49469() {
+  define void @test_rule436_id1198_at_idx37750() {
   entry:
     unreachable
   }
 
-  define void @test_rule618_id1255_at_idx49523() {
+  define void @test_rule437_id1199_at_idx37816() {
   entry:
     unreachable
   }
 
-  define void @test_rule619_id1256_at_idx49577() {
+  define void @test_rule438_id1200_at_idx37882() {
   entry:
     unreachable
   }
 
-  define void @test_rule620_id1477_at_idx49631() {
+  define void @test_rule439_id1213_at_idx37948() {
   entry:
     unreachable
   }
 
-  define void @test_rule621_id1478_at_idx49685() {
+  define void @test_rule440_id1214_at_idx38014() {
   entry:
     unreachable
   }
 
-  define void @test_rule622_id1479_at_idx49739() {
+  define void @test_rule441_id1215_at_idx38080() {
   entry:
     unreachable
   }
 
-  define void @test_rule623_id1480_at_idx49793() {
+  define void @test_rule442_id1216_at_idx38146() {
   entry:
     unreachable
   }
 
-  define void @test_rule624_id1481_at_idx49847() {
+  define void @test_rule443_id1217_at_idx38212() {
   entry:
     unreachable
   }
 
-  define void @test_rule625_id1482_at_idx49901() {
+  define void @test_rule444_id1218_at_idx38278() {
   entry:
     unreachable
   }
 
-  define void @test_rule626_id1493_at_idx49955() {
+  define void @test_rule445_id1219_at_idx38344() {
   entry:
     unreachable
   }
 
-  define void @test_rule627_id1494_at_idx50009() {
+  define void @test_rule446_id1220_at_idx38410() {
   entry:
     unreachable
   }
 
-  define void @test_rule628_id1495_at_idx50063() {
+  define void @test_rule447_id1221_at_idx38476() {
   entry:
     unreachable
   }
 
-  define void @test_rule629_id1496_at_idx50117() {
+  define void @test_rule448_id1222_at_idx38542() {
   entry:
     unreachable
   }
 
-  define void @test_rule630_id1497_at_idx50171() {
+  define void @test_rule449_id1223_at_idx38608() {
   entry:
     unreachable
   }
 
-  define void @test_rule631_id1498_at_idx50225() {
+  define void @test_rule450_id1224_at_idx38674() {
   entry:
     unreachable
   }
 
-  define void @test_rule632_id1499_at_idx50279() {
+  define void @test_rule451_id1225_at_idx38740() {
   entry:
     unreachable
   }
 
-  define void @test_rule633_id1500_at_idx50333() {
+  define void @test_rule452_id1226_at_idx38806() {
   entry:
     unreachable
   }
 
-  define void @test_rule634_id1501_at_idx50387() {
+  define void @test_rule453_id1227_at_idx38872() {
   entry:
     unreachable
   }
 
-  define void @test_rule635_id1502_at_idx50441() {
+  define void @test_rule454_id1228_at_idx38938() {
   entry:
     unreachable
   }
 
-  define void @test_rule636_id1503_at_idx50495() {
+  define void @test_rule455_id1229_at_idx39004() {
   entry:
     unreachable
   }
 
-  define void @test_rule637_id1504_at_idx50549() {
+  define void @test_rule456_id1230_at_idx39070() {
   entry:
     unreachable
   }
 
-  define void @test_rule638_id1548_at_idx50603() {
+  define void @test_rule457_id1231_at_idx39136() {
   entry:
     unreachable
   }
 
-  define void @test_rule639_id1549_at_idx50657() {
+  define void @test_rule458_id1232_at_idx39202() {
   entry:
     unreachable
   }
 
-  define void @test_rule640_id1550_at_idx50711() {
+  define void @test_rule459_id1233_at_idx39268() {
   entry:
     unreachable
   }
 
-  define void @test_rule641_id1551_at_idx50765() {
+  define void @test_rule460_id1234_at_idx39334() {
   entry:
     unreachable
   }
 
-  define void @test_rule642_id1552_at_idx50819() {
+  define void @test_rule461_id1235_at_idx39400() {
   entry:
     unreachable
   }
 
-  define void @test_rule643_id1553_at_idx50873() {
+  define void @test_rule462_id1236_at_idx39466() {
   entry:
     unreachable
   }
 
-  define void @test_rule644_id1554_at_idx50927() {
+  define void @test_rule463_id1237_at_idx39532() {
   entry:
     unreachable
   }
 
-  define void @test_rule645_id1555_at_idx50981() {
+  define void @test_rule464_id1238_at_idx39598() {
   entry:
     unreachable
   }
 
-  define void @test_rule646_id1556_at_idx51035() {
+  define void @test_rule465_id1239_at_idx39664() {
   entry:
     unreachable
   }
 
-  define void @test_rule647_id1579_at_idx51089() {
+  define void @test_rule466_id1240_at_idx39730() {
   entry:
     unreachable
   }
 
-  define void @test_rule648_id1580_at_idx51137() {
+  define void @test_rule467_id1247_at_idx39796() {
   entry:
     unreachable
   }
 
-  define void @test_rule649_id1581_at_idx51185() {
+  define void @test_rule468_id1248_at_idx39862() {
   entry:
     unreachable
   }
 
-  define void @test_rule650_id1582_at_idx51233() {
+  define void @test_rule469_id1249_at_idx39928() {
   entry:
     unreachable
   }
 
-  define void @test_rule651_id1583_at_idx51281() {
+  define void @test_rule470_id1250_at_idx39994() {
   entry:
     unreachable
   }
 
-  define void @test_rule652_id1584_at_idx51329() {
+  define void @test_rule471_id1257_at_idx40060() {
   entry:
     unreachable
   }
 
-  define void @test_rule653_id1585_at_idx51377() {
+  define void @test_rule472_id1258_at_idx40126() {
   entry:
     unreachable
   }
 
-  define void @test_rule654_id1586_at_idx51425() {
+  define void @test_rule473_id1259_at_idx40192() {
   entry:
     unreachable
   }
 
-  define void @test_rule655_id1587_at_idx51473() {
+  define void @test_rule474_id1260_at_idx40258() {
   entry:
     unreachable
   }
 
-  define void @test_rule656_id1588_at_idx51521() {
+  define void @test_rule475_id1261_at_idx40324() {
   entry:
     unreachable
   }
 
-  define void @test_rule657_id1589_at_idx51569() {
+  define void @test_rule476_id1262_at_idx40390() {
   entry:
     unreachable
   }
 
-  define void @test_rule658_id1590_at_idx51617() {
+  define void @test_rule477_id1263_at_idx40456() {
   entry:
     unreachable
   }
 
-  define void @test_rule659_id1591_at_idx51665() {
+  define void @test_rule478_id1264_at_idx40522() {
   entry:
     unreachable
   }
 
-  define void @test_rule660_id1592_at_idx51713() {
+  define void @test_rule479_id1265_at_idx40588() {
   entry:
     unreachable
   }
 
-  define void @test_rule661_id1593_at_idx51761() {
+  define void @test_rule480_id1266_at_idx40654() {
   entry:
     unreachable
   }
 
-  define void @test_rule662_id1594_at_idx51809() {
+  define void @test_rule481_id1267_at_idx40720() {
   entry:
     unreachable
   }
 
-  define void @test_rule663_id1595_at_idx51857() {
+  define void @test_rule482_id1268_at_idx40786() {
   entry:
     unreachable
   }
 
-  define void @test_rule664_id1596_at_idx51905() {
+  define void @test_rule483_id1269_at_idx40852() {
   entry:
     unreachable
   }
 
-  define void @test_rule665_id1597_at_idx51953() {
+  define void @test_rule484_id1270_at_idx40918() {
   entry:
     unreachable
   }
 
-  define void @test_rule666_id1598_at_idx52001() {
+  define void @test_rule485_id1271_at_idx40984() {
   entry:
     unreachable
   }
 
-  define void @test_rule667_id1599_at_idx52049() {
+  define void @test_rule486_id1272_at_idx41050() {
   entry:
     unreachable
   }
 
-  define void @test_rule668_id1600_at_idx52097() {
+  define void @test_rule487_id1273_at_idx41116() {
   entry:
     unreachable
   }
 
-  define void @test_rule669_id1601_at_idx52145() {
+  define void @test_rule488_id1274_at_idx41182() {
   entry:
     unreachable
   }
 
-  define void @test_rule670_id1602_at_idx52193() {
+  define void @test_rule489_id1275_at_idx41248() {
   entry:
     unreachable
   }
 
-  define void @test_rule671_id1603_at_idx52241() {
+  define void @test_rule490_id1276_at_idx41314() {
   entry:
     unreachable
   }
 
-  define void @test_rule672_id1604_at_idx52289() {
+  define void @test_rule491_id1310_at_idx41380() {
   entry:
     unreachable
   }
 
-  define void @test_rule673_id1605_at_idx52337() {
+  define void @test_rule492_id1311_at_idx41446() {
   entry:
     unreachable
   }
 
-  define void @test_rule674_id1606_at_idx52385() {
+  define void @test_rule493_id1312_at_idx41512() {
   entry:
     unreachable
   }
 
-  define void @test_rule675_id1607_at_idx52433() {
+  define void @test_rule494_id1313_at_idx41578() {
   entry:
     unreachable
   }
 
-  define void @test_rule676_id1608_at_idx52481() {
+  define void @test_rule495_id1314_at_idx41644() {
   entry:
     unreachable
   }
 
-  define void @test_rule677_id1609_at_idx52529() {
+  define void @test_rule496_id1315_at_idx41710() {
   entry:
     unreachable
   }
 
-  define void @test_rule678_id1610_at_idx52577() {
+  define void @test_rule497_id1316_at_idx41776() {
   entry:
     unreachable
   }
 
-  define void @test_rule679_id1627_at_idx52625() {
+  define void @test_rule498_id1317_at_idx41842() {
   entry:
     unreachable
   }
 
-  define void @test_rule680_id1628_at_idx52679() {
+  define void @test_rule499_id1318_at_idx41908() {
   entry:
     unreachable
   }
 
-  define void @test_rule681_id1650_at_idx52733() {
+  define void @test_rule500_id1319_at_idx41974() {
   entry:
     unreachable
   }
 
-  define void @test_rule682_id1651_at_idx52781() {
+  define void @test_rule501_id1320_at_idx42040() {
   entry:
     unreachable
   }
 
-  define void @test_rule683_id1652_at_idx52829() {
+  define void @test_rule502_id1321_at_idx42106() {
   entry:
     unreachable
   }
 
-  define void @test_rule684_id1653_at_idx52877() {
+  define void @test_rule503_id1322_at_idx42172() {
   entry:
     unreachable
   }
 
-  define void @test_rule685_id1654_at_idx52925() {
+  define void @test_rule504_id1323_at_idx42238() {
   entry:
     unreachable
   }
 
-  define void @test_rule686_id1655_at_idx52973() {
+  define void @test_rule505_id1324_at_idx42304() {
   entry:
     unreachable
   }
 
-  define void @test_rule687_id1656_at_idx53021() {
+  define void @test_rule506_id1325_at_idx42370() {
   entry:
     unreachable
   }
 
-  define void @test_rule688_id1657_at_idx53069() {
+  define void @test_rule507_id1345_at_idx42436() {
   entry:
     unreachable
   }
 
-  define void @test_rule689_id1658_at_idx53117() {
+  define void @test_rule508_id1346_at_idx42502() {
   entry:
     unreachable
   }
 
-  define void @test_rule690_id1659_at_idx53165() {
+  define void @test_rule509_id1347_at_idx42568() {
   entry:
     unreachable
   }
 
-  define void @test_rule691_id1660_at_idx53213() {
+  define void @test_rule510_id1348_at_idx42634() {
   entry:
     unreachable
   }
 
-  define void @test_rule692_id1661_at_idx53261() {
+  define void @test_rule511_id1349_at_idx42700() {
   entry:
     unreachable
   }
 
-  define void @test_rule693_id1662_at_idx53309() {
+  define void @test_rule512_id1350_at_idx42766() {
   entry:
     unreachable
   }
 
-  define void @test_rule694_id1663_at_idx53357() {
+  define void @test_rule513_id1351_at_idx42832() {
   entry:
     unreachable
   }
 
-  define void @test_rule695_id1664_at_idx53405() {
+  define void @test_rule514_id1352_at_idx42898() {
   entry:
     unreachable
   }
 
-  define void @test_rule696_id1665_at_idx53453() {
+  define void @test_rule515_id1353_at_idx42964() {
   entry:
     unreachable
   }
 
-  define void @test_rule697_id1666_at_idx53501() {
+  define void @test_rule516_id1354_at_idx43030() {
   entry:
     unreachable
   }
 
-  define void @test_rule698_id1667_at_idx53549() {
+  define void @test_rule517_id1355_at_idx43096() {
   entry:
     unreachable
   }
 
-  define void @test_rule699_id1668_at_idx53597() {
+  define void @test_rule518_id1356_at_idx43162() {
   entry:
     unreachable
   }
 
-  define void @test_rule700_id1669_at_idx53645() {
+  define void @test_rule519_id1357_at_idx43228() {
   entry:
     unreachable
   }
 
-  define void @test_rule701_id1670_at_idx53693() {
+  define void @test_rule520_id1358_at_idx43294() {
   entry:
     unreachable
   }
 
-  define void @test_rule702_id1671_at_idx53741() {
+  define void @test_rule521_id1359_at_idx43360() {
   entry:
     unreachable
   }
 
-  define void @test_rule703_id1672_at_idx53789() {
+  define void @test_rule522_id1360_at_idx43426() {
   entry:
     unreachable
   }
 
-  define void @test_rule704_id1673_at_idx53837() {
+  define void @test_rule523_id1394_at_idx43492() {
   entry:
     unreachable
   }
 
-  define void @test_rule705_id1676_at_idx53885() {
+  define void @test_rule524_id1395_at_idx43558() {
   entry:
     unreachable
   }
 
-  define void @test_rule706_id1677_at_idx53933() {
+  define void @test_rule525_id1396_at_idx43624() {
   entry:
     unreachable
   }
 
-  define void @test_rule712_id715_at_idx54278() {
+  define void @test_rule526_id1397_at_idx43690() {
   entry:
     unreachable
   }
 
-  define void @test_rule713_id716_at_idx54324() {
+  define void @test_rule527_id1398_at_idx43756() {
   entry:
     unreachable
   }
 
-  define void @test_rule714_id254_at_idx54370() {
+  define void @test_rule528_id1399_at_idx43822() {
   entry:
     unreachable
   }
 
-  define void @test_rule715_id587_at_idx54398() {
+  define void @test_rule529_id1400_at_idx43888() {
   entry:
     unreachable
   }
 
-  define void @test_rule716_id74_at_idx54432() {
+  define void @test_rule530_id1401_at_idx43954() {
   entry:
     unreachable
   }
 
-  define void @test_rule717_id411_at_idx54511() {
+  define void @test_rule531_id1402_at_idx44020() {
   entry:
     unreachable
   }
 
-  define void @test_rule718_id412_at_idx54590() {
+  define void @test_rule532_id1403_at_idx44086() {
   entry:
     unreachable
   }
 
-  define void @test_rule724_id98_at_idx55061() {
+  define void @test_rule533_id1404_at_idx44152() {
   entry:
     unreachable
   }
 
-  define void @test_rule725_id431_at_idx55140() {
+  define void @test_rule534_id1405_at_idx44218() {
   entry:
     unreachable
   }
 
-  define void @test_rule731_id2086_at_idx55611() {
+  define void @test_rule535_id1406_at_idx44284() {
   entry:
     unreachable
   }
 
-  define void @test_rule732_id2087_at_idx55705() {
+  define void @test_rule536_id1407_at_idx44350() {
   entry:
     unreachable
   }
 
-  define void @test_rule733_id2174_at_idx55799() {
+  define void @test_rule537_id1408_at_idx44416() {
   entry:
     unreachable
   }
 
-  define void @test_rule734_id2175_at_idx55893() {
+  define void @test_rule538_id1409_at_idx44482() {
   entry:
     unreachable
   }
 
-  define void @test_rule735_id2088_at_idx55987() {
+  define void @test_rule539_id1674_at_idx44548() {
   entry:
     unreachable
   }
 
-  define void @test_rule736_id2089_at_idx56081() {
+  define void @test_rule540_id1675_at_idx44608() {
   entry:
     unreachable
   }
 
-  define void @test_rule737_id2098_at_idx56175() {
+  define void @test_rule541_id1678_at_idx44668() {
   entry:
     unreachable
   }
 
-  define void @test_rule738_id2099_at_idx56269() {
+  define void @test_rule542_id1679_at_idx44728() {
   entry:
     unreachable
   }
 
-  define void @test_rule742_id2569_at_idx56651() {
+  define void @test_rule543_id1712_at_idx44788() {
   entry:
     unreachable
   }
 
-  define void @test_rule743_id2570_at_idx56745() {
+  define void @test_rule544_id1717_at_idx44857() {
   entry:
     unreachable
   }
 
-  define void @test_rule744_id2571_at_idx56839() {
+  define void @test_rule545_id1743_at_idx44926() {
   entry:
     unreachable
   }
 
-  define void @test_rule745_id2572_at_idx56933() {
+  define void @test_rule546_id1744_at_idx44992() {
   entry:
     unreachable
   }
 
-  define void @test_rule746_id2573_at_idx57027() {
+  define void @test_rule547_id1745_at_idx45058() {
   entry:
     unreachable
   }
 
-  define void @test_rule747_id2574_at_idx57121() {
+  define void @test_rule548_id1746_at_idx45124() {
   entry:
     unreachable
   }
 
-  define void @test_rule748_id2545_at_idx57215() {
+  define void @test_rule549_id1803_at_idx45190() {
   entry:
     unreachable
   }
 
-  define void @test_rule749_id2546_at_idx57297() {
+  define void @test_rule550_id1804_at_idx45256() {
   entry:
     unreachable
   }
 
-  define void @test_rule750_id2547_at_idx57379() {
+  define void @test_rule551_id1805_at_idx45322() {
   entry:
     unreachable
   }
 
-  define void @test_rule751_id2548_at_idx57461() {
+  define void @test_rule552_id1806_at_idx45388() {
   entry:
     unreachable
   }
 
-  define void @test_rule752_id2549_at_idx57543() {
+  define void @test_rule553_id1807_at_idx45454() {
   entry:
     unreachable
   }
 
-  define void @test_rule753_id2550_at_idx57625() {
+  define void @test_rule554_id1808_at_idx45520() {
   entry:
     unreachable
   }
 
-  define void @test_rule754_id865_at_idx57707() {
+  define void @test_rule555_id1903_at_idx45586() {
   entry:
     unreachable
   }
 
-  define void @test_rule755_id866_at_idx57801() {
+  define void @test_rule556_id1928_at_idx45655() {
   entry:
     unreachable
   }
 
-  define void @test_rule756_id867_at_idx57895() {
+  define void @test_rule557_id1929_at_idx45721() {
   entry:
     unreachable
   }
 
-  define void @test_rule757_id868_at_idx57989() {
+  define void @test_rule558_id1946_at_idx45787() {
   entry:
     unreachable
   }
 
-  define void @test_rule758_id869_at_idx58083() {
+  define void @test_rule559_id1947_at_idx45853() {
   entry:
     unreachable
   }
 
-  define void @test_rule759_id870_at_idx58177() {
+  define void @test_rule560_id1948_at_idx45919() {
   entry:
     unreachable
   }
 
-  define void @test_rule763_id764_at_idx58559() {
+  define void @test_rule561_id1949_at_idx45985() {
   entry:
     unreachable
   }
 
-  define void @test_rule764_id765_at_idx58641() {
+  define void @test_rule562_id1950_at_idx46051() {
   entry:
     unreachable
   }
 
-  define void @test_rule765_id766_at_idx58723() {
+  define void @test_rule563_id1951_at_idx46117() {
   entry:
     unreachable
   }
 
-  define void @test_rule766_id767_at_idx58805() {
+  define void @test_rule564_id3_at_idx46183() {
   entry:
     unreachable
   }
 
-  define void @test_rule767_id768_at_idx58887() {
+  define void @test_rule565_id123_at_idx46253() {
   entry:
     unreachable
   }
 
-  define void @test_rule768_id769_at_idx58969() {
+  define void @test_rule566_id124_at_idx46323() {
   entry:
     unreachable
   }
 
-  define void @test_rule769_id2623_at_idx59051() {
+  define void @test_rule567_id125_at_idx46393() {
   entry:
     unreachable
   }
 
-  define void @test_rule770_id2624_at_idx59145() {
+  define void @test_rule568_id126_at_idx46463() {
   entry:
     unreachable
   }
 
-  define void @test_rule771_id923_at_idx59239() {
+  define void @test_rule569_id127_at_idx46533() {
   entry:
     unreachable
   }
 
-  define void @test_rule772_id924_at_idx59333() {
+  define void @test_rule570_id128_at_idx46603() {
   entry:
     unreachable
   }
 
-  define void @test_rule773_id2029_at_idx59427() {
+  define void @test_rule571_id129_at_idx46673() {
   entry:
     unreachable
   }
 
-  define void @test_rule774_id2030_at_idx59509() {
+  define void @test_rule572_id130_at_idx46743() {
   entry:
     unreachable
   }
 
-  define void @test_rule775_id2736_at_idx59591() {
+  define void @test_rule573_id131_at_idx46813() {
   entry:
     unreachable
   }
 
-  define void @test_rule776_id2737_at_idx59673() {
+  define void @test_rule574_id132_at_idx46883() {
   entry:
     unreachable
   }
 
-  define void @test_rule777_id901_at_idx59755() {
+  define void @test_rule575_id133_at_idx46953() {
   entry:
     unreachable
   }
 
-  define void @test_rule778_id902_at_idx59849() {
+  define void @test_rule576_id134_at_idx47023() {
   entry:
     unreachable
   }
 
-  define void @test_rule779_id927_at_idx59943() {
+  define void @test_rule577_id435_at_idx47093() {
   entry:
     unreachable
   }
 
-  define void @test_rule780_id928_at_idx60037() {
+  define void @test_rule578_id448_at_idx47163() {
   entry:
     unreachable
   }
 
-  define void @test_rule783_id893_at_idx60319() {
+  define void @test_rule579_id449_at_idx47233() {
   entry:
     unreachable
   }
 
-  define void @test_rule784_id894_at_idx60413() {
+  define void @test_rule580_id450_at_idx47303() {
   entry:
     unreachable
   }
 
-  define void @test_rule785_id895_at_idx60507() {
+  define void @test_rule581_id451_at_idx47373() {
   entry:
     unreachable
   }
 
-  define void @test_rule786_id896_at_idx60601() {
+  define void @test_rule582_id452_at_idx47443() {
   entry:
     unreachable
   }
 
-  define void @test_rule787_id897_at_idx60695() {
+  define void @test_rule583_id453_at_idx47513() {
   entry:
     unreachable
   }
 
-  define void @test_rule788_id898_at_idx60789() {
+  define void @test_rule584_id454_at_idx47583() {
   entry:
     unreachable
   }
 
-  define void @test_rule789_id947_at_idx60883() {
+  define void @test_rule585_id455_at_idx47653() {
   entry:
     unreachable
   }
 
-  define void @test_rule790_id948_at_idx60965() {
+  define void @test_rule586_id456_at_idx47723() {
   entry:
     unreachable
   }
 
-  define void @test_rule791_id949_at_idx61047() {
+  define void @test_rule587_id457_at_idx47793() {
   entry:
     unreachable
   }
 
-  define void @test_rule792_id950_at_idx61129() {
+  define void @test_rule588_id458_at_idx47863() {
   entry:
     unreachable
   }
 
-  define void @test_rule793_id951_at_idx61211() {
+  define void @test_rule589_id459_at_idx47933() {
   entry:
     unreachable
   }
 
-  define void @test_rule794_id952_at_idx61293() {
+  define void @test_rule590_id351_at_idx48003() {
   entry:
     unreachable
   }
 
-  define void @test_rule795_id2092_at_idx61375() {
+  define void @test_rule591_id352_at_idx48061() {
   entry:
     unreachable
   }
 
-  define void @test_rule796_id2093_at_idx61469() {
+  define void @test_rule592_id684_at_idx48119() {
   entry:
     unreachable
   }
 
-  define void @test_rule797_id630_at_idx61563() {
+  define void @test_rule593_id685_at_idx48173() {
   entry:
     unreachable
   }
 
-  define void @test_rule798_id631_at_idx61645() {
+  define void @test_rule594_id686_at_idx48227() {
   entry:
     unreachable
   }
 
-  define void @test_rule804_id2081_at_idx61991() {
+  define void @test_rule595_id687_at_idx48281() {
   entry:
     unreachable
   }
 
-  define void @test_rule805_id2082_at_idx62065() {
+  define void @test_rule596_id1201_at_idx48335() {
   entry:
     unreachable
   }
 
-  define void @test_rule806_id2172_at_idx62139() {
+  define void @test_rule597_id1202_at_idx48389() {
   entry:
     unreachable
   }
 
-  define void @test_rule807_id2173_at_idx62213() {
+  define void @test_rule598_id1203_at_idx48443() {
   entry:
     unreachable
   }
 
-  define void @test_rule808_id75_at_idx62287() {
+  define void @test_rule599_id1204_at_idx48497() {
   entry:
     unreachable
   }
 
-  define void @test_rule809_id413_at_idx62352() {
+  define void @test_rule600_id1205_at_idx48551() {
   entry:
     unreachable
   }
 
-  define void @test_rule810_id746_at_idx62417() {
+  define void @test_rule601_id1206_at_idx48605() {
   entry:
     unreachable
   }
 
-  define void @test_rule811_id747_at_idx62479() {
+  define void @test_rule602_id1207_at_idx48659() {
   entry:
     unreachable
   }
 
-  define void @test_rule812_id748_at_idx62541() {
+  define void @test_rule603_id1208_at_idx48713() {
   entry:
     unreachable
   }
 
-  define void @test_rule813_id749_at_idx62603() {
+  define void @test_rule604_id1209_at_idx48767() {
   entry:
     unreachable
   }
 
-  define void @test_rule814_id750_at_idx62665() {
+  define void @test_rule605_id1210_at_idx48821() {
   entry:
     unreachable
   }
 
-  define void @test_rule815_id751_at_idx62727() {
+  define void @test_rule606_id1211_at_idx48875() {
   entry:
     unreachable
   }
 
-  define void @test_rule816_id752_at_idx62789() {
+  define void @test_rule607_id1212_at_idx48929() {
   entry:
     unreachable
   }
 
-  define void @test_rule817_id753_at_idx62851() {
+  define void @test_rule608_id1241_at_idx48983() {
   entry:
     unreachable
   }
 
-  define void @test_rule818_id2503_at_idx62913() {
+  define void @test_rule609_id1242_at_idx49037() {
   entry:
     unreachable
   }
 
-  define void @test_rule821_id1090_at_idx63108() {
+  define void @test_rule610_id1243_at_idx49091() {
   entry:
     unreachable
   }
 
-  define void @test_rule822_id1091_at_idx63170() {
+  define void @test_rule611_id1244_at_idx49145() {
   entry:
     unreachable
   }
 
-  define void @test_rule824_id618_at_idx63297() {
+  define void @test_rule612_id1245_at_idx49199() {
   entry:
     unreachable
   }
 
-  define void @test_rule825_id619_at_idx63359() {
+  define void @test_rule613_id1246_at_idx49253() {
   entry:
     unreachable
   }
 
-  define void @test_rule827_id754_at_idx63483() {
+  define void @test_rule614_id1251_at_idx49307() {
   entry:
     unreachable
   }
 
-  define void @test_rule828_id755_at_idx63545() {
+  define void @test_rule615_id1252_at_idx49361() {
   entry:
     unreachable
   }
 
-  define void @test_rule829_id756_at_idx63607() {
+  define void @test_rule616_id1253_at_idx49415() {
   entry:
     unreachable
   }
 
-  define void @test_rule830_id757_at_idx63669() {
+  define void @test_rule617_id1254_at_idx49469() {
   entry:
     unreachable
   }
 
-  define void @test_rule831_id624_at_idx63731() {
+  define void @test_rule618_id1255_at_idx49523() {
   entry:
     unreachable
   }
 
-  define void @test_rule832_id625_at_idx63793() {
+  define void @test_rule619_id1256_at_idx49577() {
   entry:
     unreachable
   }
 
-  define void @test_rule834_id627_at_idx63917() {
+  define void @test_rule620_id1477_at_idx49631() {
   entry:
     unreachable
   }
 
-  define void @test_rule835_id628_at_idx63979() {
+  define void @test_rule621_id1478_at_idx49685() {
   entry:
     unreachable
   }
 
-  define void @test_rule837_id821_at_idx64103() {
+  define void @test_rule622_id1479_at_idx49739() {
   entry:
     unreachable
   }
 
-  define void @test_rule838_id822_at_idx64165() {
+  define void @test_rule623_id1480_at_idx49793() {
   entry:
     unreachable
   }
 
-  define void @test_rule839_id823_at_idx64227() {
+  define void @test_rule624_id1481_at_idx49847() {
   entry:
     unreachable
   }
 
-  define void @test_rule840_id824_at_idx64289() {
+  define void @test_rule625_id1482_at_idx49901() {
   entry:
     unreachable
   }
 
-  define void @test_rule841_id621_at_idx64351() {
+  define void @test_rule626_id1493_at_idx49955() {
   entry:
     unreachable
   }
 
-  define void @test_rule842_id622_at_idx64413() {
+  define void @test_rule627_id1494_at_idx50009() {
   entry:
     unreachable
   }
 
-  define void @test_rule844_id937_at_idx64537() {
+  define void @test_rule628_id1495_at_idx50063() {
   entry:
     unreachable
   }
 
-  define void @test_rule845_id938_at_idx64599() {
+  define void @test_rule629_id1496_at_idx50117() {
   entry:
     unreachable
   }
 
-  define void @test_rule846_id939_at_idx64661() {
+  define void @test_rule630_id1497_at_idx50171() {
   entry:
     unreachable
   }
 
-  define void @test_rule847_id940_at_idx64723() {
+  define void @test_rule631_id1498_at_idx50225() {
   entry:
     unreachable
   }
 
-  define void @test_rule849_id171_at_idx64850() {
+  define void @test_rule632_id1499_at_idx50279() {
   entry:
     unreachable
   }
 
-  define void @test_rule850_id172_at_idx64915() {
+  define void @test_rule633_id1500_at_idx50333() {
   entry:
     unreachable
   }
 
-  define void @test_rule851_id506_at_idx64980() {
+  define void @test_rule634_id1501_at_idx50387() {
   entry:
     unreachable
   }
 
-  define void @test_rule852_id813_at_idx65042() {
+  define void @test_rule635_id1502_at_idx50441() {
   entry:
     unreachable
   }
 
-  define void @test_rule853_id814_at_idx65104() {
+  define void @test_rule636_id1503_at_idx50495() {
   entry:
     unreachable
   }
 
-  define void @test_rule854_id815_at_idx65166() {
+  define void @test_rule637_id1504_at_idx50549() {
   entry:
     unreachable
   }
 
-  define void @test_rule855_id816_at_idx65228() {
+  define void @test_rule638_id1548_at_idx50603() {
   entry:
     unreachable
   }
 
-  define void @test_rule856_id817_at_idx65290() {
+  define void @test_rule639_id1549_at_idx50657() {
   entry:
     unreachable
   }
 
-  define void @test_rule857_id818_at_idx65352() {
+  define void @test_rule640_id1550_at_idx50711() {
   entry:
     unreachable
   }
 
-  define void @test_rule860_id1094_at_idx65544() {
+  define void @test_rule641_id1551_at_idx50765() {
   entry:
     unreachable
   }
 
-  define void @test_rule861_id1095_at_idx65606() {
+  define void @test_rule642_id1552_at_idx50819() {
   entry:
     unreachable
   }
 
-  define void @test_rule862_id197_at_idx65668() {
+  define void @test_rule643_id1553_at_idx50873() {
   entry:
     unreachable
   }
 
-  define void @test_rule863_id536_at_idx65730() {
+  define void @test_rule644_id1554_at_idx50927() {
   entry:
     unreachable
   }
 
-  define void @test_rule867_id929_at_idx65987() {
+  define void @test_rule645_id1555_at_idx50981() {
   entry:
     unreachable
   }
 
-  define void @test_rule868_id930_at_idx66049() {
+  define void @test_rule646_id1556_at_idx51035() {
   entry:
     unreachable
   }
 
-  define void @test_rule869_id931_at_idx66111() {
+  define void @test_rule647_id1579_at_idx51089() {
   entry:
     unreachable
   }
 
-  define void @test_rule870_id932_at_idx66173() {
+  define void @test_rule648_id1580_at_idx51137() {
   entry:
     unreachable
   }
 
-  define void @test_rule871_id933_at_idx66235() {
+  define void @test_rule649_id1581_at_idx51185() {
   entry:
     unreachable
   }
 
-  define void @test_rule872_id934_at_idx66297() {
+  define void @test_rule650_id1582_at_idx51233() {
   entry:
     unreachable
   }
 
-  define void @test_rule873_id935_at_idx66359() {
+  define void @test_rule651_id1583_at_idx51281() {
   entry:
     unreachable
   }
 
-  define void @test_rule874_id936_at_idx66421() {
+  define void @test_rule652_id1584_at_idx51329() {
   entry:
     unreachable
   }
 
-  define void @test_rule875_id198_at_idx66483() {
+  define void @test_rule653_id1585_at_idx51377() {
   entry:
     unreachable
   }
 
-  define void @test_rule876_id537_at_idx66545() {
+  define void @test_rule654_id1586_at_idx51425() {
   entry:
     unreachable
   }
 
-  define void @test_rule879_id1092_at_idx66737() {
+  define void @test_rule655_id1587_at_idx51473() {
   entry:
     unreachable
   }
 
-  define void @test_rule880_id1093_at_idx66799() {
+  define void @test_rule656_id1588_at_idx51521() {
   entry:
     unreachable
   }
 
-  define void @test_rule881_id2253_at_idx66861() {
+  define void @test_rule657_id1589_at_idx51569() {
   entry:
     unreachable
   }
 
-  define void @test_rule882_id2254_at_idx66909() {
+  define void @test_rule658_id1590_at_idx51617() {
   entry:
     unreachable
   }
 
-  define void @test_rule883_id2255_at_idx66957() {
+  define void @test_rule659_id1591_at_idx51665() {
   entry:
     unreachable
   }
 
-  define void @test_rule884_id678_at_idx67005() {
+  define void @test_rule660_id1592_at_idx51713() {
   entry:
     unreachable
   }
 
-  define void @test_rule885_id679_at_idx67055() {
+  define void @test_rule661_id1593_at_idx51761() {
   entry:
     unreachable
   }
 
-  define void @test_rule886_id2295_at_idx67105() {
+  define void @test_rule662_id1594_at_idx51809() {
   entry:
     unreachable
   }
 
-  define void @test_rule887_id2296_at_idx67151() {
+  define void @test_rule663_id1595_at_idx51857() {
   entry:
     unreachable
   }
 
-  define void @test_rule888_id2297_at_idx67197() {
+  define void @test_rule664_id1596_at_idx51905() {
   entry:
     unreachable
   }
 
-  define void @test_rule889_id2298_at_idx67243() {
+  define void @test_rule665_id1597_at_idx51953() {
   entry:
     unreachable
   }
 
-  define void @test_rule891_id2300_at_idx67333() {
+  define void @test_rule666_id1598_at_idx52001() {
   entry:
     unreachable
   }
 
-  define void @test_rule892_id2301_at_idx67379() {
+  define void @test_rule667_id1599_at_idx52049() {
   entry:
     unreachable
   }
 
-  define void @test_rule893_id2302_at_idx67425() {
+  define void @test_rule668_id1600_at_idx52097() {
   entry:
     unreachable
   }
 
-  define void @test_rule895_id2304_at_idx67517() {
+  define void @test_rule669_id1601_at_idx52145() {
   entry:
     unreachable
   }
 
-  define void @test_rule896_id2305_at_idx67561() {
+  define void @test_rule670_id1602_at_idx52193() {
   entry:
     unreachable
   }
 
-  define void @test_rule897_id2306_at_idx67607() {
+  define void @test_rule671_id1603_at_idx52241() {
   entry:
     unreachable
   }
 
-  define void @test_rule898_id2307_at_idx67653() {
+  define void @test_rule672_id1604_at_idx52289() {
   entry:
     unreachable
   }
 
-  define void @test_rule901_id2310_at_idx67791() {
+  define void @test_rule673_id1605_at_idx52337() {
   entry:
     unreachable
   }
 
-  define void @test_rule902_id2311_at_idx67837() {
+  define void @test_rule674_id1606_at_idx52385() {
   entry:
     unreachable
   }
 
-  define void @test_rule903_id2312_at_idx67883() {
+  define void @test_rule675_id1607_at_idx52433() {
   entry:
     unreachable
   }
 
-  define void @test_rule916_id2325_at_idx68477() {
+  define void @test_rule676_id1608_at_idx52481() {
   entry:
     unreachable
   }
 
-  define void @test_rule917_id2326_at_idx68523() {
+  define void @test_rule677_id1609_at_idx52529() {
   entry:
     unreachable
   }
 
-  define void @test_rule918_id2327_at_idx68569() {
+  define void @test_rule678_id1610_at_idx52577() {
   entry:
     unreachable
   }
 
-  define void @test_rule919_id2328_at_idx68615() {
+  define void @test_rule679_id1627_at_idx52625() {
   entry:
     unreachable
   }
 
-  define void @test_rule921_id2330_at_idx68705() {
+  define void @test_rule680_id1628_at_idx52679() {
   entry:
     unreachable
   }
 
-  define void @test_rule922_id2331_at_idx68751() {
+  define void @test_rule681_id1650_at_idx52733() {
   entry:
     unreachable
   }
 
-  define void @test_rule923_id2332_at_idx68797() {
+  define void @test_rule682_id1651_at_idx52781() {
   entry:
     unreachable
   }
 
-  define void @test_rule925_id2334_at_idx68889() {
+  define void @test_rule683_id1652_at_idx52829() {
   entry:
     unreachable
   }
 
-  define void @test_rule926_id2335_at_idx68933() {
+  define void @test_rule684_id1653_at_idx52877() {
   entry:
     unreachable
   }
 
-  define void @test_rule927_id2336_at_idx68979() {
+  define void @test_rule685_id1654_at_idx52925() {
   entry:
     unreachable
   }
 
-  define void @test_rule928_id2337_at_idx69025() {
+  define void @test_rule686_id1655_at_idx52973() {
   entry:
     unreachable
   }
 
-  define void @test_rule931_id2340_at_idx69163() {
+  define void @test_rule687_id1656_at_idx53021() {
   entry:
     unreachable
   }
 
-  define void @test_rule932_id2341_at_idx69209() {
+  define void @test_rule688_id1657_at_idx53069() {
   entry:
     unreachable
   }
 
-  define void @test_rule933_id2342_at_idx69255() {
+  define void @test_rule689_id1658_at_idx53117() {
   entry:
     unreachable
   }
 
-  define void @test_rule946_id2355_at_idx69849() {
+  define void @test_rule690_id1659_at_idx53165() {
   entry:
     unreachable
   }
 
-  define void @test_rule947_id2356_at_idx69899() {
+  define void @test_rule691_id1660_at_idx53213() {
   entry:
     unreachable
   }
 
-  define void @test_rule948_id2357_at_idx69949() {
+  define void @test_rule692_id1661_at_idx53261() {
   entry:
     unreachable
   }
 
-  define void @test_rule950_id2359_at_idx70049() {
+  define void @test_rule693_id1662_at_idx53309() {
   entry:
     unreachable
   }
 
-  define void @test_rule951_id2360_at_idx70099() {
+  define void @test_rule694_id1663_at_idx53357() {
   entry:
     unreachable
   }
 
-  define void @test_rule952_id2361_at_idx70149() {
+  define void @test_rule695_id1664_at_idx53405() {
   entry:
     unreachable
   }
 
-  define void @test_rule954_id2363_at_idx70249() {
+  define void @test_rule696_id1665_at_idx53453() {
   entry:
     unreachable
   }
 
-  define void @test_rule955_id2364_at_idx70299() {
+  define void @test_rule697_id1666_at_idx53501() {
   entry:
     unreachable
   }
 
-  define void @test_rule956_id2365_at_idx70349() {
+  define void @test_rule698_id1667_at_idx53549() {
   entry:
     unreachable
   }
 
-  define void @test_rule959_id2368_at_idx70499() {
+  define void @test_rule699_id1668_at_idx53597() {
   entry:
     unreachable
   }
 
-  define void @test_rule960_id2369_at_idx70549() {
+  define void @test_rule700_id1669_at_idx53645() {
   entry:
     unreachable
   }
 
-  define void @test_rule961_id2370_at_idx70599() {
+  define void @test_rule701_id1670_at_idx53693() {
   entry:
     unreachable
   }
 
-  define void @test_rule972_id2381_at_idx71149() {
+  define void @test_rule702_id1671_at_idx53741() {
   entry:
     unreachable
   }
 
-  define void @test_rule973_id2382_at_idx71199() {
+  define void @test_rule703_id1672_at_idx53789() {
   entry:
     unreachable
   }
 
-  define void @test_rule974_id2383_at_idx71249() {
+  define void @test_rule704_id1673_at_idx53837() {
   entry:
     unreachable
   }
 
-  define void @test_rule976_id2385_at_idx71349() {
+  define void @test_rule705_id1676_at_idx53885() {
   entry:
     unreachable
   }
 
-  define void @test_rule977_id2386_at_idx71399() {
+  define void @test_rule706_id1677_at_idx53933() {
   entry:
     unreachable
   }
 
-  define void @test_rule978_id2387_at_idx71449() {
+  define void @test_rule707_id1711_at_idx53981() {
   entry:
     unreachable
   }
 
-  define void @test_rule980_id2389_at_idx71549() {
+  define void @test_rule708_id1902_at_idx54038() {
   entry:
     unreachable
   }
 
-  define void @test_rule981_id2390_at_idx71599() {
+  define void @test_rule709_id1708_at_idx54095() {
   entry:
     unreachable
   }
 
-  define void @test_rule982_id2391_at_idx71649() {
+  define void @test_rule710_id1897_at_idx54156() {
   entry:
     unreachable
   }
 
-  define void @test_rule985_id2394_at_idx71799() {
+  define void @test_rule711_id167_at_idx54217() {
   entry:
     unreachable
   }
 
-  define void @test_rule986_id2395_at_idx71849() {
+  define void @test_rule712_id715_at_idx54278() {
   entry:
     unreachable
   }
 
-  define void @test_rule987_id2396_at_idx71899() {
+  define void @test_rule713_id716_at_idx54324() {
   entry:
     unreachable
   }
 
-  define void @test_rule998_id201_at_idx72449() {
+  define void @test_rule714_id254_at_idx54370() {
   entry:
     unreachable
   }
 
-  define void @test_rule999_id334_at_idx72499() {
+  define void @test_rule715_id587_at_idx54398() {
   entry:
     unreachable
   }
 
-  define void @test_rule1000_id540_at_idx72549() {
+  define void @test_rule716_id74_at_idx54432() {
   entry:
     unreachable
   }
 
-  define void @test_rule1002_id661_at_idx72634() {
+  define void @test_rule717_id411_at_idx54511() {
   entry:
     unreachable
   }
 
-  define void @test_rule1003_id662_at_idx72684() {
+  define void @test_rule718_id412_at_idx54590() {
   entry:
     unreachable
   }
 
-  define void @test_rule1005_id1489_at_idx72784() {
+  define void @test_rule719_id149_at_idx54666() {
   entry:
     unreachable
   }
 
-  define void @test_rule1006_id1490_at_idx72834() {
+  define void @test_rule720_id485_at_idx54745() {
   entry:
     unreachable
   }
 
-  define void @test_rule1007_id1491_at_idx72884() {
+  define void @test_rule721_id153_at_idx54824() {
   entry:
     unreachable
   }
 
-  define void @test_rule1008_id1492_at_idx72934() {
+  define void @test_rule722_id488_at_idx54903() {
   entry:
     unreachable
   }
 
-  define void @test_rule1009_id659_at_idx72984() {
+  define void @test_rule723_id474_at_idx54982() {
   entry:
     unreachable
   }
 
-  define void @test_rule1012_id1563_at_idx73166() {
+  define void @test_rule724_id98_at_idx55061() {
   entry:
     unreachable
   }
 
-  define void @test_rule1013_id1567_at_idx73216() {
+  define void @test_rule725_id431_at_idx55140() {
   entry:
     unreachable
   }
 
-  define void @test_rule1014_id1571_at_idx73266() {
+  define void @test_rule726_id78_at_idx55219() {
   entry:
     unreachable
   }
 
-  define void @test_rule1015_id1575_at_idx73316() {
+  define void @test_rule727_id415_at_idx55298() {
   entry:
     unreachable
   }
 
-  define void @test_rule1016_id2053_at_idx73366() {
+  define void @test_rule728_id416_at_idx55377() {
   entry:
     unreachable
   }
 
-  define void @test_rule1017_id2055_at_idx73434() {
+  define void @test_rule729_id157_at_idx55453() {
   entry:
     unreachable
   }
 
-  define void @test_rule1019_id1564_at_idx73570() {
+  define void @test_rule730_id491_at_idx55532() {
   entry:
     unreachable
   }
 
-  define void @test_rule1020_id1568_at_idx73620() {
+  define void @test_rule731_id2086_at_idx55611() {
   entry:
     unreachable
   }
 
-  define void @test_rule1021_id1572_at_idx73670() {
+  define void @test_rule732_id2087_at_idx55705() {
   entry:
     unreachable
   }
 
-  define void @test_rule1022_id1576_at_idx73720() {
+  define void @test_rule733_id2174_at_idx55799() {
   entry:
     unreachable
   }
 
-  define void @test_rule1023_id2058_at_idx73770() {
+  define void @test_rule734_id2175_at_idx55893() {
   entry:
     unreachable
   }
 
-  define void @test_rule1024_id2060_at_idx73838() {
+  define void @test_rule735_id2088_at_idx55987() {
   entry:
     unreachable
   }
 
-  define void @test_rule1026_id660_at_idx73974() {
+  define void @test_rule736_id2089_at_idx56081() {
   entry:
     unreachable
   }
 
-  define void @test_rule1029_id1557_at_idx74160() {
+  define void @test_rule737_id2098_at_idx56175() {
   entry:
     unreachable
   }
 
-  define void @test_rule1030_id1558_at_idx74210() {
+  define void @test_rule738_id2099_at_idx56269() {
   entry:
     unreachable
   }
 
-  define void @test_rule1031_id1559_at_idx74260() {
+  define void @test_rule739_id173_at_idx56363() {
   entry:
     unreachable
   }
 
-  define void @test_rule1032_id1565_at_idx74310() {
+  define void @test_rule740_id174_at_idx56460() {
   entry:
     unreachable
   }
 
-  define void @test_rule1033_id1569_at_idx74360() {
+  define void @test_rule741_id507_at_idx56557() {
   entry:
     unreachable
   }
 
-  define void @test_rule1034_id1573_at_idx74410() {
+  define void @test_rule742_id2569_at_idx56651() {
   entry:
     unreachable
   }
 
-  define void @test_rule1035_id1577_at_idx74460() {
+  define void @test_rule743_id2570_at_idx56745() {
   entry:
     unreachable
   }
 
-  define void @test_rule1036_id2043_at_idx74510() {
+  define void @test_rule744_id2571_at_idx56839() {
   entry:
     unreachable
   }
 
-  define void @test_rule1037_id2045_at_idx74576() {
+  define void @test_rule745_id2572_at_idx56933() {
   entry:
     unreachable
   }
 
-  define void @test_rule1039_id1545_at_idx74708() {
+  define void @test_rule746_id2573_at_idx57027() {
   entry:
     unreachable
   }
 
-  define void @test_rule1040_id1546_at_idx74758() {
+  define void @test_rule747_id2574_at_idx57121() {
   entry:
     unreachable
   }
 
-  define void @test_rule1041_id1547_at_idx74808() {
+  define void @test_rule748_id2545_at_idx57215() {
   entry:
     unreachable
   }
 
-  define void @test_rule1042_id1566_at_idx74858() {
+  define void @test_rule749_id2546_at_idx57297() {
   entry:
     unreachable
   }
 
-  define void @test_rule1043_id1570_at_idx74908() {
+  define void @test_rule750_id2547_at_idx57379() {
   entry:
     unreachable
   }
 
-  define void @test_rule1044_id1574_at_idx74958() {
+  define void @test_rule751_id2548_at_idx57461() {
   entry:
     unreachable
   }
 
-  define void @test_rule1045_id1578_at_idx75008() {
+  define void @test_rule752_id2549_at_idx57543() {
   entry:
     unreachable
   }
 
-  define void @test_rule1046_id2048_at_idx75058() {
+  define void @test_rule753_id2550_at_idx57625() {
   entry:
     unreachable
   }
 
-  define void @test_rule1047_id2050_at_idx75124() {
+  define void @test_rule754_id865_at_idx57707() {
   entry:
     unreachable
   }
 
-  define void @test_rule1049_id1560_at_idx75256() {
+  define void @test_rule755_id866_at_idx57801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule756_id867_at_idx57895() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule757_id868_at_idx57989() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule758_id869_at_idx58083() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule759_id870_at_idx58177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule760_id2483_at_idx58271() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule761_id2484_at_idx58368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule762_id2521_at_idx58465() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule763_id764_at_idx58559() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule764_id765_at_idx58641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule765_id766_at_idx58723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule766_id767_at_idx58805() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule767_id768_at_idx58887() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule768_id769_at_idx58969() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule769_id2623_at_idx59051() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule770_id2624_at_idx59145() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule771_id923_at_idx59239() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule772_id924_at_idx59333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule773_id2029_at_idx59427() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule774_id2030_at_idx59509() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule775_id2736_at_idx59591() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule776_id2737_at_idx59673() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule777_id901_at_idx59755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule778_id902_at_idx59849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule779_id927_at_idx59943() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule780_id928_at_idx60037() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule781_id175_at_idx60131() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule782_id508_at_idx60225() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule783_id893_at_idx60319() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule784_id894_at_idx60413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule785_id895_at_idx60507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule786_id896_at_idx60601() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule787_id897_at_idx60695() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule788_id898_at_idx60789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule789_id947_at_idx60883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule790_id948_at_idx60965() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule791_id949_at_idx61047() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule792_id950_at_idx61129() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule793_id951_at_idx61211() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule794_id952_at_idx61293() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule795_id2092_at_idx61375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule796_id2093_at_idx61469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule797_id630_at_idx61563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule798_id631_at_idx61645() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule799_id632_at_idx61727() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule800_id408_at_idx61809() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule801_id59_at_idx61856() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule802_id60_at_idx61903() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule803_id409_at_idx61947() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule804_id2081_at_idx61991() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule805_id2082_at_idx62065() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule806_id2172_at_idx62139() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule807_id2173_at_idx62213() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule808_id75_at_idx62287() {
   entry:
     unreachable
   }
 
-  define void @test_rule1050_id1561_at_idx75306() {
-  entry:
-    unreachable
-  }
+  define void @test_rule809_id413_at_idx62352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule810_id746_at_idx62417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule811_id747_at_idx62479() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule812_id748_at_idx62541() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule813_id749_at_idx62603() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule814_id750_at_idx62665() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule815_id751_at_idx62727() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule816_id752_at_idx62789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule817_id753_at_idx62851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule818_id2503_at_idx62913() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule819_id150_at_idx62978() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule820_id486_at_idx63043() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule821_id1090_at_idx63108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule822_id1091_at_idx63170() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule823_id479_at_idx63232() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule824_id618_at_idx63297() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule825_id619_at_idx63359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule826_id620_at_idx63421() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule827_id754_at_idx63483() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule828_id755_at_idx63545() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule829_id756_at_idx63607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule830_id757_at_idx63669() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule831_id624_at_idx63731() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule832_id625_at_idx63793() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule833_id626_at_idx63855() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule834_id627_at_idx63917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule835_id628_at_idx63979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule836_id629_at_idx64041() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule837_id821_at_idx64103() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule838_id822_at_idx64165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule839_id823_at_idx64227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule840_id824_at_idx64289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule841_id621_at_idx64351() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule842_id622_at_idx64413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule843_id623_at_idx64475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule844_id937_at_idx64537() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule845_id938_at_idx64599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule846_id939_at_idx64661() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule847_id940_at_idx64723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule848_id477_at_idx64785() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule849_id171_at_idx64850() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule850_id172_at_idx64915() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule851_id506_at_idx64980() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule852_id813_at_idx65042() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule853_id814_at_idx65104() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule854_id815_at_idx65166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule855_id816_at_idx65228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule856_id817_at_idx65290() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule857_id818_at_idx65352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule858_id154_at_idx65414() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule859_id489_at_idx65479() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule860_id1094_at_idx65544() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule861_id1095_at_idx65606() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule862_id197_at_idx65668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule863_id536_at_idx65730() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule864_id475_at_idx65792() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule865_id79_at_idx65857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule866_id417_at_idx65922() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule867_id929_at_idx65987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule868_id930_at_idx66049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule869_id931_at_idx66111() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule870_id932_at_idx66173() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule871_id933_at_idx66235() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule872_id934_at_idx66297() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule873_id935_at_idx66359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule874_id936_at_idx66421() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule875_id198_at_idx66483() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule876_id537_at_idx66545() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule877_id158_at_idx66607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule878_id492_at_idx66672() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule879_id1092_at_idx66737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule880_id1093_at_idx66799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule881_id2253_at_idx66861() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule882_id2254_at_idx66909() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule883_id2255_at_idx66957() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule884_id678_at_idx67005() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule885_id679_at_idx67055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule886_id2295_at_idx67105() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule887_id2296_at_idx67151() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule888_id2297_at_idx67197() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule889_id2298_at_idx67243() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule891_id2300_at_idx67333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule892_id2301_at_idx67379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule893_id2302_at_idx67425() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule895_id2304_at_idx67517() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule896_id2305_at_idx67561() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule897_id2306_at_idx67607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule898_id2307_at_idx67653() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule901_id2310_at_idx67791() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule902_id2311_at_idx67837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule903_id2312_at_idx67883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule916_id2325_at_idx68477() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule917_id2326_at_idx68523() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule918_id2327_at_idx68569() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule919_id2328_at_idx68615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule921_id2330_at_idx68705() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule922_id2331_at_idx68751() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule923_id2332_at_idx68797() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule925_id2334_at_idx68889() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule926_id2335_at_idx68933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule927_id2336_at_idx68979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule928_id2337_at_idx69025() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule931_id2340_at_idx69163() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule932_id2341_at_idx69209() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule933_id2342_at_idx69255() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule946_id2355_at_idx69849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule947_id2356_at_idx69899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule948_id2357_at_idx69949() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule950_id2359_at_idx70049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule951_id2360_at_idx70099() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule952_id2361_at_idx70149() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule954_id2363_at_idx70249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule955_id2364_at_idx70299() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule956_id2365_at_idx70349() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule959_id2368_at_idx70499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule960_id2369_at_idx70549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule961_id2370_at_idx70599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule972_id2381_at_idx71149() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule973_id2382_at_idx71199() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule974_id2383_at_idx71249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule976_id2385_at_idx71349() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule977_id2386_at_idx71399() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule978_id2387_at_idx71449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule980_id2389_at_idx71549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule981_id2390_at_idx71599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule982_id2391_at_idx71649() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule985_id2394_at_idx71799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule986_id2395_at_idx71849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule987_id2396_at_idx71899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule998_id201_at_idx72449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule999_id334_at_idx72499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1000_id540_at_idx72549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1001_id595_at_idx72599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1002_id661_at_idx72634() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1003_id662_at_idx72684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1004_id663_at_idx72734() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1005_id1489_at_idx72784() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1006_id1490_at_idx72834() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1007_id1491_at_idx72884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1008_id1492_at_idx72934() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1009_id659_at_idx72984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1012_id1563_at_idx73166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1013_id1567_at_idx73216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1014_id1571_at_idx73266() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1015_id1575_at_idx73316() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1016_id2053_at_idx73366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1017_id2055_at_idx73434() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1018_id2057_at_idx73502() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1019_id1564_at_idx73570() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1020_id1568_at_idx73620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1021_id1572_at_idx73670() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1022_id1576_at_idx73720() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1023_id2058_at_idx73770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1024_id2060_at_idx73838() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1025_id2062_at_idx73906() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1026_id660_at_idx73974() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1027_id2033_at_idx74024() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1028_id2037_at_idx74092() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1029_id1557_at_idx74160() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1030_id1558_at_idx74210() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1031_id1559_at_idx74260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1032_id1565_at_idx74310() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1033_id1569_at_idx74360() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1034_id1573_at_idx74410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1035_id1577_at_idx74460() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1036_id2043_at_idx74510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1037_id2045_at_idx74576() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1038_id2047_at_idx74642() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1039_id1545_at_idx74708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1040_id1546_at_idx74758() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1041_id1547_at_idx74808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1042_id1566_at_idx74858() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1043_id1570_at_idx74908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1044_id1574_at_idx74958() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1045_id1578_at_idx75008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1046_id2048_at_idx75058() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1047_id2050_at_idx75124() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1048_id2052_at_idx75190() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1049_id1560_at_idx75256() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1050_id1561_at_idx75306() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1051_id1562_at_idx75356() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1052_id34_at_idx75406() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1053_id291_at_idx75428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1054_id590_at_idx75461() {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            test_return
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_return
+    ; SELECTED: $noreg = PATCHABLE_RET
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule0_id2693_at_idx0
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule0_id2693_at_idx0
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %10:gprb(s32) = G_CONSTANT 24
+    %5:gprb(s32) = G_CONSTANT 255
+    %7:gprb(s32) = G_CONSTANT 8
+    %3:gprb(s32) = G_SHL %9, %10
+    %2:gprb(s32) = G_ASHR %3, %8
+    %1:gprb(s32) = G_LSHR %9, %7
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule1_id2724_at_idx167
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1_id2724_at_idx167
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %10:gprb(s32) = G_CONSTANT 24
+    %5:gprb(s32) = G_CONSTANT 255
+    %7:gprb(s32) = G_CONSTANT 8
+    %3:gprb(s32) = G_SHL %9, %10
+    %2:gprb(s32) = G_ASHR %3, %8
+    %1:gprb(s32) = G_LSHR %9, %7
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule2_id1749_at_idx334
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule2_id1749_at_idx334
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 255
+    %10:gprb(s32) = G_CONSTANT 8
+    %5:gprb(s32) = G_CONSTANT 16
+    %7:gprb(s32) = G_CONSTANT 24
+    %3:gprb(s32) = G_LSHR %9, %10
+    %2:gprb(s32) = G_AND %3, %8
+    %1:gprb(s32) = G_SHL %9, %7
+    %0:gprb(s32) = G_ASHR %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule3_id1969_at_idx501
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule3_id1969_at_idx501
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 255
+    %10:gprb(s32) = G_CONSTANT 8
+    %5:gprb(s32) = G_CONSTANT 16
+    %7:gprb(s32) = G_CONSTANT 24
+    %3:gprb(s32) = G_LSHR %9, %10
+    %2:gprb(s32) = G_AND %3, %8
+    %1:gprb(s32) = G_SHL %9, %7
+    %0:gprb(s32) = G_ASHR %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule4_id1713_at_idx668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule4_id1713_at_idx668
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %4:gprb(s32) = G_CONSTANT 8
+    %0:gprb(s32) = G_LSHR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule5_id1912_at_idx757
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule5_id1912_at_idx757
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %4:gprb(s32) = G_CONSTANT 8
+    %0:gprb(s32) = G_LSHR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule6_id2704_at_idx846
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule6_id2704_at_idx846
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule7_id2705_at_idx939
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule7_id2705_at_idx939
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule8_id2732_at_idx1032
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule8_id2732_at_idx1032
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule9_id2733_at_idx1125
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule9_id2733_at_idx1125
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule10_id1819_at_idx1218
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule10_id1819_at_idx1218
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule11_id1820_at_idx1311
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule11_id1820_at_idx1311
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule12_id1999_at_idx1404
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule12_id1999_at_idx1404
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule13_id2000_at_idx1497
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule13_id2000_at_idx1497
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule14_id255_at_idx1590
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule14_id255_at_idx1590
+    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule15_id256_at_idx1768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule15_id256_at_idx1768
+    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule16_id610_at_idx1940
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule16_id610_at_idx1940
+    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule17_id611_at_idx2118
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule17_id611_at_idx2118
+    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule18_id2493_at_idx2296
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule18_id2493_at_idx2296
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2ASRrr]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 4294901760
+    %5:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ASHR %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule19_id2530_at_idx2460
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule19_id2530_at_idx2460
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2ASRrr]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 4294901760
+    %5:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ASHR %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule20_id2698_at_idx2624
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule20_id2698_at_idx2624
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2LSRrr]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 4294901760
+    %5:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_LSHR %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule21_id2729_at_idx2788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule21_id2729_at_idx2788
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2LSRrr]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 4294901760
+    %5:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_LSHR %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule22_id2492_at_idx2952
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule22_id2492_at_idx2952
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY1]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[t2LSLri]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 65535
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SHL %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule23_id2529_at_idx3116
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%6' }
+  - { reg: '$r0', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule23_id2529_at_idx3116
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY1]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[t2LSLri]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %7:gprb(s32) = COPY $r0
+    %6:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 65535
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_AND %7, %8
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SHL %6, %2
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule24_id205_at_idx3280
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule24_id205_at_idx3280
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2ASRrr]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 65535
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_ASHR %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule25_id544_at_idx3444
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule25_id544_at_idx3444
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2ASRrr]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 65535
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_ASHR %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule26_id1754_at_idx3608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule26_id1754_at_idx3608
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2LSRrr]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 65535
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_LSHR %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule27_id1974_at_idx3772
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule27_id1974_at_idx3772
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[t2LSRrr]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 65535
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_LSHR %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule28_id204_at_idx3936
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule28_id204_at_idx3936
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[t2LSLri]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 4294901760
+    %6:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_SHL %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule29_id543_at_idx4100
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$r0', virtual-reg: '%8' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule29_id543_at_idx4100
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[t2LSLri]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %8:gprb(s32) = COPY $r0
+    %5:gprb(s32) = COPY $lr
+    %7:gprb(s32) = G_CONSTANT 4294901760
+    %6:gprb(s32) = G_CONSTANT 65535
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_SHL %8, %3
+    %1:gprb(s32) = G_AND %2, %7
+    %0:gprb(s32) = G_AND %5, %6
+    %4:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule30_id1917_at_idx4264
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule30_id1917_at_idx4264
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2UXTAB16_:%[0-9]+]]:rgpr = t2UXTAB16 [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2UXTAB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtab16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule31_id1816_at_idx4333
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule31_id1816_at_idx4333
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule32_id1817_at_idx4394
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule32_id1817_at_idx4394
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule33_id1818_at_idx4455
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule33_id1818_at_idx4455
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule34_id1996_at_idx4516
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule34_id1996_at_idx4516
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule35_id1997_at_idx4577
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule35_id1997_at_idx4577
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule36_id1998_at_idx4638
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule36_id1998_at_idx4638
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule37_id1714_at_idx4699
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule37_id1714_at_idx4699
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule38_id1911_at_idx4756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule38_id1911_at_idx4756
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule39_id1771_at_idx4813
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule39_id1771_at_idx4813
+    ; SELECTED: [[MRC:%[0-9]+]]:gprwithapsr = MRC 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MRC]]
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET %5(s32)
+
+...
+---
+name:            test_rule40_id1772_at_idx4979
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule40_id1772_at_idx4979
+    ; SELECTED: [[MRC2_:%[0-9]+]]:gprwithapsr = MRC2 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MRC2_]]
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET %5(s32)
+
+...
+---
+name:            test_rule41_id1994_at_idx5139
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule41_id1994_at_idx5139
+    ; SELECTED: [[MRC:%[0-9]+]]:gprwithapsr = MRC 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MRC]]
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET %5(s32)
+
+...
+---
+name:            test_rule42_id1995_at_idx5305
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule42_id1995_at_idx5305
+    ; SELECTED: [[MRC2_:%[0-9]+]]:gprwithapsr = MRC2 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MRC2_]]
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET %5(s32)
+
+...
+---
+name:            test_rule43_id265_at_idx5471
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule43_id265_at_idx5471
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule44_id266_at_idx5637
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule44_id266_at_idx5637
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule45_id606_at_idx5797
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule45_id606_at_idx5797
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule46_id607_at_idx5963
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule46_id607_at_idx5963
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule47_id2489_at_idx6129
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$r1', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule47_id2489_at_idx6129
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %7:gprb(s32) = COPY $r1
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %6:gprb(s32) = G_CONSTANT 16
+    %2:gprb(s32) = G_ASHR %7, %8
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_MUL %1, %2
+    %3:gprb(s32) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule48_id2526_at_idx6279
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$r1', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule48_id2526_at_idx6279
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %7:gprb(s32) = COPY $r1
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %6:gprb(s32) = G_CONSTANT 16
+    %2:gprb(s32) = G_ASHR %7, %8
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_MUL %1, %2
+    %3:gprb(s32) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule49_id194_at_idx6429
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$r1', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule49_id194_at_idx6429
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %7:gprb(s32) = COPY $r1
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %6:gprb(s32) = G_CONSTANT 16
+    %2:gprb(s32) = G_ASHR %7, %8
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_MUL %1, %2
+    %3:gprb(s32) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule50_id525_at_idx6579
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$r1', virtual-reg: '%7' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule50_id525_at_idx6579
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %7:gprb(s32) = COPY $r1
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %6:gprb(s32) = G_CONSTANT 16
+    %2:gprb(s32) = G_ASHR %7, %8
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_MUL %1, %2
+    %3:gprb(s32) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule51_id188_at_idx6729
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule51_id188_at_idx6729
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 16
+    %4:gprb(s32) = G_CONSTANT 16
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_ASHR %3, %4
+    %2:gprb(s32) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule52_id519_at_idx6847
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule52_id519_at_idx6847
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 16
+    %4:gprb(s32) = G_CONSTANT 16
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_ASHR %3, %4
+    %2:gprb(s32) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule53_id1750_at_idx6965
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule53_id1750_at_idx6965
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %4:gprb(s32) = G_CONSTANT 65535
+    %1:gprb(s32) = G_AND %5, %6
+    %0:gprb(s32) = G_AND %3, %4
+    %2:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule54_id1970_at_idx7086
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule54_id1970_at_idx7086
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %4:gprb(s32) = G_CONSTANT 65535
+    %1:gprb(s32) = G_AND %5, %6
+    %0:gprb(s32) = G_AND %3, %4
+    %2:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule55_id2694_at_idx7207
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule55_id2694_at_idx7207
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 65535
+    %4:gprb(s32) = G_CONSTANT 4294901760
+    %1:gprb(s32) = G_AND %5, %6
+    %0:gprb(s32) = G_AND %3, %4
+    %2:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule56_id2725_at_idx7328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule56_id2725_at_idx7328
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 65535
+    %4:gprb(s32) = G_CONSTANT 4294901760
+    %1:gprb(s32) = G_AND %5, %6
+    %0:gprb(s32) = G_AND %3, %4
+    %2:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule57_id1753_at_idx7449
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule57_id1753_at_idx7449
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[t2ASRrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ASHR %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule58_id1973_at_idx7585
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule58_id1973_at_idx7585
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[t2ASRrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ASHR %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule59_id1752_at_idx7721
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule59_id1752_at_idx7721
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[t2LSRrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_LSHR %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule60_id1972_at_idx7857
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule60_id1972_at_idx7857
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[ANDrr]], [[t2LSRrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_LSHR %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule61_id1751_at_idx7993
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule61_id1751_at_idx7993
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[t2LSLri]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 65535
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SHL %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule62_id1971_at_idx8129
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule62_id1971_at_idx8129
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[UXTH]], [[t2LSLri]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %6:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %5:gprb(s32) = G_CONSTANT 65535
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SHL %6, %2
+    %0:gprb(s32) = G_AND %4, %5
+    %3:gprb(s32) = G_OR %0, %1
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule63_id2697_at_idx8265
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule63_id2697_at_idx8265
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2ASRrr]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_ASHR %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule64_id2728_at_idx8401
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule64_id2728_at_idx8401
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2ASRrr]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_ASHR %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule65_id2696_at_idx8537
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule65_id2696_at_idx8537
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2LSRrr]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_LSHR %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule66_id2727_at_idx8673
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule66_id2727_at_idx8673
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY1]], [[t2MOVi]], 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2LSRrr]], [[ANDrr]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 4294901760
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_LSHR %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule67_id2695_at_idx8809
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule67_id2695_at_idx8809
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY1]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2LSLri]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 65535
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_SHL %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule68_id2726_at_idx8945
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%4' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule68_id2726_at_idx8945
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY1]], 1, 14, $noreg, $noreg
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[t2LSLri]], [[UXTH]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %5:gprb(s32) = COPY $r0
+    %4:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 65535
+    %2:gprb(s32) = G_AND %5, %6
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_SHL %4, %1
+    %3:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %3(s32)
+
+...
+---
+name:            test_rule69_id267_at_idx9081
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule69_id267_at_idx9081
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule70_id268_at_idx9211
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule70_id268_at_idx9211
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule71_id608_at_idx9335
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule71_id608_at_idx9335
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule72_id609_at_idx9465
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule72_id609_at_idx9465
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule73_id2758_at_idx9595
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule73_id2758_at_idx9595
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule74_id2759_at_idx9697
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule74_id2759_at_idx9697
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule75_id2760_at_idx9799
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule75_id2760_at_idx9799
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLAHv8i16_:%[0-9]+]]:qpr = VQRDMLAHv8i16 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule76_id2761_at_idx9901
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule76_id2761_at_idx9901
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLAHv4i32_:%[0-9]+]]:qpr = VQRDMLAHv4i32 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule77_id2778_at_idx10003
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $q8
+
+    ; SELECTED-LABEL: name: test_rule77_id2778_at_idx10003
+    ; SELECTED: liveins: $d16, $d17, $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQDMLALv4i32_:%[0-9]+]]:qpr = VQDMLALv4i32 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLALv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q8
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule78_id2779_at_idx10103
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $q8
+
+    ; SELECTED-LABEL: name: test_rule78_id2779_at_idx10103
+    ; SELECTED: liveins: $d16, $d17, $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQDMLALv2i64_:%[0-9]+]]:qpr = VQDMLALv2i64 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLALv2i64_]]
+    %4:fprb(<2 x s64>) = COPY $q8
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule79_id111_at_idx10203
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule79_id111_at_idx10203
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDADD:%[0-9]+]]:gprnopc = QDADD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDADD]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %2(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %0(s32), %3(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule80_id1930_at_idx10298
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule80_id1930_at_idx10298
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDADD:%[0-9]+]]:gprnopc = QDADD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDADD]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %2(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %0(s32), %3(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule81_id2145_at_idx10393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule81_id2145_at_idx10393
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule82_id2146_at_idx10495
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule82_id2146_at_idx10495
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule83_id2147_at_idx10597
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule83_id2147_at_idx10597
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLAHv8i16_:%[0-9]+]]:qpr = VQRDMLAHv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule84_id2148_at_idx10699
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule84_id2148_at_idx10699
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLAHv4i32_:%[0-9]+]]:qpr = VQRDMLAHv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule85_id2153_at_idx10801
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule85_id2153_at_idx10801
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLSHv4i16_:%[0-9]+]]:dpr = VQRDMLSHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule86_id2154_at_idx10903
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule86_id2154_at_idx10903
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLSHv2i32_:%[0-9]+]]:dpr = VQRDMLSHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule87_id2155_at_idx11005
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule87_id2155_at_idx11005
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLSHv8i16_:%[0-9]+]]:qpr = VQRDMLSHv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule88_id2156_at_idx11107
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule88_id2156_at_idx11107
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMLSHv4i32_:%[0-9]+]]:qpr = VQRDMLSHv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule89_id2161_at_idx11209
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule89_id2161_at_idx11209
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMLALv4i32_:%[0-9]+]]:qpr = VQDMLALv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLALv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule90_id2162_at_idx11309
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule90_id2162_at_idx11309
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMLALv2i64_:%[0-9]+]]:qpr = VQDMLALv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLALv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule91_id2168_at_idx11409
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule91_id2168_at_idx11409
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMLSLv4i32_:%[0-9]+]]:qpr = VQDMLSLv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLSLv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule92_id2169_at_idx11509
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule92_id2169_at_idx11509
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMLSLv2i64_:%[0-9]+]]:qpr = VQDMLSLv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMLSLv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule93_id112_at_idx11609
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule93_id112_at_idx11609
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDSUB:%[0-9]+]]:gprnopc = QDSUB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDSUB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule94_id1931_at_idx11704
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule94_id1931_at_idx11704
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDSUB:%[0-9]+]]:gprnopc = QDSUB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDSUB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule95_id2470_at_idx11799
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule95_id2470_at_idx11799
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDADD:%[0-9]+]]:gprnopc = QDADD [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDADD]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule96_id2720_at_idx11894
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule96_id2720_at_idx11894
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QDADD:%[0-9]+]]:gprnopc = QDADD [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QDADD]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule97_id203_at_idx11989
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule97_id203_at_idx11989
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule98_id2479_at_idx12067
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule98_id2479_at_idx12067
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_AND %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule99_id2512_at_idx12174
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule99_id2512_at_idx12174
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_AND %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule100_id2478_at_idx12281
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule100_id2478_at_idx12281
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_AND %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule101_id2511_at_idx12388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule101_id2511_at_idx12388
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_AND %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule102_id2477_at_idx12495
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule102_id2477_at_idx12495
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule103_id2510_at_idx12602
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule103_id2510_at_idx12602
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule104_id161_at_idx12709
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule104_id161_at_idx12709
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule105_id494_at_idx12816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule105_id494_at_idx12816
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_AND %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule106_id2517_at_idx12923
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule106_id2517_at_idx12923
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNri:%[0-9]+]]:rgpr = t2ORNri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule107_id2516_at_idx13030
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule107_id2516_at_idx13030
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNri:%[0-9]+]]:rgpr = t2ORNri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_OR %0, %3
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule108_id2515_at_idx13137
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule108_id2515_at_idx13137
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNri:%[0-9]+]]:rgpr = t2ORNri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %4, %1
+    %2:gprb(s32) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule109_id500_at_idx13244
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule109_id500_at_idx13244
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNri:%[0-9]+]]:rgpr = t2ORNri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNri]]
+    %3:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_XOR %1, %4
+    %2:gprb(s32) = G_OR %3, %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule110_id2651_at_idx13351
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule110_id2651_at_idx13351
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv8i16_:%[0-9]+]]:qpr = VABALsv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv8i16_]]
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:fprb(<8 x s16>) = COPY $q8
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule111_id2652_at_idx13469
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule111_id2652_at_idx13469
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv4i32_:%[0-9]+]]:qpr = VABALsv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv4i32_]]
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:fprb(<4 x s32>) = COPY $q8
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule112_id2653_at_idx13587
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule112_id2653_at_idx13587
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv2i64_:%[0-9]+]]:qpr = VABALsv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv2i64_]]
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:fprb(<2 x s64>) = COPY $q8
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule113_id2654_at_idx13705
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule113_id2654_at_idx13705
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv8i16_:%[0-9]+]]:qpr = VABALuv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv8i16_]]
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:fprb(<8 x s16>) = COPY $q8
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule114_id2655_at_idx13823
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule114_id2655_at_idx13823
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv4i32_:%[0-9]+]]:qpr = VABALuv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv4i32_]]
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:fprb(<4 x s32>) = COPY $q8
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule115_id2656_at_idx13941
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule115_id2656_at_idx13941
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv2i64_:%[0-9]+]]:qpr = VABALuv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv2i64_]]
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:fprb(<2 x s64>) = COPY $q8
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule116_id1150_at_idx14059
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule116_id1150_at_idx14059
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv8i16_:%[0-9]+]]:qpr = VABALsv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv8i16_]]
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:fprb(<8 x s16>) = COPY $q8
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule117_id1151_at_idx14177
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule117_id1151_at_idx14177
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv4i32_:%[0-9]+]]:qpr = VABALsv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv4i32_]]
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:fprb(<4 x s32>) = COPY $q8
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule118_id1152_at_idx14295
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule118_id1152_at_idx14295
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALsv2i64_:%[0-9]+]]:qpr = VABALsv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALsv2i64_]]
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:fprb(<2 x s64>) = COPY $q8
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule119_id1153_at_idx14413
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule119_id1153_at_idx14413
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv8i16_:%[0-9]+]]:qpr = VABALuv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv8i16_]]
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:fprb(<8 x s16>) = COPY $q8
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule120_id1154_at_idx14531
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule120_id1154_at_idx14531
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv4i32_:%[0-9]+]]:qpr = VABALuv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv4i32_]]
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:fprb(<4 x s32>) = COPY $q8
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule121_id1155_at_idx14649
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule121_id1155_at_idx14649
+    ; SELECTED: liveins: $q8, $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABALuv2i64_:%[0-9]+]]:qpr = VABALuv2i64 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABALuv2i64_]]
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:fprb(<2 x s64>) = COPY $q8
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule122_id2520_at_idx14767
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule122_id2520_at_idx14767
+    ; SELECTED: [[t2MVNi:%[0-9]+]]:rgpr = t2MVNi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MVNi]]
+    %2:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule123_id503_at_idx14842
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule123_id503_at_idx14842
+    ; SELECTED: [[t2MVNi:%[0-9]+]]:rgpr = t2MVNi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MVNi]]
+    %2:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule124_id350_at_idx14917
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule124_id350_at_idx14917
+    ; SELECTED: t__brkdiv0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 249
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule125_id1725_at_idx14953
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule125_id1725_at_idx14953
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAT:%[0-9]+]]:gprnopc = USAT 1, [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAT]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule126_id1729_at_idx15036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule126_id1729_at_idx15036
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAT16_:%[0-9]+]]:gprnopc = USAT16 1, [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAT16_]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat16), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule127_id1935_at_idx15116
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule127_id1935_at_idx15116
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAT:%[0-9]+]]:gprnopc = USAT 1, [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAT]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule128_id1937_at_idx15199
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule128_id1937_at_idx15199
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAT16_:%[0-9]+]]:gprnopc = USAT16 1, [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAT16_]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat16), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule129_id2_at_idx15279
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule129_id2_at_idx15279
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule130_id10_at_idx15340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule130_id10_at_idx15340
+    ; SELECTED: DBG 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule131_id11_at_idx15401
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule131_id11_at_idx15401
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule132_id237_at_idx15456
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule132_id237_at_idx15456
+    ; SELECTED: DMB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule133_id238_at_idx15511
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule133_id238_at_idx15511
+    ; SELECTED: DSB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule134_id239_at_idx15566
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule134_id239_at_idx15566
+    ; SELECTED: ISB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule135_id285_at_idx15621
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule135_id285_at_idx15621
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule136_id349_at_idx15682
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule136_id349_at_idx15682
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule137_id498_at_idx15737
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule137_id498_at_idx15737
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule138_id572_at_idx15792
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule138_id572_at_idx15792
+    ; SELECTED: DMB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule139_id573_at_idx15853
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule139_id573_at_idx15853
+    ; SELECTED: DSB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule140_id574_at_idx15914
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule140_id574_at_idx15914
+    ; SELECTED: ISB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule141_id592_at_idx15975
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule141_id592_at_idx15975
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule142_id593_at_idx16036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule142_id593_at_idx16036
+    ; SELECTED: DBG 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule143_id1611_at_idx16097
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule143_id1611_at_idx16097
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2xsd:%[0-9]+]]:dpr = VCVTf2xsd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xsd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule144_id1612_at_idx16174
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule144_id1612_at_idx16174
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2xud:%[0-9]+]]:dpr = VCVTf2xud [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xud]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule145_id1613_at_idx16251
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule145_id1613_at_idx16251
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxs2fd:%[0-9]+]]:dpr = VCVTxs2fd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2fd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule146_id1614_at_idx16328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule146_id1614_at_idx16328
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxu2fd:%[0-9]+]]:dpr = VCVTxu2fd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2fd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule147_id1615_at_idx16405
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule147_id1615_at_idx16405
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2xsd:%[0-9]+]]:dpr = VCVTh2xsd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xsd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule148_id1616_at_idx16482
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule148_id1616_at_idx16482
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2xud:%[0-9]+]]:dpr = VCVTh2xud [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xud]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule149_id1617_at_idx16559
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule149_id1617_at_idx16559
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxs2hd:%[0-9]+]]:dpr = VCVTxs2hd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2hd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule150_id1618_at_idx16636
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule150_id1618_at_idx16636
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxu2hd:%[0-9]+]]:dpr = VCVTxu2hd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2hd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule151_id1619_at_idx16713
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule151_id1619_at_idx16713
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTf2xsq:%[0-9]+]]:qpr = VCVTf2xsq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xsq]]
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule152_id1620_at_idx16790
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule152_id1620_at_idx16790
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTf2xuq:%[0-9]+]]:qpr = VCVTf2xuq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xuq]]
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule153_id1621_at_idx16867
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule153_id1621_at_idx16867
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTxs2fq:%[0-9]+]]:qpr = VCVTxs2fq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2fq]]
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule154_id1622_at_idx16944
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule154_id1622_at_idx16944
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTxu2fq:%[0-9]+]]:qpr = VCVTxu2fq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2fq]]
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule155_id1623_at_idx17021
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule155_id1623_at_idx17021
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTh2xsq:%[0-9]+]]:qpr = VCVTh2xsq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xsq]]
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule156_id1624_at_idx17098
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule156_id1624_at_idx17098
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTh2xuq:%[0-9]+]]:qpr = VCVTh2xuq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xuq]]
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule157_id1625_at_idx17175
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule157_id1625_at_idx17175
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTxs2hq:%[0-9]+]]:qpr = VCVTxs2hq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2hq]]
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule158_id1626_at_idx17252
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule158_id1626_at_idx17252
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTxu2hq:%[0-9]+]]:qpr = VCVTxu2hq [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2hq]]
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule159_id1684_at_idx17329
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule159_id1684_at_idx17329
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SPACE:%[0-9]+]]:gpr = SPACE 1, [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SPACE]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule160_id2639_at_idx17403
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule160_id2639_at_idx17403
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule161_id2640_at_idx17501
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule161_id2640_at_idx17501
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule162_id2641_at_idx17599
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule162_id2641_at_idx17599
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule163_id2642_at_idx17697
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule163_id2642_at_idx17697
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv16i8_:%[0-9]+]]:qpr = VABAsv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fprb(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule164_id2643_at_idx17795
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule164_id2643_at_idx17795
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv8i16_:%[0-9]+]]:qpr = VABAsv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule165_id2644_at_idx17893
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule165_id2644_at_idx17893
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv4i32_:%[0-9]+]]:qpr = VABAsv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule166_id2645_at_idx17991
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule166_id2645_at_idx17991
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule167_id2646_at_idx18089
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule167_id2646_at_idx18089
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule168_id2647_at_idx18187
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule168_id2647_at_idx18187
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule169_id2648_at_idx18285
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule169_id2648_at_idx18285
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv16i8_:%[0-9]+]]:qpr = VABAuv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fprb(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule170_id2649_at_idx18383
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule170_id2649_at_idx18383
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv8i16_:%[0-9]+]]:qpr = VABAuv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule171_id2650_at_idx18481
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule171_id2650_at_idx18481
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv4i32_:%[0-9]+]]:qpr = VABAuv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule172_id1138_at_idx18579
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule172_id1138_at_idx18579
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule173_id1139_at_idx18677
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule173_id1139_at_idx18677
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule174_id1140_at_idx18775
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule174_id1140_at_idx18775
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule175_id1141_at_idx18873
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule175_id1141_at_idx18873
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv16i8_:%[0-9]+]]:qpr = VABAsv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fprb(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule176_id1142_at_idx18971
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule176_id1142_at_idx18971
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv8i16_:%[0-9]+]]:qpr = VABAsv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule177_id1143_at_idx19069
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule177_id1143_at_idx19069
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAsv4i32_:%[0-9]+]]:qpr = VABAsv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule178_id1144_at_idx19167
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule178_id1144_at_idx19167
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule179_id1145_at_idx19265
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule179_id1145_at_idx19265
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule180_id1146_at_idx19363
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule180_id1146_at_idx19363
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule181_id1147_at_idx19461
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule181_id1147_at_idx19461
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv16i8_:%[0-9]+]]:qpr = VABAuv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fprb(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule182_id1148_at_idx19559
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule182_id1148_at_idx19559
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv8i16_:%[0-9]+]]:qpr = VABAuv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fprb(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule183_id1149_at_idx19657
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule183_id1149_at_idx19657
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABAuv4i32_:%[0-9]+]]:qpr = VABAuv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fprb(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule184_id2480_at_idx19755
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule184_id2480_at_idx19755
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule185_id2513_at_idx19848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule185_id2513_at_idx19848
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule186_id162_at_idx19941
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule186_id162_at_idx19941
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule187_id495_at_idx20034
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule187_id495_at_idx20034
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule188_id336_at_idx20127
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule188_id336_at_idx20127
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule189_id542_at_idx20205
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule189_id542_at_idx20205
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule190_id2518_at_idx20283
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule190_id2518_at_idx20283
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule191_id501_at_idx20376
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule191_id501_at_idx20376
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ORNrr]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %3, %4
+    %1:gprb(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule192_id1132_at_idx20469
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule192_id1132_at_idx20469
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLsv8i16_:%[0-9]+]]:qpr = VABDLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLsv8i16_]]
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule193_id1133_at_idx20555
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule193_id1133_at_idx20555
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLsv4i32_:%[0-9]+]]:qpr = VABDLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLsv4i32_]]
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule194_id1134_at_idx20641
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule194_id1134_at_idx20641
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLsv2i64_:%[0-9]+]]:qpr = VABDLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLsv2i64_]]
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule195_id1135_at_idx20727
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule195_id1135_at_idx20727
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLuv8i16_:%[0-9]+]]:qpr = VABDLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLuv8i16_]]
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule196_id1136_at_idx20813
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule196_id1136_at_idx20813
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLuv4i32_:%[0-9]+]]:qpr = VABDLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLuv4i32_]]
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule197_id1137_at_idx20899
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule197_id1137_at_idx20899
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDLuv2i64_:%[0-9]+]]:qpr = VABDLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDLuv2i64_]]
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule198_id2094_at_idx20985
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule198_id2094_at_idx20985
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FNEG %4
+    %2:fprb(s64) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule199_id2095_at_idx21099
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
 
-  define void @test_rule1051_id1562_at_idx75356() {
-  entry:
-    unreachable
-  }
+    ; SELECTED-LABEL: name: test_rule199_id2095_at_idx21099
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FNEG %4
+    %2:fprb(s32) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s32)
 
-  define void @test_rule1052_id34_at_idx75406() {
-  entry:
-    unreachable
-  }
+...
+---
+name:            test_rule200_id758_at_idx21213
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
 
-  define void @test_rule1053_id291_at_idx75428() {
-  entry:
-    unreachable
-  }
+    ; SELECTED-LABEL: name: test_rule200_id758_at_idx21213
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLsv8i16_:%[0-9]+]]:qpr = VADDLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLsv8i16_]]
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:fprb(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
 
-  define void @test_rule1054_id590_at_idx75461() {
-  entry:
-    unreachable
-  }
+...
+---
+name:            test_rule201_id759_at_idx21315
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule201_id759_at_idx21315
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLsv4i32_:%[0-9]+]]:qpr = VADDLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLsv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:fprb(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
 
 ...
 ---
-name:            test_return
+name:            test_rule202_id760_at_idx21417
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule202_id760_at_idx21417
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLsv2i64_:%[0-9]+]]:qpr = VADDLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLsv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:fprb(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule203_id761_at_idx21519
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_return
-    ; SELECTED: $noreg = PATCHABLE_RET
-    $noreg = PATCHABLE_RET
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule203_id761_at_idx21519
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLuv8i16_:%[0-9]+]]:qpr = VADDLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLuv8i16_]]
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:fprb(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
 
 ...
 ---
-name:            test_rule0_id2693_at_idx0
+name:            test_rule204_id762_at_idx21621
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
-  - { id: 6, class: gprb }
-  - { id: 7, class: gprb }
-  - { id: 8, class: gprb }
-  - { id: 9, class: gprb }
-  - { id: 10, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%9' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule0_id2693_at_idx0
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
-    %9:gprb(s32) = COPY $lr
-    %8:gprb(s32) = G_CONSTANT 16
-    %10:gprb(s32) = G_CONSTANT 24
-    %5:gprb(s32) = G_CONSTANT 255
-    %7:gprb(s32) = G_CONSTANT 8
-    %3:gprb(s32) = G_SHL %9, %10
-    %2:gprb(s32) = G_ASHR %3, %8
-    %1:gprb(s32) = G_LSHR %9, %7
-    %0:gprb(s32) = G_AND %1, %5
-    %4:gprb(s32) = G_OR %0, %2
-    $noreg = PATCHABLE_RET %4(s32)
+    ; SELECTED-LABEL: name: test_rule204_id762_at_idx21621
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLuv4i32_:%[0-9]+]]:qpr = VADDLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLuv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:fprb(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
 
 ...
 ---
-name:            test_rule1_id2724_at_idx167
+name:            test_rule205_id763_at_idx21723
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
-  - { id: 6, class: gprb }
-  - { id: 7, class: gprb }
-  - { id: 8, class: gprb }
-  - { id: 9, class: gprb }
-  - { id: 10, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%9' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule1_id2724_at_idx167
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
-    %9:gprb(s32) = COPY $lr
-    %8:gprb(s32) = G_CONSTANT 16
-    %10:gprb(s32) = G_CONSTANT 24
-    %5:gprb(s32) = G_CONSTANT 255
-    %7:gprb(s32) = G_CONSTANT 8
-    %3:gprb(s32) = G_SHL %9, %10
-    %2:gprb(s32) = G_ASHR %3, %8
-    %1:gprb(s32) = G_LSHR %9, %7
-    %0:gprb(s32) = G_AND %1, %5
-    %4:gprb(s32) = G_OR %0, %2
-    $noreg = PATCHABLE_RET %4(s32)
+    ; SELECTED-LABEL: name: test_rule205_id763_at_idx21723
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDLuv2i64_:%[0-9]+]]:qpr = VADDLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDLuv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:fprb(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
 
 ...
 ---
-name:            test_rule4_id1713_at_idx668
+name:            test_rule206_id941_at_idx21825
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule4_id1713_at_idx668
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16711935
-    %4:gprb(s32) = G_CONSTANT 8
-    %0:gprb(s32) = G_LSHR %3, %4
-    %1:gprb(s32) = G_AND %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule206_id941_at_idx21825
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLsv8i16_:%[0-9]+]]:qpr = VSUBLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLsv8i16_]]
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:fprb(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
 
 ...
 ---
-name:            test_rule5_id1912_at_idx757
+name:            test_rule207_id942_at_idx21927
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule5_id1912_at_idx757
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16711935
-    %4:gprb(s32) = G_CONSTANT 8
-    %0:gprb(s32) = G_LSHR %3, %4
-    %1:gprb(s32) = G_AND %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule207_id942_at_idx21927
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLsv4i32_:%[0-9]+]]:qpr = VSUBLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLsv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:fprb(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
 
 ...
 ---
-name:            test_rule6_id2704_at_idx846
+name:            test_rule208_id943_at_idx22029
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule6_id2704_at_idx846
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule208_id943_at_idx22029
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLsv2i64_:%[0-9]+]]:qpr = VSUBLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLsv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:fprb(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
 
 ...
 ---
-name:            test_rule7_id2705_at_idx939
+name:            test_rule209_id944_at_idx22131
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule7_id2705_at_idx939
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule209_id944_at_idx22131
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLuv8i16_:%[0-9]+]]:qpr = VSUBLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLuv8i16_]]
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:fprb(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:fprb(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
 
 ...
 ---
-name:            test_rule8_id2732_at_idx1032
+name:            test_rule210_id945_at_idx22233
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule8_id2732_at_idx1032
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule210_id945_at_idx22233
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLuv4i32_:%[0-9]+]]:qpr = VSUBLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLuv4i32_]]
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:fprb(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:fprb(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
 
 ...
 ---
-name:            test_rule9_id2733_at_idx1125
+name:            test_rule211_id946_at_idx22335
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule9_id2733_at_idx1125
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule211_id946_at_idx22335
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBLuv2i64_:%[0-9]+]]:qpr = VSUBLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBLuv2i64_]]
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:fprb(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:fprb(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
 
 ...
 ---
-name:            test_rule10_id1819_at_idx1218
+name:            test_rule212_id504_at_idx22437
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4107,158 +11956,173 @@
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$lr', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule10_id1819_at_idx1218
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule212_id504_at_idx22437
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MVNr]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule11_id1820_at_idx1311
+name:            test_rule213_id2100_at_idx22498
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule11_id1820_at_idx1311
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule213_id2100_at_idx22498
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FMA %1, %3, %4
+    %2:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s64)
 
 ...
 ---
-name:            test_rule12_id1999_at_idx1404
+name:            test_rule214_id2101_at_idx22612
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $s0, $s2, $s4
 
-    ; SELECTED-LABEL: name: test_rule12_id1999_at_idx1404
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule214_id2101_at_idx22612
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FMA %1, %3, %4
+    %2:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s32)
 
 ...
 ---
-name:            test_rule13_id2000_at_idx1497
+name:            test_rule215_id2102_at_idx22726
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
-  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule13_id2000_at_idx1497
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
-    %3:gprb(s32) = COPY $r0
-    %2:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %3, %4
-    %1:gprb(s32) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule215_id2102_at_idx22726
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FMA %3, %1, %4
+    %2:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s64)
 
 ...
 ---
-name:            test_rule14_id255_at_idx1590
+name:            test_rule216_id2103_at_idx22840
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule14_id255_at_idx1590
-    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = G_CONSTANT 1
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule216_id2103_at_idx22840
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FMA %3, %1, %4
+    %2:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s32)
 
 ...
 ---
-name:            test_rule15_id256_at_idx1768
+name:            test_rule217_id148_at_idx22954
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4268,25 +12132,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule15_id256_at_idx1768
-    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = G_CONSTANT 1
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule217_id148_at_idx22954
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule16_id610_at_idx1940
+name:            test_rule218_id473_at_idx23032
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4296,25 +12165,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule16_id610_at_idx1940
-    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = G_CONSTANT 1
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule218_id473_at_idx23032
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule17_id611_at_idx2118
+name:            test_rule219_id532_at_idx23110
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4324,25 +12198,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule17_id611_at_idx2118
-    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = G_CONSTANT 1
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
-    $noreg = PATCHABLE_RET
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule219_id532_at_idx23110
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLAD:%[0-9]+]]:rgpr = t2SMLAD [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLAD]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlad), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule31_id1816_at_idx4333
+name:            test_rule220_id533_at_idx23188
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4351,25 +12230,31 @@
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
   - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule31_id1816_at_idx4333
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    ; SELECTED-LABEL: name: test_rule220_id533_at_idx23188
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLADX:%[0-9]+]]:rgpr = t2SMLADX [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLADX]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
     %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %1, %2
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smladx), %1(s32), %2(s32), %3(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule32_id1817_at_idx4394
+name:            test_rule221_id534_at_idx23266
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4378,25 +12263,31 @@
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
   - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule32_id1817_at_idx4394
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    ; SELECTED-LABEL: name: test_rule221_id534_at_idx23266
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLSD:%[0-9]+]]:rgpr = t2SMLSD [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLSD]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
     %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %1, %2
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsd), %1(s32), %2(s32), %3(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule33_id1818_at_idx4455
+name:            test_rule222_id535_at_idx23344
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4405,156 +12296,196 @@
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
   - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule33_id1818_at_idx4455
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    ; SELECTED-LABEL: name: test_rule222_id535_at_idx23344
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLSDX:%[0-9]+]]:rgpr = t2SMLSDX [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLSDX]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
     %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16711935
-    %0:gprb(s32) = G_AND %1, %2
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsdx), %1(s32), %2(s32), %3(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule34_id1996_at_idx4516
+name:            test_rule223_id1649_at_idx23422
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule34_id1996_at_idx4516
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
-    %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule223_id1649_at_idx23422
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTBX1_:%[0-9]+]]:dpr = VTBX1 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTBX1_]]
+    %3:fprb(<8 x s8>) = COPY $d18
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule35_id1997_at_idx4577
+name:            test_rule224_id1680_at_idx23500
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8, $q9, $q10
 
-    ; SELECTED-LABEL: name: test_rule35_id1997_at_idx4577
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
-    %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule224_id1680_at_idx23500
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA1SU0_:%[0-9]+]]:qpr = SHA1SU0 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1SU0_]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule36_id1998_at_idx4638
+name:            test_rule225_id1681_at_idx23572
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8, $q9, $q10
 
-    ; SELECTED-LABEL: name: test_rule36_id1998_at_idx4638
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
-    %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16711935
-    %0:gprb(s32) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule225_id1681_at_idx23572
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA256H:%[0-9]+]]:qpr = SHA256H [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256H]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule37_id1714_at_idx4699
+name:            test_rule226_id1682_at_idx23644
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8, $q9, $q10
 
-    ; SELECTED-LABEL: name: test_rule37_id1714_at_idx4699
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule226_id1682_at_idx23644
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA256H2_:%[0-9]+]]:qpr = SHA256H2 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256H2_]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule38_id1911_at_idx4756
+name:            test_rule227_id1683_at_idx23716
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8, $q9, $q10
 
-    ; SELECTED-LABEL: name: test_rule38_id1911_at_idx4756
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule227_id1683_at_idx23716
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA256SU1_:%[0-9]+]]:qpr = SHA256SU1 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256SU1_]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule43_id265_at_idx5471
+name:            test_rule228_id1735_at_idx23788
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4564,31 +12495,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule43_id265_at_idx5471
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule228_id1735_at_idx23788
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLAD:%[0-9]+]]:rgpr = t2SMLAD [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLAD]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlad), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule44_id266_at_idx5637
+name:            test_rule229_id1736_at_idx23866
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4598,31 +12528,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule44_id266_at_idx5637
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule229_id1736_at_idx23866
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLADX:%[0-9]+]]:rgpr = t2SMLADX [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLADX]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smladx), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule45_id606_at_idx5797
+name:            test_rule230_id1737_at_idx23944
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4632,31 +12561,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%5' }
-body:             |
-  bb.0.entry:
-    liveins: $lr
-
-    ; SELECTED-LABEL: name: test_rule45_id606_at_idx5797
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-    $noreg = PATCHABLE_RET
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule230_id1737_at_idx23944
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLSD:%[0-9]+]]:rgpr = t2SMLSD [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLSD]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsd), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule46_id607_at_idx5963
+name:            test_rule231_id1738_at_idx24022
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4666,31 +12594,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule46_id607_at_idx5963
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %5:gprb(s32) = COPY $lr
-    %4:gprb(s32) = G_CONSTANT 1
-    %3:gprb(s32) = G_CONSTANT 1
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule231_id1738_at_idx24022
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMLSDX:%[0-9]+]]:rgpr = t2SMLSDX [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMLSDX]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsdx), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule51_id188_at_idx6729
+name:            test_rule232_id1809_at_idx24100
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4700,34 +12627,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
-  - { id: 6, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule51_id188_at_idx6729
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
-    %5:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %6:gprb(s32) = G_CONSTANT 16
-    %4:gprb(s32) = G_CONSTANT 16
-    %1:gprb(s32) = G_ASHR %5, %6
-    %0:gprb(s32) = G_ASHR %3, %4
-    %2:gprb(s32) = G_MUL %0, %1
-    $noreg = PATCHABLE_RET %2(s32)
+    ; SELECTED-LABEL: name: test_rule232_id1809_at_idx24100
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLABB:%[0-9]+]]:gprnopc = SMLABB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLABB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule52_id519_at_idx6847
+name:            test_rule233_id1810_at_idx24178
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4737,34 +12660,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-  - { id: 5, class: gprb }
-  - { id: 6, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule52_id519_at_idx6847
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
-    %5:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %6:gprb(s32) = G_CONSTANT 16
-    %4:gprb(s32) = G_CONSTANT 16
-    %1:gprb(s32) = G_ASHR %5, %6
-    %0:gprb(s32) = G_ASHR %3, %4
-    %2:gprb(s32) = G_MUL %0, %1
-    $noreg = PATCHABLE_RET %2(s32)
+    ; SELECTED-LABEL: name: test_rule233_id1810_at_idx24178
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLABT:%[0-9]+]]:gprnopc = SMLABT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLABT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule69_id267_at_idx9081
+name:            test_rule234_id1811_at_idx24256
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4774,31 +12693,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule69_id267_at_idx9081
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %4:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule234_id1811_at_idx24256
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLATB:%[0-9]+]]:gprnopc = SMLATB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule70_id268_at_idx9211
+name:            test_rule235_id1812_at_idx24334
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4808,31 +12726,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule70_id268_at_idx9211
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %4:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule235_id1812_at_idx24334
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule71_id608_at_idx9335
+name:            test_rule236_id1813_at_idx24412
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4842,31 +12759,30 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule71_id608_at_idx9335
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %4:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule236_id1813_at_idx24412
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLAWB:%[0-9]+]]:gprnopc = SMLAWB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLAWB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule72_id609_at_idx9465
+name:            test_rule237_id1814_at_idx24490
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -4876,233 +12792,228 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
   - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
-  - { reg: '$r0', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule72_id609_at_idx9465
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %4:gprb(s32) = COPY $r0
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_CONSTANT 1
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED-LABEL: name: test_rule237_id1814_at_idx24490
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLAWT:%[0-9]+]]:gprnopc = SMLAWT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLAWT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule73_id2758_at_idx9595
+name:            test_rule238_id1955_at_idx24568
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule73_id2758_at_idx9595
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule238_id1955_at_idx24568
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLABB:%[0-9]+]]:gprnopc = SMLABB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLABB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule74_id2759_at_idx9697
+name:            test_rule239_id1956_at_idx24646
 alignment:       2
 legalized:       true
 regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule74_id2759_at_idx9697
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule239_id1956_at_idx24646
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLABT:%[0-9]+]]:gprnopc = SMLABT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLABT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule75_id2760_at_idx9799
+name:            test_rule240_id1957_at_idx24724
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule75_id2760_at_idx9799
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule240_id1957_at_idx24724
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLATB:%[0-9]+]]:gprnopc = SMLATB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule76_id2761_at_idx9901
+name:            test_rule241_id1958_at_idx24802
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule76_id2761_at_idx9901
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule241_id1958_at_idx24802
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLATT:%[0-9]+]]:gprnopc = SMLATT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLATT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule77_id2778_at_idx10003
+name:            test_rule242_id1959_at_idx24880
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule77_id2778_at_idx10003
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<4 x s32>), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule242_id1959_at_idx24880
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLAWB:%[0-9]+]]:gprnopc = SMLAWB [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLAWB]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawb), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule78_id2779_at_idx10103
+name:            test_rule243_id1960_at_idx24958
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0, $r1
 
-    ; SELECTED-LABEL: name: test_rule78_id2779_at_idx10103
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<2 x s64>), [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %4:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule243_id1960_at_idx24958
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SMLAWT:%[0-9]+]]:gprnopc = SMLAWT [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLAWT]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawt), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule81_id2145_at_idx10393
+name:            test_rule244_id2181_at_idx25036
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -5112,32 +13023,30 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
   - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule81_id2145_at_idx10393
+    ; SELECTED-LABEL: name: test_rule244_id2181_at_idx25036
     ; SELECTED: liveins: $d16, $d17, $d18
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<8 x s8>) = COPY $d18
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule82_id2146_at_idx10495
+name:            test_rule245_id2182_at_idx25114
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -5147,92 +13056,30 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
   - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule82_id2146_at_idx10495
+    ; SELECTED-LABEL: name: test_rule245_id2182_at_idx25114
     ; SELECTED: liveins: $d16, $d17, $d18
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
-
-...
----
-name:            test_rule83_id2147_at_idx10597
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule83_id2147_at_idx10597
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<8 x s16>), [[INT]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule84_id2148_at_idx10699
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule84_id2148_at_idx10699
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<4 x s16>) = COPY $d18
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule85_id2153_at_idx10801
+name:            test_rule246_id2183_at_idx25192
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -5242,32 +13089,30 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
   - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule85_id2153_at_idx10801
+    ; SELECTED-LABEL: name: test_rule246_id2183_at_idx25192
     ; SELECTED: liveins: $d16, $d17, $d18
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLSHv4i16_:%[0-9]+]]:dpr = VQRDMLSHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<2 x s32>) = COPY $d18
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule86_id2154_at_idx10903
+name:            test_rule248_id2185_at_idx25348
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -5277,236 +13122,249 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
   - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17, $d18
 
-    ; SELECTED-LABEL: name: test_rule86_id2154_at_idx10903
+    ; SELECTED-LABEL: name: test_rule248_id2185_at_idx25348
     ; SELECTED: liveins: $d16, $d17, $d18
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMLSHv2i32_:%[0-9]+]]:dpr = VQRDMLSHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(s64) = COPY $d18
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule249_id2188_at_idx25426
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule249_id2188_at_idx25426
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VBSLq:%[0-9]+]]:qpr = VBSLq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLq]]
+    %3:fprb(<16 x s8>) = COPY $q10
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule87_id2155_at_idx11005
+name:            test_rule250_id2189_at_idx25504
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule87_id2155_at_idx11005
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<8 x s16>), [[INT]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule250_id2189_at_idx25504
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VBSLq:%[0-9]+]]:qpr = VBSLq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLq]]
+    %3:fprb(<8 x s16>) = COPY $q10
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule88_id2156_at_idx11107
+name:            test_rule251_id2190_at_idx25582
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule88_id2156_at_idx11107
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule251_id2190_at_idx25582
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VBSLq:%[0-9]+]]:qpr = VBSLq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLq]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule89_id2161_at_idx11209
+name:            test_rule253_id2192_at_idx25738
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9, $q10
 
-    ; SELECTED-LABEL: name: test_rule89_id2161_at_idx11209
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule253_id2192_at_idx25738
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VBSLq:%[0-9]+]]:qpr = VBSLq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLq]]
+    %3:fprb(<2 x s64>) = COPY $q10
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule90_id2162_at_idx11309
+name:            test_rule254_id107_at_idx25816
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule90_id2162_at_idx11309
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<2 x s64>), [[INT]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
-    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule254_id107_at_idx25816
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD8_:%[0-9]+]]:gprnopc = QADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule91_id2168_at_idx11409
+name:            test_rule255_id108_at_idx25882
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule91_id2168_at_idx11409
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule255_id108_at_idx25882
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD16_:%[0-9]+]]:gprnopc = QADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule92_id2169_at_idx11509
+name:            test_rule256_id109_at_idx25948
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule92_id2169_at_idx11509
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<2 x s64>), [[INT]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
-    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule256_id109_at_idx25948
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB16_:%[0-9]+]]:gprnopc = QSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule97_id203_at_idx11989
+name:            test_rule257_id110_at_idx26014
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -5515,1173 +13373,1274 @@
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule97_id203_at_idx11989
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16
-    %0:gprb(s32) = G_BSWAP %3
-    %1:gprb(s32) = G_ASHR %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule257_id110_at_idx26014
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB8_:%[0-9]+]]:gprnopc = QSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule110_id2651_at_idx13351
+name:            test_rule258_id113_at_idx26080
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule110_id2651_at_idx13351
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %5:fprb(<8 x s8>) = COPY $d17
-    %4:fprb(<8 x s8>) = COPY $d16
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule258_id113_at_idx26080
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB:%[0-9]+]]:gprnopc = QSUB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule111_id2652_at_idx13469
+name:            test_rule259_id114_at_idx26146
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule111_id2652_at_idx13469
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %5:fprb(<4 x s16>) = COPY $d17
-    %4:fprb(<4 x s16>) = COPY $d16
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule259_id114_at_idx26146
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD:%[0-9]+]]:gprnopc = QADD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule112_id2653_at_idx13587
+name:            test_rule260_id115_at_idx26212
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule112_id2653_at_idx13587
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %5:fprb(<2 x s32>) = COPY $d17
-    %4:fprb(<2 x s32>) = COPY $d16
-    %3:_(<2 x s64>) = IMPLICIT_DEF
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule260_id115_at_idx26212
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQADD16_:%[0-9]+]]:gprnopc = UQADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule113_id2654_at_idx13705
+name:            test_rule261_id116_at_idx26278
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule113_id2654_at_idx13705
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %5:fprb(<8 x s8>) = COPY $d17
-    %4:fprb(<8 x s8>) = COPY $d16
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule261_id116_at_idx26278
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQADD8_:%[0-9]+]]:gprnopc = UQADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule114_id2655_at_idx13823
+name:            test_rule262_id117_at_idx26344
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule114_id2655_at_idx13823
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %5:fprb(<4 x s16>) = COPY $d17
-    %4:fprb(<4 x s16>) = COPY $d16
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule262_id117_at_idx26344
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSUB16_:%[0-9]+]]:gprnopc = UQSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule115_id2656_at_idx13941
+name:            test_rule263_id118_at_idx26410
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule115_id2656_at_idx13941
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %5:fprb(<2 x s32>) = COPY $d17
-    %4:fprb(<2 x s32>) = COPY $d16
-    %3:_(<2 x s64>) = IMPLICIT_DEF
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %0, %3
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule263_id118_at_idx26410
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSUB8_:%[0-9]+]]:gprnopc = UQSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule116_id1150_at_idx14059
+name:            test_rule264_id119_at_idx26476
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule116_id1150_at_idx14059
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %5:fprb(<8 x s8>) = COPY $d17
-    %4:fprb(<8 x s8>) = COPY $d16
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule264_id119_at_idx26476
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QASX:%[0-9]+]]:gprnopc = QASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule117_id1151_at_idx14177
+name:            test_rule265_id120_at_idx26542
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule117_id1151_at_idx14177
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %5:fprb(<4 x s16>) = COPY $d17
-    %4:fprb(<4 x s16>) = COPY $d16
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule265_id120_at_idx26542
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSAX:%[0-9]+]]:gprnopc = QSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule118_id1152_at_idx14295
+name:            test_rule266_id121_at_idx26608
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule118_id1152_at_idx14295
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %5:fprb(<2 x s32>) = COPY $d17
-    %4:fprb(<2 x s32>) = COPY $d16
-    %3:_(<2 x s64>) = IMPLICIT_DEF
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule266_id121_at_idx26608
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQASX:%[0-9]+]]:gprnopc = UQASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule119_id1153_at_idx14413
+name:            test_rule267_id122_at_idx26674
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule119_id1153_at_idx14413
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %5:fprb(<8 x s8>) = COPY $d17
-    %4:fprb(<8 x s8>) = COPY $d16
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule267_id122_at_idx26674
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSAX:%[0-9]+]]:gprnopc = UQSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule120_id1154_at_idx14531
+name:            test_rule268_id135_at_idx26740
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule120_id1154_at_idx14531
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %5:fprb(<4 x s16>) = COPY $d17
-    %4:fprb(<4 x s16>) = COPY $d16
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule268_id135_at_idx26740
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHASX:%[0-9]+]]:gprnopc = SHASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule121_id1155_at_idx14649
+name:            test_rule269_id136_at_idx26806
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: fprb }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%4' }
-  - { reg: '$d17', virtual-reg: '%5' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule121_id1155_at_idx14649
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %5:fprb(<2 x s32>) = COPY $d17
-    %4:fprb(<2 x s32>) = COPY $d16
-    %3:_(<2 x s64>) = IMPLICIT_DEF
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %3, %0
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule269_id136_at_idx26806
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHADD16_:%[0-9]+]]:gprnopc = SHADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule124_id350_at_idx14917
+name:            test_rule270_id137_at_idx26872
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule124_id350_at_idx14917
-    ; SELECTED: t__brkdiv0
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 249
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule270_id137_at_idx26872
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHADD8_:%[0-9]+]]:gprnopc = SHADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule129_id2_at_idx15279
+name:            test_rule271_id138_at_idx26938
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule129_id2_at_idx15279
-    ; SELECTED: HINT 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule271_id138_at_idx26938
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSAX:%[0-9]+]]:gprnopc = SHSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule130_id10_at_idx15340
+name:            test_rule272_id139_at_idx27004
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule130_id10_at_idx15340
-    ; SELECTED: DBG 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule272_id139_at_idx27004
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSUB16_:%[0-9]+]]:gprnopc = SHSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule131_id11_at_idx15401
+name:            test_rule273_id140_at_idx27070
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule131_id11_at_idx15401
-    ; SELECTED: UDF 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule273_id140_at_idx27070
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSUB8_:%[0-9]+]]:gprnopc = SHSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule132_id237_at_idx15456
+name:            test_rule274_id141_at_idx27136
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule132_id237_at_idx15456
-    ; SELECTED: DMB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule274_id141_at_idx27136
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHASX:%[0-9]+]]:gprnopc = UHASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule133_id238_at_idx15511
+name:            test_rule275_id142_at_idx27202
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule133_id238_at_idx15511
-    ; SELECTED: DSB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule275_id142_at_idx27202
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHADD16_:%[0-9]+]]:gprnopc = UHADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule134_id239_at_idx15566
+name:            test_rule276_id143_at_idx27268
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule134_id239_at_idx15566
-    ; SELECTED: ISB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule276_id143_at_idx27268
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHADD8_:%[0-9]+]]:gprnopc = UHADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule135_id285_at_idx15621
+name:            test_rule277_id144_at_idx27334
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule135_id285_at_idx15621
-    ; SELECTED: HINT 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule277_id144_at_idx27334
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSAX:%[0-9]+]]:gprnopc = UHSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule136_id349_at_idx15682
+name:            test_rule278_id145_at_idx27400
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule136_id349_at_idx15682
-    ; SELECTED: UDF 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule278_id145_at_idx27400
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSUB16_:%[0-9]+]]:gprnopc = UHSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule137_id498_at_idx15737
+name:            test_rule279_id146_at_idx27466
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule137_id498_at_idx15737
-    ; SELECTED: UDF 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule279_id146_at_idx27466
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSUB8_:%[0-9]+]]:gprnopc = UHSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule138_id572_at_idx15792
+name:            test_rule280_id147_at_idx27532
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule138_id572_at_idx15792
-    ; SELECTED: DMB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule280_id147_at_idx27532
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USAD8_:%[0-9]+]]:gpr = USAD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usad8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule139_id573_at_idx15853
+name:            test_rule281_id206_at_idx27598
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule139_id573_at_idx15853
-    ; SELECTED: DSB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule281_id206_at_idx27598
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32B:%[0-9]+]]:gprnopc = CRC32B [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32B]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32b), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule140_id574_at_idx15914
+name:            test_rule282_id207_at_idx27658
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule140_id574_at_idx15914
-    ; SELECTED: ISB 1
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule282_id207_at_idx27658
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CB:%[0-9]+]]:gprnopc = CRC32CB [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule141_id592_at_idx15975
+name:            test_rule283_id208_at_idx27718
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule141_id592_at_idx15975
-    ; SELECTED: HINT 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule283_id208_at_idx27718
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32H:%[0-9]+]]:gprnopc = CRC32H [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32H]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32h), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule142_id593_at_idx16036
+name:            test_rule284_id209_at_idx27778
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule142_id593_at_idx16036
-    ; SELECTED: DBG 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = G_CONSTANT 1
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
-    $noreg = PATCHABLE_RET
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule284_id209_at_idx27778
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CH:%[0-9]+]]:gprnopc = CRC32CH [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CH]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32ch), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule143_id1611_at_idx16097
+name:            test_rule285_id210_at_idx27838
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d16
-
-    ; SELECTED-LABEL: name: test_rule143_id1611_at_idx16097
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTf2xsd:%[0-9]+]]:dpr = VCVTf2xsd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xsd]]
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule285_id210_at_idx27838
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32W:%[0-9]+]]:gprnopc = CRC32W [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32W]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32w), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule144_id1612_at_idx16174
+name:            test_rule286_id211_at_idx27898
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule144_id1612_at_idx16174
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTf2xud:%[0-9]+]]:dpr = VCVTf2xud [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xud]]
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule286_id211_at_idx27898
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CW:%[0-9]+]]:gprnopc = CRC32CW [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CW]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cw), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule145_id1613_at_idx16251
+name:            test_rule287_id436_at_idx27958
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule145_id1613_at_idx16251
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTxs2fd:%[0-9]+]]:dpr = VCVTxs2fd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2fd]]
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule287_id436_at_idx27958
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD16_:%[0-9]+]]:gprnopc = QADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule146_id1614_at_idx16328
+name:            test_rule288_id437_at_idx28024
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule146_id1614_at_idx16328
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTxu2fd:%[0-9]+]]:dpr = VCVTxu2fd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2fd]]
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule288_id437_at_idx28024
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD8_:%[0-9]+]]:gprnopc = QADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule147_id1615_at_idx16405
+name:            test_rule289_id438_at_idx28090
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule147_id1615_at_idx16405
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTh2xsd:%[0-9]+]]:dpr = VCVTh2xsd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xsd]]
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule289_id438_at_idx28090
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QASX:%[0-9]+]]:gprnopc = QASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule148_id1616_at_idx16482
+name:            test_rule290_id439_at_idx28156
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule148_id1616_at_idx16482
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTh2xud:%[0-9]+]]:dpr = VCVTh2xud [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xud]]
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule290_id439_at_idx28156
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSUB8_:%[0-9]+]]:gprnopc = UQSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule149_id1617_at_idx16559
+name:            test_rule291_id440_at_idx28222
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule149_id1617_at_idx16559
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTxs2hd:%[0-9]+]]:dpr = VCVTxs2hd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2hd]]
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule291_id440_at_idx28222
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSAX:%[0-9]+]]:gprnopc = QSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule150_id1618_at_idx16636
+name:            test_rule292_id441_at_idx28288
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule150_id1618_at_idx16636
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTxu2hd:%[0-9]+]]:dpr = VCVTxu2hd [[COPY]], 1, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2hd]]
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(s32) = G_CONSTANT 1
-    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule292_id441_at_idx28288
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB16_:%[0-9]+]]:gprnopc = QSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule151_id1619_at_idx16713
+name:            test_rule293_id442_at_idx28354
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule151_id1619_at_idx16713
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), [[DEF]](<4 x s32>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule293_id442_at_idx28354
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB8_:%[0-9]+]]:gprnopc = QSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule152_id1620_at_idx16790
+name:            test_rule294_id443_at_idx28420
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule152_id1620_at_idx16790
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), [[DEF]](<4 x s32>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule294_id443_at_idx28420
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQADD16_:%[0-9]+]]:gprnopc = UQADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule153_id1621_at_idx16867
+name:            test_rule295_id444_at_idx28486
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule153_id1621_at_idx16867
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), [[DEF]](<4 x s32>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule295_id444_at_idx28486
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQADD8_:%[0-9]+]]:gprnopc = UQADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule154_id1622_at_idx16944
+name:            test_rule296_id445_at_idx28552
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule154_id1622_at_idx16944
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), [[DEF]](<4 x s32>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule296_id445_at_idx28552
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQASX:%[0-9]+]]:gprnopc = UQASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule155_id1623_at_idx17021
+name:            test_rule297_id446_at_idx28618
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule155_id1623_at_idx17021
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), [[DEF]](<8 x s16>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule297_id446_at_idx28618
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSAX:%[0-9]+]]:gprnopc = UQSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule156_id1624_at_idx17098
+name:            test_rule298_id447_at_idx28684
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule156_id1624_at_idx17098
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), [[DEF]](<8 x s16>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule298_id447_at_idx28684
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UQSUB16_:%[0-9]+]]:gprnopc = UQSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule157_id1625_at_idx17175
+name:            test_rule299_id460_at_idx28750
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule157_id1625_at_idx17175
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), [[DEF]](<8 x s16>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule299_id460_at_idx28750
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHASX:%[0-9]+]]:gprnopc = SHASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule158_id1626_at_idx17252
+name:            test_rule300_id461_at_idx28816
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule158_id1626_at_idx17252
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), [[DEF]](<8 x s16>), [[C]](s32)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule300_id461_at_idx28816
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHADD16_:%[0-9]+]]:gprnopc = SHADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule159_id1684_at_idx17329
+name:            test_rule301_id462_at_idx28882
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -6691,679 +14650,606 @@
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule159_id1684_at_idx17329
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[SPACE:%[0-9]+]]:gpr = SPACE 1, [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SPACE]]
-    %2:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule301_id462_at_idx28882
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHADD8_:%[0-9]+]]:gprnopc = SHADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule160_id2639_at_idx17403
+name:            test_rule302_id463_at_idx28948
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule160_id2639_at_idx17403
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
-    %4:fprb(<8 x s8>) = COPY $d18
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
-    %1:fprb(<8 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule302_id463_at_idx28948
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSAX:%[0-9]+]]:gprnopc = SHSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule161_id2640_at_idx17501
+name:            test_rule303_id464_at_idx29014
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule161_id2640_at_idx17501
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule303_id464_at_idx29014
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSUB16_:%[0-9]+]]:gprnopc = SHSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule162_id2641_at_idx17599
+name:            test_rule304_id465_at_idx29080
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule162_id2641_at_idx17599
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule304_id465_at_idx29080
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SHSUB8_:%[0-9]+]]:gprnopc = SHSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule163_id2642_at_idx17697
+name:            test_rule305_id466_at_idx29146
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule163_id2642_at_idx17697
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
-    %1:_(<16 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule305_id466_at_idx29146
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHASX:%[0-9]+]]:gprnopc = UHASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule164_id2643_at_idx17795
+name:            test_rule306_id467_at_idx29212
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule164_id2643_at_idx17795
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule306_id467_at_idx29212
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHADD16_:%[0-9]+]]:gprnopc = UHADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule165_id2644_at_idx17893
+name:            test_rule307_id468_at_idx29278
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule165_id2644_at_idx17893
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule307_id468_at_idx29278
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHADD8_:%[0-9]+]]:gprnopc = UHADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule166_id2645_at_idx17991
+name:            test_rule308_id469_at_idx29344
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule166_id2645_at_idx17991
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
-    %4:fprb(<8 x s8>) = COPY $d18
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
-    %1:fprb(<8 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule308_id469_at_idx29344
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSAX:%[0-9]+]]:gprnopc = UHSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule167_id2646_at_idx18089
+name:            test_rule309_id470_at_idx29410
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule167_id2646_at_idx18089
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule309_id470_at_idx29410
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSUB16_:%[0-9]+]]:gprnopc = UHSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule168_id2647_at_idx18187
+name:            test_rule310_id471_at_idx29476
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule168_id2647_at_idx18187
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule310_id471_at_idx29476
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UHSUB8_:%[0-9]+]]:gprnopc = UHSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule169_id2648_at_idx18285
+name:            test_rule311_id472_at_idx29542
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule169_id2648_at_idx18285
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
-    %1:_(<16 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule311_id472_at_idx29542
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USAD8_:%[0-9]+]]:gpr = USAD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usad8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule170_id2649_at_idx18383
+name:            test_rule312_id528_at_idx29608
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule170_id2649_at_idx18383
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule312_id528_at_idx29608
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUAD:%[0-9]+]]:rgpr = t2SMUAD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUAD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuad), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule171_id2650_at_idx18481
+name:            test_rule313_id529_at_idx29674
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule171_id2650_at_idx18481
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[INT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule313_id529_at_idx29674
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUADX:%[0-9]+]]:rgpr = t2SMUADX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUADX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuadx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule172_id1138_at_idx18579
+name:            test_rule314_id530_at_idx29740
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule172_id1138_at_idx18579
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
-    %4:fprb(<8 x s8>) = COPY $d18
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
-    %1:fprb(<8 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule314_id530_at_idx29740
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUSD:%[0-9]+]]:rgpr = t2SMUSD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUSD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule173_id1139_at_idx18677
+name:            test_rule315_id531_at_idx29806
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule173_id1139_at_idx18677
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule315_id531_at_idx29806
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUSDX:%[0-9]+]]:rgpr = t2SMUSDX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUSDX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusdx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule174_id1140_at_idx18775
+name:            test_rule316_id545_at_idx29872
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule174_id1140_at_idx18775
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule316_id545_at_idx29872
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32B:%[0-9]+]]:gprnopc = CRC32B [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32B]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32b), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule175_id1141_at_idx18873
+name:            test_rule317_id546_at_idx29932
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule175_id1141_at_idx18873
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
-    %1:_(<16 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule317_id546_at_idx29932
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CB:%[0-9]+]]:gprnopc = CRC32CB [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule176_id1142_at_idx18971
+name:            test_rule318_id547_at_idx29992
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule176_id1142_at_idx18971
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule318_id547_at_idx29992
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32H:%[0-9]+]]:gprnopc = CRC32H [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32H]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32h), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule177_id1143_at_idx19069
+name:            test_rule319_id548_at_idx30052
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule177_id1143_at_idx19069
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule319_id548_at_idx30052
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CH:%[0-9]+]]:gprnopc = CRC32CH [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CH]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32ch), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule178_id1144_at_idx19167
+name:            test_rule320_id549_at_idx30112
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule178_id1144_at_idx19167
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
-    %4:fprb(<8 x s8>) = COPY $d18
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
-    %1:fprb(<8 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule320_id549_at_idx30112
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32W:%[0-9]+]]:gprnopc = CRC32W [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32W]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32w), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule179_id1145_at_idx19265
+name:            test_rule321_id550_at_idx30172
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule179_id1145_at_idx19265
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
-    %4:fprb(<4 x s16>) = COPY $d18
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
-    %1:fprb(<4 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule321_id550_at_idx30172
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[CRC32CW:%[0-9]+]]:gprnopc = CRC32CW [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CW]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cw), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule180_id1146_at_idx19363
+name:            test_rule322_id770_at_idx30232
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -7372,379 +15258,346 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
-  - { reg: '$d18', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule180_id1146_at_idx19363
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
-    %4:fprb(<2 x s32>) = COPY $d18
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
-    %1:fprb(<2 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule322_id770_at_idx30232
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv4i16_:%[0-9]+]]:dpr = VHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule181_id1147_at_idx19461
+name:            test_rule323_id771_at_idx30298
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule181_id1147_at_idx19461
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
-    %1:_(<16 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule323_id771_at_idx30298
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv2i32_:%[0-9]+]]:dpr = VHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule182_id1148_at_idx19559
+name:            test_rule324_id772_at_idx30364
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule182_id1148_at_idx19559
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
-    %1:_(<8 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule324_id772_at_idx30364
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDsv8i16_:%[0-9]+]]:qpr = VHADDsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule183_id1149_at_idx19657
+name:            test_rule325_id773_at_idx30430
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule183_id1149_at_idx19657
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[INT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
-    %1:_(<4 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule325_id773_at_idx30430
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDsv4i32_:%[0-9]+]]:qpr = VHADDsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule188_id336_at_idx20127
+name:            test_rule326_id774_at_idx30496
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule188_id336_at_idx20127
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16
-    %0:gprb(s32) = G_BSWAP %3
-    %1:gprb(s32) = G_ASHR %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule326_id774_at_idx30496
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv8i8_:%[0-9]+]]:dpr = VHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule189_id542_at_idx20205
+name:            test_rule327_id775_at_idx30562
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule189_id542_at_idx20205
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
-    %3:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 16
-    %0:gprb(s32) = G_BSWAP %3
-    %1:gprb(s32) = G_ASHR %0, %2
-    $noreg = PATCHABLE_RET %1(s32)
+    ; SELECTED-LABEL: name: test_rule327_id775_at_idx30562
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDsv16i8_:%[0-9]+]]:qpr = VHADDsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule192_id1132_at_idx20469
+name:            test_rule328_id776_at_idx30628
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule192_id1132_at_idx20469
+    ; SELECTED-LABEL: name: test_rule328_id776_at_idx30628
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv4i16_:%[0-9]+]]:dpr = VHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule193_id1133_at_idx20555
+name:            test_rule329_id777_at_idx30694
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule193_id1133_at_idx20555
+    ; SELECTED-LABEL: name: test_rule329_id777_at_idx30694
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv2i32_:%[0-9]+]]:dpr = VHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule194_id1134_at_idx20641
+name:            test_rule330_id778_at_idx30760
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule194_id1134_at_idx20641
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule330_id778_at_idx30760
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDuv8i16_:%[0-9]+]]:qpr = VHADDuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule195_id1135_at_idx20727
+name:            test_rule331_id779_at_idx30826
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule195_id1135_at_idx20727
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
-    %3:fprb(<8 x s8>) = COPY $d17
-    %2:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule331_id779_at_idx30826
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDuv4i32_:%[0-9]+]]:qpr = VHADDuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule196_id1136_at_idx20813
+name:            test_rule332_id780_at_idx30892
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule196_id1136_at_idx20813
+    ; SELECTED-LABEL: name: test_rule332_id780_at_idx30892
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
-    %3:fprb(<4 x s16>) = COPY $d17
-    %2:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv8i8_:%[0-9]+]]:dpr = VHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule197_id1137_at_idx20899
+name:            test_rule333_id781_at_idx30958
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%2' }
-  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule197_id1137_at_idx20899
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
-    %3:fprb(<2 x s32>) = COPY $d17
-    %2:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule333_id781_at_idx30958
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHADDuv16i8_:%[0-9]+]]:qpr = VHADDuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule198_id2094_at_idx20985
+name:            test_rule334_id782_at_idx31024
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -7753,35 +15606,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
-  - { reg: '$d18', virtual-reg: '%5' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule198_id2094_at_idx20985
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAD]]
-    %5:fprb(s64) = COPY $d18
-    %4:fprb(s64) = COPY $d17
-    %3:fprb(s64) = COPY $d16
-    %1:fprb(s64) = G_FNEG %5
-    %0:fprb(s64) = G_FNEG %4
-    %2:fprb(s64) = G_FMA %0, %3, %1
-    $noreg = PATCHABLE_RET %2(s64)
+    ; SELECTED-LABEL: name: test_rule334_id782_at_idx31024
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv4i16_:%[0-9]+]]:dpr = VRHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule199_id2095_at_idx21099
+name:            test_rule335_id783_at_idx31090
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -7790,467 +15635,375 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$s0', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-  - { reg: '$s4', virtual-reg: '%5' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $s0, $s2, $s4
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule199_id2095_at_idx21099
-    ; SELECTED: liveins: $s0, $s2, $s4
-    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
-    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
-    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
-    ; SELECTED: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAS]]
-    %5:fprb(s32) = COPY $s4
-    %4:fprb(s32) = COPY $s2
-    %3:fprb(s32) = COPY $s0
-    %1:fprb(s32) = G_FNEG %5
-    %0:fprb(s32) = G_FNEG %4
-    %2:fprb(s32) = G_FMA %0, %3, %1
-    $noreg = PATCHABLE_RET %2(s32)
+    ; SELECTED-LABEL: name: test_rule335_id783_at_idx31090
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv2i32_:%[0-9]+]]:dpr = VRHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule200_id758_at_idx21213
+name:            test_rule336_id784_at_idx31156
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule200_id758_at_idx21213
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %4:fprb(<8 x s8>) = COPY $d17
-    %3:fprb(<8 x s8>) = COPY $d16
-    %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
-    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule336_id784_at_idx31156
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDsv8i16_:%[0-9]+]]:qpr = VRHADDsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule201_id759_at_idx21315
+name:            test_rule337_id785_at_idx31222
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule201_id759_at_idx21315
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
-    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule337_id785_at_idx31222
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDsv4i32_:%[0-9]+]]:qpr = VRHADDsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule202_id760_at_idx21417
+name:            test_rule338_id786_at_idx31288
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule202_id760_at_idx21417
+    ; SELECTED-LABEL: name: test_rule338_id786_at_idx31288
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY1]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
-    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv8i8_:%[0-9]+]]:dpr = VRHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule203_id761_at_idx21519
+name:            test_rule339_id787_at_idx31354
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule203_id761_at_idx21519
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %4:fprb(<8 x s8>) = COPY $d17
-    %3:fprb(<8 x s8>) = COPY $d16
-    %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %2:_(<8 x s16>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule339_id787_at_idx31354
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDsv16i8_:%[0-9]+]]:qpr = VRHADDsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule204_id762_at_idx21621
+name:            test_rule340_id788_at_idx31420
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule204_id762_at_idx21621
+    ; SELECTED-LABEL: name: test_rule340_id788_at_idx31420
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %2:_(<4 x s32>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv4i16_:%[0-9]+]]:dpr = VRHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule205_id763_at_idx21723
+name:            test_rule341_id789_at_idx31486
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule205_id763_at_idx21723
+    ; SELECTED-LABEL: name: test_rule341_id789_at_idx31486
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY1]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %2:_(<2 x s64>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv2i32_:%[0-9]+]]:dpr = VRHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule206_id941_at_idx21825
+name:            test_rule342_id790_at_idx31552
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule206_id941_at_idx21825
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
-    %4:fprb(<8 x s8>) = COPY $d17
-    %3:fprb(<8 x s8>) = COPY $d16
-    %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
-    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %2:_(<8 x s16>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule342_id790_at_idx31552
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDuv8i16_:%[0-9]+]]:qpr = VRHADDuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule207_id942_at_idx21927
+name:            test_rule343_id791_at_idx31618
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule207_id942_at_idx21927
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
-    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %2:_(<4 x s32>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule343_id791_at_idx31618
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDuv4i32_:%[0-9]+]]:qpr = VRHADDuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule208_id943_at_idx22029
+name:            test_rule344_id792_at_idx31684
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule208_id943_at_idx22029
+    ; SELECTED-LABEL: name: test_rule344_id792_at_idx31684
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY1]](<2 x s32>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[SEXT1]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
-    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %2:_(<2 x s64>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv8i8_:%[0-9]+]]:dpr = VRHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule209_id944_at_idx22131
+name:            test_rule345_id793_at_idx31750
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule209_id944_at_idx22131
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
-    %4:fprb(<8 x s8>) = COPY $d17
-    %3:fprb(<8 x s8>) = COPY $d16
-    %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %2:_(<8 x s16>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule345_id793_at_idx31750
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRHADDuv16i8_:%[0-9]+]]:qpr = VRHADDuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule210_id945_at_idx22233
+name:            test_rule346_id794_at_idx31816
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule210_id945_at_idx22233
+    ; SELECTED-LABEL: name: test_rule346_id794_at_idx31816
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
-    %4:fprb(<4 x s16>) = COPY $d17
-    %3:fprb(<4 x s16>) = COPY $d16
-    %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %2:_(<4 x s32>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv4i16_:%[0-9]+]]:dpr = VQADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule211_id946_at_idx22335
+name:            test_rule347_id795_at_idx31882
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule211_id946_at_idx22335
+    ; SELECTED-LABEL: name: test_rule347_id795_at_idx31882
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY1]](<2 x s32>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[ZEXT1]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
-    %4:fprb(<2 x s32>) = COPY $d17
-    %3:fprb(<2 x s32>) = COPY $d16
-    %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %2:_(<2 x s64>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv2i32_:%[0-9]+]]:dpr = VQADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule213_id2100_at_idx22498
+name:            test_rule348_id796_at_idx31948
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8259,35 +16012,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
-  - { reg: '$d18', virtual-reg: '%5' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule213_id2100_at_idx22498
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
-    %5:fprb(s64) = COPY $d18
-    %4:fprb(s64) = COPY $d17
-    %3:fprb(s64) = COPY $d16
-    %1:fprb(s64) = G_FNEG %5
-    %0:fprb(s64) = G_FMA %1, %3, %4
-    %2:fprb(s64) = G_FNEG %0
-    $noreg = PATCHABLE_RET %2(s64)
+    ; SELECTED-LABEL: name: test_rule348_id796_at_idx31948
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDsv8i16_:%[0-9]+]]:qpr = VQADDsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule214_id2101_at_idx22612
+name:            test_rule349_id797_at_idx32014
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8296,35 +16041,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$s0', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-  - { reg: '$s4', virtual-reg: '%5' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $s0, $s2, $s4
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule214_id2101_at_idx22612
-    ; SELECTED: liveins: $s0, $s2, $s4
-    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
-    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
-    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
-    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
-    %5:fprb(s32) = COPY $s4
-    %4:fprb(s32) = COPY $s2
-    %3:fprb(s32) = COPY $s0
-    %1:fprb(s32) = G_FNEG %5
-    %0:fprb(s32) = G_FMA %1, %3, %4
-    %2:fprb(s32) = G_FNEG %0
-    $noreg = PATCHABLE_RET %2(s32)
+    ; SELECTED-LABEL: name: test_rule349_id797_at_idx32014
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDsv4i32_:%[0-9]+]]:qpr = VQADDsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule215_id2102_at_idx22726
+name:            test_rule350_id798_at_idx32080
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8333,35 +16070,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%3' }
-  - { reg: '$d17', virtual-reg: '%4' }
-  - { reg: '$d18', virtual-reg: '%5' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule215_id2102_at_idx22726
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
-    %5:fprb(s64) = COPY $d18
-    %4:fprb(s64) = COPY $d17
-    %3:fprb(s64) = COPY $d16
-    %1:fprb(s64) = G_FNEG %5
-    %0:fprb(s64) = G_FMA %3, %1, %4
-    %2:fprb(s64) = G_FNEG %0
-    $noreg = PATCHABLE_RET %2(s64)
+    ; SELECTED-LABEL: name: test_rule350_id798_at_idx32080
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv8i8_:%[0-9]+]]:dpr = VQADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule216_id2103_at_idx22840
+name:            test_rule351_id799_at_idx32146
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8370,101 +16099,85 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
-  - { id: 4, class: fprb }
-  - { id: 5, class: fprb }
 liveins:
-  - { reg: '$s0', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-  - { reg: '$s4', virtual-reg: '%5' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $s0, $s2, $s4
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule216_id2103_at_idx22840
-    ; SELECTED: liveins: $s0, $s2, $s4
-    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
-    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
-    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
-    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
-    %5:fprb(s32) = COPY $s4
-    %4:fprb(s32) = COPY $s2
-    %3:fprb(s32) = COPY $s0
-    %1:fprb(s32) = G_FNEG %5
-    %0:fprb(s32) = G_FMA %3, %1, %4
-    %2:fprb(s32) = G_FNEG %0
-    $noreg = PATCHABLE_RET %2(s32)
+    ; SELECTED-LABEL: name: test_rule351_id799_at_idx32146
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDsv16i8_:%[0-9]+]]:qpr = VQADDsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule217_id148_at_idx22954
+name:            test_rule352_id800_at_idx32212
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
-  - { reg: '$r1', virtual-reg: '%3' }
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0, $r1
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule217_id148_at_idx22954
-    ; SELECTED: liveins: $lr, $r0, $r1
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
-    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
-    %3:gprb(s32) = COPY $r1
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule352_id800_at_idx32212
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv1i64_:%[0-9]+]]:dpr = VQADDsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule218_id473_at_idx23032
+name:            test_rule353_id801_at_idx32278
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
-  - { reg: '$r1', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0, $r1
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule218_id473_at_idx23032
-    ; SELECTED: liveins: $lr, $r0, $r1
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
-    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
-    %3:gprb(s32) = COPY $r1
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule353_id801_at_idx32278
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDsv2i64_:%[0-9]+]]:qpr = VQADDsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule223_id1649_at_idx23422
+name:            test_rule354_id802_at_idx32344
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8473,139 +16186,143 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
   - { reg: '$d17', virtual-reg: '%2' }
-  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule223_id1649_at_idx23422
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VTBX1_:%[0-9]+]]:dpr = VTBX1 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VTBX1_]]
-    %3:fprb(<8 x s8>) = COPY $d18
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule354_id802_at_idx32344
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv4i16_:%[0-9]+]]:dpr = VQADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule224_id1680_at_idx23500
+name:            test_rule355_id803_at_idx32410
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule224_id1680_at_idx23500
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule355_id803_at_idx32410
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv2i32_:%[0-9]+]]:dpr = VQADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule225_id1681_at_idx23572
+name:            test_rule356_id804_at_idx32476
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule225_id1681_at_idx23572
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule356_id804_at_idx32476
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDuv8i16_:%[0-9]+]]:qpr = VQADDuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule226_id1682_at_idx23644
+name:            test_rule357_id805_at_idx32542
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule226_id1682_at_idx23644
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule357_id805_at_idx32542
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDuv4i32_:%[0-9]+]]:qpr = VQADDuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule227_id1683_at_idx23716
+name:            test_rule358_id806_at_idx32608
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule227_id1683_at_idx23716
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule358_id806_at_idx32608
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv8i8_:%[0-9]+]]:dpr = VQADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule244_id2181_at_idx25036
+name:            test_rule359_id807_at_idx32674
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8614,31 +16331,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
-  - { reg: '$d18', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule244_id2181_at_idx25036
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
-    %3:fprb(<8 x s8>) = COPY $d18
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule359_id807_at_idx32674
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDuv16i8_:%[0-9]+]]:qpr = VQADDuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule245_id2182_at_idx25114
+name:            test_rule360_id808_at_idx32740
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8647,31 +16360,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
   - { reg: '$d17', virtual-reg: '%2' }
-  - { reg: '$d18', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule245_id2182_at_idx25114
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
-    %3:fprb(<4 x s16>) = COPY $d18
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule360_id808_at_idx32740
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv1i64_:%[0-9]+]]:dpr = VQADDuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule246_id2183_at_idx25192
+name:            test_rule361_id809_at_idx32806
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8680,31 +16389,27 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
-  - { reg: '$d18', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $d16, $d17, $d18
-
-    ; SELECTED-LABEL: name: test_rule246_id2183_at_idx25192
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
-    %3:fprb(<2 x s32>) = COPY $d18
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule361_id809_at_idx32806
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQADDuv2i64_:%[0-9]+]]:qpr = VQADDuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule248_id2185_at_idx25348
+name:            test_rule362_id810_at_idx32872
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8713,139 +16418,143 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
-  - { id: 3, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
-  - { reg: '$d18', virtual-reg: '%3' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17, $d18
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule248_id2185_at_idx25348
-    ; SELECTED: liveins: $d16, $d17, $d18
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
-    %3:fprb(s64) = COPY $d18
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED-LABEL: name: test_rule362_id810_at_idx32872
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRADDHNv8i8_:%[0-9]+]]:dpr = VRADDHNv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRADDHNv8i8_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule249_id2188_at_idx25426
+name:            test_rule363_id811_at_idx32938
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule249_id2188_at_idx25426
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule363_id811_at_idx32938
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRADDHNv4i16_:%[0-9]+]]:dpr = VRADDHNv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRADDHNv4i16_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule250_id2189_at_idx25504
+name:            test_rule364_id812_at_idx33004
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule250_id2189_at_idx25504
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule364_id812_at_idx33004
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRADDHNv2i32_:%[0-9]+]]:dpr = VRADDHNv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRADDHNv2i32_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule251_id2190_at_idx25582
+name:            test_rule365_id819_at_idx33070
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule251_id2190_at_idx25582
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule365_id819_at_idx33070
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULpd:%[0-9]+]]:dpr = VMULpd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULpd]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule253_id2192_at_idx25738
+name:            test_rule366_id820_at_idx33136
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule253_id2192_at_idx25738
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>), [[DEF2]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %3:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule366_id820_at_idx33136
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULpq:%[0-9]+]]:qpr = VMULpq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULpq]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule322_id770_at_idx30232
+name:            test_rule367_id833_at_idx33202
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8861,20 +16570,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule322_id770_at_idx30232
+    ; SELECTED-LABEL: name: test_rule367_id833_at_idx33202
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDsv4i16_:%[0-9]+]]:dpr = VHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv4i16_]]
+    ; SELECTED: [[VQDMULHv4i16_:%[0-9]+]]:dpr = VQDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule323_id771_at_idx30298
+name:            test_rule368_id834_at_idx33268
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8890,68 +16599,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule323_id771_at_idx30298
+    ; SELECTED-LABEL: name: test_rule368_id834_at_idx33268
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDsv2i32_:%[0-9]+]]:dpr = VHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv2i32_]]
+    ; SELECTED: [[VQDMULHv2i32_:%[0-9]+]]:dpr = VQDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule324_id772_at_idx30364
+name:            test_rule369_id835_at_idx33334
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule324_id772_at_idx30364
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule369_id835_at_idx33334
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMULHv8i16_:%[0-9]+]]:qpr = VQDMULHv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule325_id773_at_idx30430
+name:            test_rule370_id836_at_idx33400
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule325_id773_at_idx30430
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule370_id836_at_idx33400
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQDMULHv4i32_:%[0-9]+]]:qpr = VQDMULHv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule326_id774_at_idx30496
+name:            test_rule371_id841_at_idx33466
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -8967,44 +16686,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule326_id774_at_idx30496
+    ; SELECTED-LABEL: name: test_rule371_id841_at_idx33466
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDsv8i8_:%[0-9]+]]:dpr = VHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VQRDMULHv4i16_:%[0-9]+]]:dpr = VQRDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule327_id775_at_idx30562
+name:            test_rule372_id842_at_idx33532
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule327_id775_at_idx30562
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule372_id842_at_idx33532
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMULHv2i32_:%[0-9]+]]:dpr = VQRDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule328_id776_at_idx30628
+name:            test_rule373_id843_at_idx33598
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9014,26 +16738,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule328_id776_at_idx30628
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDuv4i16_:%[0-9]+]]:dpr = VHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule373_id843_at_idx33598
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMULHv8i16_:%[0-9]+]]:qpr = VQRDMULHv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule329_id777_at_idx30694
+name:            test_rule374_id844_at_idx33664
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9043,74 +16767,84 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule329_id777_at_idx30694
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDuv2i32_:%[0-9]+]]:dpr = VHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule374_id844_at_idx33664
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRDMULHv4i32_:%[0-9]+]]:qpr = VQRDMULHv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule330_id778_at_idx30760
+name:            test_rule375_id855_at_idx33730
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule330_id778_at_idx30760
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule375_id855_at_idx33730
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULLp8_:%[0-9]+]]:qpr = VMULLp8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULLp8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule331_id779_at_idx30826
+name:            test_rule376_id856_at_idx33796
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule331_id779_at_idx30826
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule376_id856_at_idx33796
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULLp64_:%[0-9]+]]:qpr = VMULLp64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULLp64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule332_id780_at_idx30892
+name:            test_rule377_id861_at_idx33856
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9126,44 +16860,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule332_id780_at_idx30892
+    ; SELECTED-LABEL: name: test_rule377_id861_at_idx33856
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHADDuv8i8_:%[0-9]+]]:dpr = VHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VQDMULLv4i32_:%[0-9]+]]:qpr = VQDMULLv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULLv4i32_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule333_id781_at_idx30958
+name:            test_rule378_id862_at_idx33922
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule333_id781_at_idx30958
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule378_id862_at_idx33922
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQDMULLv2i64_:%[0-9]+]]:qpr = VQDMULLv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULLv2i64_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule334_id782_at_idx31024
+name:            test_rule379_id953_at_idx33988
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9179,20 +16918,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule334_id782_at_idx31024
+    ; SELECTED-LABEL: name: test_rule379_id953_at_idx33988
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDsv4i16_:%[0-9]+]]:dpr = VRHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv4i16_]]
+    ; SELECTED: [[VHSUBsv4i16_:%[0-9]+]]:dpr = VHSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule335_id783_at_idx31090
+name:            test_rule380_id954_at_idx34054
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9208,68 +16947,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule335_id783_at_idx31090
+    ; SELECTED-LABEL: name: test_rule380_id954_at_idx34054
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDsv2i32_:%[0-9]+]]:dpr = VRHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv2i32_]]
+    ; SELECTED: [[VHSUBsv2i32_:%[0-9]+]]:dpr = VHSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule336_id784_at_idx31156
+name:            test_rule381_id955_at_idx34120
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule336_id784_at_idx31156
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule381_id955_at_idx34120
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBsv8i16_:%[0-9]+]]:qpr = VHSUBsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule337_id785_at_idx31222
+name:            test_rule382_id956_at_idx34186
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule337_id785_at_idx31222
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule382_id956_at_idx34186
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBsv4i32_:%[0-9]+]]:qpr = VHSUBsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule338_id786_at_idx31288
+name:            test_rule383_id957_at_idx34252
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9285,44 +17034,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule338_id786_at_idx31288
+    ; SELECTED-LABEL: name: test_rule383_id957_at_idx34252
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDsv8i8_:%[0-9]+]]:dpr = VRHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv8i8_]]
+    ; SELECTED: [[VHSUBsv8i8_:%[0-9]+]]:dpr = VHSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule339_id787_at_idx31354
+name:            test_rule384_id958_at_idx34318
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule339_id787_at_idx31354
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule384_id958_at_idx34318
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBsv16i8_:%[0-9]+]]:qpr = VHSUBsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule340_id788_at_idx31420
+name:            test_rule385_id959_at_idx34384
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9338,20 +17092,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule340_id788_at_idx31420
+    ; SELECTED-LABEL: name: test_rule385_id959_at_idx34384
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDuv4i16_:%[0-9]+]]:dpr = VRHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv4i16_]]
+    ; SELECTED: [[VHSUBuv4i16_:%[0-9]+]]:dpr = VHSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule341_id789_at_idx31486
+name:            test_rule386_id960_at_idx34450
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9367,68 +17121,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule341_id789_at_idx31486
+    ; SELECTED-LABEL: name: test_rule386_id960_at_idx34450
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDuv2i32_:%[0-9]+]]:dpr = VRHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv2i32_]]
+    ; SELECTED: [[VHSUBuv2i32_:%[0-9]+]]:dpr = VHSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule342_id790_at_idx31552
+name:            test_rule387_id961_at_idx34516
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule342_id790_at_idx31552
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule387_id961_at_idx34516
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBuv8i16_:%[0-9]+]]:qpr = VHSUBuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule343_id791_at_idx31618
+name:            test_rule388_id962_at_idx34582
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule343_id791_at_idx31618
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule388_id962_at_idx34582
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBuv4i32_:%[0-9]+]]:qpr = VHSUBuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule344_id792_at_idx31684
+name:            test_rule389_id963_at_idx34648
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9444,44 +17208,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule344_id792_at_idx31684
+    ; SELECTED-LABEL: name: test_rule389_id963_at_idx34648
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRHADDuv8i8_:%[0-9]+]]:dpr = VRHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv8i8_]]
+    ; SELECTED: [[VHSUBuv8i8_:%[0-9]+]]:dpr = VHSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule345_id793_at_idx31750
+name:            test_rule390_id964_at_idx34714
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule345_id793_at_idx31750
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule390_id964_at_idx34714
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VHSUBuv16i8_:%[0-9]+]]:qpr = VHSUBuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule346_id794_at_idx31816
+name:            test_rule391_id965_at_idx34780
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9497,20 +17266,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule346_id794_at_idx31816
+    ; SELECTED-LABEL: name: test_rule391_id965_at_idx34780
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDsv4i16_:%[0-9]+]]:dpr = VQADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv4i16_]]
+    ; SELECTED: [[VQSUBsv4i16_:%[0-9]+]]:dpr = VQSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule347_id795_at_idx31882
+name:            test_rule392_id966_at_idx34846
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9526,68 +17295,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule347_id795_at_idx31882
+    ; SELECTED-LABEL: name: test_rule392_id966_at_idx34846
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDsv2i32_:%[0-9]+]]:dpr = VQADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv2i32_]]
+    ; SELECTED: [[VQSUBsv2i32_:%[0-9]+]]:dpr = VQSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule348_id796_at_idx31948
+name:            test_rule393_id967_at_idx34912
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule348_id796_at_idx31948
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule393_id967_at_idx34912
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBsv8i16_:%[0-9]+]]:qpr = VQSUBsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule349_id797_at_idx32014
+name:            test_rule394_id968_at_idx34978
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule349_id797_at_idx32014
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule394_id968_at_idx34978
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBsv4i32_:%[0-9]+]]:qpr = VQSUBsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule350_id798_at_idx32080
+name:            test_rule395_id969_at_idx35044
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9603,44 +17382,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule350_id798_at_idx32080
+    ; SELECTED-LABEL: name: test_rule395_id969_at_idx35044
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDsv8i8_:%[0-9]+]]:dpr = VQADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv8i8_]]
+    ; SELECTED: [[VQSUBsv8i8_:%[0-9]+]]:dpr = VQSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule351_id799_at_idx32146
+name:            test_rule396_id970_at_idx35110
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule351_id799_at_idx32146
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule396_id970_at_idx35110
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBsv16i8_:%[0-9]+]]:qpr = VQSUBsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule352_id800_at_idx32212
+name:            test_rule397_id971_at_idx35176
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9656,44 +17440,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule352_id800_at_idx32212
+    ; SELECTED-LABEL: name: test_rule397_id971_at_idx35176
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDsv1i64_:%[0-9]+]]:dpr = VQADDsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv1i64_]]
+    ; SELECTED: [[VQSUBsv1i64_:%[0-9]+]]:dpr = VQSUBsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule353_id801_at_idx32278
+name:            test_rule398_id972_at_idx35242
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule353_id801_at_idx32278
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule398_id972_at_idx35242
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBsv2i64_:%[0-9]+]]:qpr = VQSUBsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule354_id802_at_idx32344
+name:            test_rule399_id973_at_idx35308
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9709,20 +17498,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule354_id802_at_idx32344
+    ; SELECTED-LABEL: name: test_rule399_id973_at_idx35308
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDuv4i16_:%[0-9]+]]:dpr = VQADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv4i16_]]
+    ; SELECTED: [[VQSUBuv4i16_:%[0-9]+]]:dpr = VQSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule355_id803_at_idx32410
+name:            test_rule400_id974_at_idx35374
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9738,68 +17527,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule355_id803_at_idx32410
+    ; SELECTED-LABEL: name: test_rule400_id974_at_idx35374
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDuv2i32_:%[0-9]+]]:dpr = VQADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv2i32_]]
+    ; SELECTED: [[VQSUBuv2i32_:%[0-9]+]]:dpr = VQSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule356_id804_at_idx32476
+name:            test_rule401_id975_at_idx35440
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule356_id804_at_idx32476
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule401_id975_at_idx35440
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBuv8i16_:%[0-9]+]]:qpr = VQSUBuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule357_id805_at_idx32542
+name:            test_rule402_id976_at_idx35506
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule357_id805_at_idx32542
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule402_id976_at_idx35506
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBuv4i32_:%[0-9]+]]:qpr = VQSUBuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule358_id806_at_idx32608
+name:            test_rule403_id977_at_idx35572
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9815,44 +17614,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule358_id806_at_idx32608
+    ; SELECTED-LABEL: name: test_rule403_id977_at_idx35572
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDuv8i8_:%[0-9]+]]:dpr = VQADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv8i8_]]
+    ; SELECTED: [[VQSUBuv8i8_:%[0-9]+]]:dpr = VQSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule359_id807_at_idx32674
+name:            test_rule404_id978_at_idx35638
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule359_id807_at_idx32674
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule404_id978_at_idx35638
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBuv16i8_:%[0-9]+]]:qpr = VQSUBuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule360_id808_at_idx32740
+name:            test_rule405_id979_at_idx35704
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9868,116 +17672,136 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule360_id808_at_idx32740
+    ; SELECTED-LABEL: name: test_rule405_id979_at_idx35704
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQADDuv1i64_:%[0-9]+]]:dpr = VQADDuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv1i64_]]
+    ; SELECTED: [[VQSUBuv1i64_:%[0-9]+]]:dpr = VQSUBuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule361_id809_at_idx32806
+name:            test_rule406_id980_at_idx35770
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule361_id809_at_idx32806
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule406_id980_at_idx35770
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSUBuv2i64_:%[0-9]+]]:qpr = VQSUBuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule362_id810_at_idx32872
+name:            test_rule407_id981_at_idx35836
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule362_id810_at_idx32872
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule407_id981_at_idx35836
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSUBHNv8i8_:%[0-9]+]]:dpr = VRSUBHNv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSUBHNv8i8_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule363_id811_at_idx32938
+name:            test_rule408_id982_at_idx35902
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule363_id811_at_idx32938
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule408_id982_at_idx35902
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSUBHNv4i16_:%[0-9]+]]:dpr = VRSUBHNv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSUBHNv4i16_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule364_id812_at_idx33004
+name:            test_rule409_id983_at_idx35968
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule364_id812_at_idx33004
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule409_id983_at_idx35968
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSUBHNv2i32_:%[0-9]+]]:dpr = VRSUBHNv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSUBHNv2i32_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule365_id819_at_idx33070
+name:            test_rule410_id1076_at_idx36034
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -9993,44 +17817,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule365_id819_at_idx33070
+    ; SELECTED-LABEL: name: test_rule410_id1076_at_idx36034
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VMULpd:%[0-9]+]]:dpr = VMULpd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VMULpd]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VACGEfd:%[0-9]+]]:dpr = VACGEfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule366_id820_at_idx33136
+name:            test_rule411_id1077_at_idx36100
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule366_id820_at_idx33136
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule411_id1077_at_idx36100
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VACGEfq:%[0-9]+]]:qpr = VACGEfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule367_id833_at_idx33202
+name:            test_rule412_id1078_at_idx36166
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10046,20 +17875,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule367_id833_at_idx33202
+    ; SELECTED-LABEL: name: test_rule412_id1078_at_idx36166
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQDMULHv4i16_:%[0-9]+]]:dpr = VQDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv4i16_]]
+    ; SELECTED: [[VACGEhd:%[0-9]+]]:dpr = VACGEhd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEhd]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule368_id834_at_idx33268
+name:            test_rule413_id1079_at_idx36232
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10069,74 +17898,84 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule368_id834_at_idx33268
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQDMULHv2i32_:%[0-9]+]]:dpr = VQDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule413_id1079_at_idx36232
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VACGEhq:%[0-9]+]]:qpr = VACGEhq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEhq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule369_id835_at_idx33334
+name:            test_rule414_id1080_at_idx36298
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule369_id835_at_idx33334
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule414_id1080_at_idx36298
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VACGTfd:%[0-9]+]]:dpr = VACGTfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGTfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule370_id836_at_idx33400
+name:            test_rule415_id1081_at_idx36364
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule370_id836_at_idx33400
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule415_id1081_at_idx36364
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VACGTfq:%[0-9]+]]:qpr = VACGTfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGTfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule371_id841_at_idx33466
+name:            test_rule416_id1082_at_idx36430
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10152,20 +17991,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule371_id841_at_idx33466
+    ; SELECTED-LABEL: name: test_rule416_id1082_at_idx36430
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMULHv4i16_:%[0-9]+]]:dpr = VQRDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv4i16_]]
+    ; SELECTED: [[VACGThd:%[0-9]+]]:dpr = VACGThd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGThd]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule372_id842_at_idx33532
+name:            test_rule417_id1083_at_idx36496
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10175,141 +18014,148 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule372_id842_at_idx33532
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRDMULHv2i32_:%[0-9]+]]:dpr = VQRDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule417_id1083_at_idx36496
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VACGThq:%[0-9]+]]:qpr = VACGThq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGThq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule373_id843_at_idx33598
+name:            test_rule418_id1116_at_idx36562
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule373_id843_at_idx33598
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule418_id1116_at_idx36562
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule374_id844_at_idx33664
+name:            test_rule419_id1117_at_idx36628
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule374_id844_at_idx33664
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule419_id1117_at_idx36628
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule375_id855_at_idx33730
+name:            test_rule420_id1118_at_idx36694
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule375_id855_at_idx33730
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule420_id1118_at_idx36694
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDsv8i16_:%[0-9]+]]:qpr = VABDsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule376_id856_at_idx33796
+name:            test_rule421_id1119_at_idx36760
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule376_id856_at_idx33796
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), [[COPY1]](s64), [[COPY]](s64)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule421_id1119_at_idx36760
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDsv4i32_:%[0-9]+]]:qpr = VABDsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule377_id861_at_idx33856
+name:            test_rule422_id1120_at_idx36826
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
@@ -10319,50 +18165,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule377_id861_at_idx33856
+    ; SELECTED-LABEL: name: test_rule422_id1120_at_idx36826
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv8i8_:%[0-9]+]]:dpr = VABDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule378_id862_at_idx33922
+name:            test_rule423_id1121_at_idx36892
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule378_id862_at_idx33922
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule423_id1121_at_idx36892
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDsv16i8_:%[0-9]+]]:qpr = VABDsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule379_id953_at_idx33988
+name:            test_rule424_id1122_at_idx36958
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10378,20 +18223,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule379_id953_at_idx33988
+    ; SELECTED-LABEL: name: test_rule424_id1122_at_idx36958
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBsv4i16_:%[0-9]+]]:dpr = VHSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv4i16_]]
+    ; SELECTED: [[VABDuv4i16_:%[0-9]+]]:dpr = VABDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule380_id954_at_idx34054
+name:            test_rule425_id1123_at_idx37024
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10407,68 +18252,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule380_id954_at_idx34054
+    ; SELECTED-LABEL: name: test_rule425_id1123_at_idx37024
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBsv2i32_:%[0-9]+]]:dpr = VHSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv2i32_]]
+    ; SELECTED: [[VABDuv2i32_:%[0-9]+]]:dpr = VABDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule381_id955_at_idx34120
+name:            test_rule426_id1124_at_idx37090
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule381_id955_at_idx34120
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule426_id1124_at_idx37090
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDuv8i16_:%[0-9]+]]:qpr = VABDuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule382_id956_at_idx34186
+name:            test_rule427_id1125_at_idx37156
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule382_id956_at_idx34186
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule427_id1125_at_idx37156
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDuv4i32_:%[0-9]+]]:qpr = VABDuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule383_id957_at_idx34252
+name:            test_rule428_id1126_at_idx37222
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10484,44 +18339,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule383_id957_at_idx34252
+    ; SELECTED-LABEL: name: test_rule428_id1126_at_idx37222
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBsv8i8_:%[0-9]+]]:dpr = VHSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv8i8_]]
+    ; SELECTED: [[VABDuv8i8_:%[0-9]+]]:dpr = VABDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule384_id958_at_idx34318
+name:            test_rule429_id1127_at_idx37288
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule384_id958_at_idx34318
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule429_id1127_at_idx37288
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDuv16i8_:%[0-9]+]]:qpr = VABDuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule385_id959_at_idx34384
+name:            test_rule430_id1128_at_idx37354
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10537,20 +18397,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule385_id959_at_idx34384
+    ; SELECTED-LABEL: name: test_rule430_id1128_at_idx37354
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBuv4i16_:%[0-9]+]]:dpr = VHSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule386_id960_at_idx34450
+name:            test_rule431_id1129_at_idx37420
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10560,74 +18420,84 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule386_id960_at_idx34450
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBuv2i32_:%[0-9]+]]:dpr = VHSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule431_id1129_at_idx37420
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDsv4i32_:%[0-9]+]]:qpr = VABDsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule387_id961_at_idx34516
+name:            test_rule432_id1130_at_idx37486
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule387_id961_at_idx34516
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule432_id1130_at_idx37486
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule388_id962_at_idx34582
+name:            test_rule433_id1131_at_idx37552
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule388_id962_at_idx34582
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule433_id1131_at_idx37552
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VABDsv8i16_:%[0-9]+]]:qpr = VABDsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule389_id963_at_idx34648
+name:            test_rule434_id1196_at_idx37618
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10643,44 +18513,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule389_id963_at_idx34648
+    ; SELECTED-LABEL: name: test_rule434_id1196_at_idx37618
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VHSUBuv8i8_:%[0-9]+]]:dpr = VHSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv8i8_]]
+    ; SELECTED: [[VPADDi8_:%[0-9]+]]:dpr = VPADDi8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule390_id964_at_idx34714
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule390_id964_at_idx34714
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule391_id965_at_idx34780
+name:            test_rule435_id1197_at_idx37684
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10696,20 +18542,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule391_id965_at_idx34780
+    ; SELECTED-LABEL: name: test_rule435_id1197_at_idx37684
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBsv4i16_:%[0-9]+]]:dpr = VQSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv4i16_]]
+    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule392_id966_at_idx34846
+name:            test_rule436_id1198_at_idx37750
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10725,68 +18571,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule392_id966_at_idx34846
+    ; SELECTED-LABEL: name: test_rule436_id1198_at_idx37750
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBsv2i32_:%[0-9]+]]:dpr = VQSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv2i32_]]
+    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule393_id967_at_idx34912
+name:            test_rule437_id1199_at_idx37816
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule393_id967_at_idx34912
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
 
-...
----
-name:            test_rule394_id968_at_idx34978
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule394_id968_at_idx34978
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule437_id1199_at_idx37816
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule395_id969_at_idx35044
+name:            test_rule438_id1200_at_idx37882
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10802,44 +18629,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule395_id969_at_idx35044
+    ; SELECTED-LABEL: name: test_rule438_id1200_at_idx37882
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBsv8i8_:%[0-9]+]]:dpr = VQSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule396_id970_at_idx35110
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule396_id970_at_idx35110
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule397_id971_at_idx35176
+name:            test_rule439_id1213_at_idx37948
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10855,44 +18658,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule397_id971_at_idx35176
+    ; SELECTED-LABEL: name: test_rule439_id1213_at_idx37948
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBsv1i64_:%[0-9]+]]:dpr = VQSUBsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
-
-...
----
-name:            test_rule398_id972_at_idx35242
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule398_id972_at_idx35242
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    ; SELECTED: [[VPADALsv8i8_:%[0-9]+]]:dpr = VPADALsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule399_id973_at_idx35308
+name:            test_rule440_id1214_at_idx38014
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10908,20 +18687,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule399_id973_at_idx35308
+    ; SELECTED-LABEL: name: test_rule440_id1214_at_idx38014
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBuv4i16_:%[0-9]+]]:dpr = VQSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv4i16_]]
+    ; SELECTED: [[VPADALsv4i16_:%[0-9]+]]:dpr = VPADALsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule400_id974_at_idx35374
+name:            test_rule441_id1215_at_idx38080
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -10937,68 +18716,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule400_id974_at_idx35374
+    ; SELECTED-LABEL: name: test_rule441_id1215_at_idx38080
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBuv2i32_:%[0-9]+]]:dpr = VQSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv2i32_]]
+    ; SELECTED: [[VPADALsv2i32_:%[0-9]+]]:dpr = VPADALsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule401_id975_at_idx35440
+name:            test_rule442_id1216_at_idx38146
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule401_id975_at_idx35440
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule442_id1216_at_idx38146
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALsv16i8_:%[0-9]+]]:qpr = VPADALsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule402_id976_at_idx35506
+name:            test_rule443_id1217_at_idx38212
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule402_id976_at_idx35506
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule443_id1217_at_idx38212
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALsv8i16_:%[0-9]+]]:qpr = VPADALsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule403_id977_at_idx35572
+name:            test_rule444_id1218_at_idx38278
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11008,50 +18797,55 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule403_id977_at_idx35572
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBuv8i8_:%[0-9]+]]:dpr = VQSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule444_id1218_at_idx38278
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALsv4i32_:%[0-9]+]]:qpr = VPADALsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule404_id978_at_idx35638
+name:            test_rule445_id1219_at_idx38344
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule404_id978_at_idx35638
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule445_id1219_at_idx38344
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALuv8i8_:%[0-9]+]]:dpr = VPADALuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule405_id979_at_idx35704
+name:            test_rule446_id1220_at_idx38410
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11067,116 +18861,136 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule405_id979_at_idx35704
+    ; SELECTED-LABEL: name: test_rule446_id1220_at_idx38410
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSUBuv1i64_:%[0-9]+]]:dpr = VQSUBuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED: [[VPADALuv4i16_:%[0-9]+]]:dpr = VPADALuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule406_id980_at_idx35770
+name:            test_rule447_id1221_at_idx38476
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule406_id980_at_idx35770
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule447_id1221_at_idx38476
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALuv2i32_:%[0-9]+]]:dpr = VPADALuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule407_id981_at_idx35836
+name:            test_rule448_id1222_at_idx38542
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule407_id981_at_idx35836
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule448_id1222_at_idx38542
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALuv16i8_:%[0-9]+]]:qpr = VPADALuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule408_id982_at_idx35902
+name:            test_rule449_id1223_at_idx38608
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule408_id982_at_idx35902
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule449_id1223_at_idx38608
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALuv8i16_:%[0-9]+]]:qpr = VPADALuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule409_id983_at_idx35968
+name:            test_rule450_id1224_at_idx38674
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule409_id983_at_idx35968
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule450_id1224_at_idx38674
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADALuv4i32_:%[0-9]+]]:qpr = VPADALuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule410_id1076_at_idx36034
+name:            test_rule451_id1225_at_idx38740
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11192,44 +19006,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule410_id1076_at_idx36034
+    ; SELECTED-LABEL: name: test_rule451_id1225_at_idx38740
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VACGEfd:%[0-9]+]]:dpr = VACGEfd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEfd]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule411_id1077_at_idx36100
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule411_id1077_at_idx36100
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED: [[VPMAXs8_:%[0-9]+]]:dpr = VPMAXs8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule412_id1078_at_idx36166
+name:            test_rule452_id1226_at_idx38806
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11245,44 +19035,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule412_id1078_at_idx36166
+    ; SELECTED-LABEL: name: test_rule452_id1226_at_idx38806
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VACGEhd:%[0-9]+]]:dpr = VACGEhd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEhd]]
+    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule413_id1079_at_idx36232
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule413_id1079_at_idx36232
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule414_id1080_at_idx36298
+name:            test_rule453_id1227_at_idx38872
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11298,44 +19064,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule414_id1080_at_idx36298
+    ; SELECTED-LABEL: name: test_rule453_id1227_at_idx38872
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VACGTfd:%[0-9]+]]:dpr = VACGTfd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VACGTfd]]
+    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule415_id1081_at_idx36364
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule415_id1081_at_idx36364
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule416_id1082_at_idx36430
+name:            test_rule454_id1228_at_idx38938
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11351,44 +19093,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule416_id1082_at_idx36430
+    ; SELECTED-LABEL: name: test_rule454_id1228_at_idx38938
     ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VACGThd:%[0-9]+]]:dpr = VACGThd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VACGThd]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule417_id1083_at_idx36496
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule417_id1083_at_idx36496
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXu8_:%[0-9]+]]:dpr = VPMAXu8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule418_id1116_at_idx36562
+name:            test_rule455_id1229_at_idx39004
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11404,20 +19122,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule418_id1116_at_idx36562
+    ; SELECTED-LABEL: name: test_rule455_id1229_at_idx39004
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    ; SELECTED: [[VPMAXu16_:%[0-9]+]]:dpr = VPMAXu16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule419_id1117_at_idx36628
+name:            test_rule456_id1230_at_idx39070
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11433,68 +19151,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule419_id1117_at_idx36628
+    ; SELECTED-LABEL: name: test_rule456_id1230_at_idx39070
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    ; SELECTED: [[VPMAXu32_:%[0-9]+]]:dpr = VPMAXu32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule420_id1118_at_idx36694
+name:            test_rule457_id1231_at_idx39136
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule420_id1118_at_idx36694
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule457_id1231_at_idx39136
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule421_id1119_at_idx36760
+name:            test_rule458_id1232_at_idx39202
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule421_id1119_at_idx36760
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule458_id1232_at_idx39202
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule422_id1120_at_idx36826
+name:            test_rule459_id1233_at_idx39268
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11510,44 +19238,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule422_id1120_at_idx36826
+    ; SELECTED-LABEL: name: test_rule459_id1233_at_idx39268
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDsv8i8_:%[0-9]+]]:dpr = VABDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv8i8_]]
+    ; SELECTED: [[VPMINs8_:%[0-9]+]]:dpr = VPMINs8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule423_id1121_at_idx36892
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule423_id1121_at_idx36892
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule424_id1122_at_idx36958
+name:            test_rule460_id1234_at_idx39334
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11563,20 +19267,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule424_id1122_at_idx36958
+    ; SELECTED-LABEL: name: test_rule460_id1234_at_idx39334
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDuv4i16_:%[0-9]+]]:dpr = VABDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv4i16_]]
+    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule425_id1123_at_idx37024
+name:            test_rule461_id1235_at_idx39400
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11592,68 +19296,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule425_id1123_at_idx37024
+    ; SELECTED-LABEL: name: test_rule461_id1235_at_idx39400
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDuv2i32_:%[0-9]+]]:dpr = VABDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv2i32_]]
+    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule426_id1124_at_idx37090
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule426_id1124_at_idx37090
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule427_id1125_at_idx37156
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule427_id1125_at_idx37156
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule428_id1126_at_idx37222
+name:            test_rule462_id1236_at_idx39466
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11669,44 +19325,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule428_id1126_at_idx37222
+    ; SELECTED-LABEL: name: test_rule462_id1236_at_idx39466
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDuv8i8_:%[0-9]+]]:dpr = VABDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv8i8_]]
+    ; SELECTED: [[VPMINu8_:%[0-9]+]]:dpr = VPMINu8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule429_id1127_at_idx37288
+name:            test_rule463_id1237_at_idx39532
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule429_id1127_at_idx37288
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule463_id1237_at_idx39532
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINu16_:%[0-9]+]]:dpr = VPMINu16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule430_id1128_at_idx37354
+name:            test_rule464_id1238_at_idx39598
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11722,44 +19383,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule430_id1128_at_idx37354
+    ; SELECTED-LABEL: name: test_rule464_id1238_at_idx39598
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    ; SELECTED: [[VPMINu32_:%[0-9]+]]:dpr = VPMINu32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule431_id1129_at_idx37420
+name:            test_rule465_id1239_at_idx39664
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule431_id1129_at_idx37420
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule465_id1239_at_idx39664
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule432_id1130_at_idx37486
+name:            test_rule466_id1240_at_idx39730
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11775,44 +19441,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule432_id1130_at_idx37486
+    ; SELECTED-LABEL: name: test_rule466_id1240_at_idx39730
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule433_id1131_at_idx37552
+name:            test_rule467_id1247_at_idx39796
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule433_id1131_at_idx37552
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule467_id1247_at_idx39796
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPSfd:%[0-9]+]]:dpr = VRECPSfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPSfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule434_id1196_at_idx37618
+name:            test_rule468_id1248_at_idx39862
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11822,26 +19493,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule434_id1196_at_idx37618
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDi8_:%[0-9]+]]:dpr = VPADDi8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule468_id1248_at_idx39862
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRECPSfq:%[0-9]+]]:qpr = VRECPSfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPSfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule435_id1197_at_idx37684
+name:            test_rule469_id1249_at_idx39928
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11857,20 +19528,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule435_id1197_at_idx37684
+    ; SELECTED-LABEL: name: test_rule469_id1249_at_idx39928
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
+    ; SELECTED: [[VRECPShd:%[0-9]+]]:dpr = VRECPShd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPShd]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule436_id1198_at_idx37750
+name:            test_rule470_id1250_at_idx39994
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11880,26 +19551,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule436_id1198_at_idx37750
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule470_id1250_at_idx39994
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRECPShq:%[0-9]+]]:qpr = VRECPShq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPShq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule437_id1199_at_idx37816
+name:            test_rule471_id1257_at_idx40060
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11915,20 +19586,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule437_id1199_at_idx37816
+    ; SELECTED-LABEL: name: test_rule471_id1257_at_idx40060
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
+    ; SELECTED: [[VRSQRTSfd:%[0-9]+]]:dpr = VRSQRTSfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTSfd]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule438_id1200_at_idx37882
+name:            test_rule472_id1258_at_idx40126
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule472_id1258_at_idx40126
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSQRTSfq:%[0-9]+]]:qpr = VRSQRTSfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTSfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule473_id1259_at_idx40192
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11944,20 +19644,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule438_id1200_at_idx37882
+    ; SELECTED-LABEL: name: test_rule473_id1259_at_idx40192
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
+    ; SELECTED: [[VRSQRTShd:%[0-9]+]]:dpr = VRSQRTShd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTShd]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule439_id1213_at_idx37948
+name:            test_rule474_id1260_at_idx40258
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -11967,26 +19667,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule439_id1213_at_idx37948
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALsv8i8_:%[0-9]+]]:dpr = VPADALsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule474_id1260_at_idx40258
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSQRTShq:%[0-9]+]]:qpr = VRSQRTShq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTShq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule440_id1214_at_idx38014
+name:            test_rule475_id1261_at_idx40324
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12002,20 +19702,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule440_id1214_at_idx38014
+    ; SELECTED-LABEL: name: test_rule475_id1261_at_idx40324
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALsv4i16_:%[0-9]+]]:dpr = VPADALsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv4i16_]]
+    ; SELECTED: [[VSHLsv4i16_:%[0-9]+]]:dpr = VSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule441_id1215_at_idx38080
+name:            test_rule476_id1262_at_idx40390
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12031,92 +19731,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule441_id1215_at_idx38080
+    ; SELECTED-LABEL: name: test_rule476_id1262_at_idx40390
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALsv2i32_:%[0-9]+]]:dpr = VPADALsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv2i32_]]
+    ; SELECTED: [[VSHLsv2i32_:%[0-9]+]]:dpr = VSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(s64)
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule442_id1216_at_idx38146
+name:            test_rule477_id1263_at_idx40456
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule442_id1216_at_idx38146
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<8 x s16>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule477_id1263_at_idx40456
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLsv8i16_:%[0-9]+]]:qpr = VSHLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule443_id1217_at_idx38212
+name:            test_rule478_id1264_at_idx40522
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule443_id1217_at_idx38212
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<4 x s32>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8, $q9
 
-...
----
-name:            test_rule444_id1218_at_idx38278
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule444_id1218_at_idx38278
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<2 x s64>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    ; SELECTED-LABEL: name: test_rule478_id1264_at_idx40522
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLsv4i32_:%[0-9]+]]:qpr = VSHLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule445_id1219_at_idx38344
+name:            test_rule479_id1265_at_idx40588
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12132,20 +19818,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule445_id1219_at_idx38344
+    ; SELECTED-LABEL: name: test_rule479_id1265_at_idx40588
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALuv8i8_:%[0-9]+]]:dpr = VPADALuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv8i8_]]
+    ; SELECTED: [[VSHLsv8i8_:%[0-9]+]]:dpr = VSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule446_id1220_at_idx38410
+name:            test_rule480_id1266_at_idx40654
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12155,26 +19841,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule446_id1220_at_idx38410
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALuv4i16_:%[0-9]+]]:dpr = VPADALuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule480_id1266_at_idx40654
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLsv16i8_:%[0-9]+]]:qpr = VSHLsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule447_id1221_at_idx38476
+name:            test_rule481_id1267_at_idx40720
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12190,92 +19876,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule447_id1221_at_idx38476
+    ; SELECTED-LABEL: name: test_rule481_id1267_at_idx40720
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADALuv2i32_:%[0-9]+]]:dpr = VPADALuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[VSHLsv1i64_:%[0-9]+]]:dpr = VSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule448_id1222_at_idx38542
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule448_id1222_at_idx38542
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<8 x s16>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule449_id1223_at_idx38608
+name:            test_rule482_id1268_at_idx40786
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule449_id1223_at_idx38608
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<4 x s32>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8, $q9
 
-...
----
-name:            test_rule450_id1224_at_idx38674
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule450_id1224_at_idx38674
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<2 x s64>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule482_id1268_at_idx40786
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLsv2i64_:%[0-9]+]]:qpr = VSHLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule451_id1225_at_idx38740
+name:            test_rule483_id1269_at_idx40852
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12291,20 +19934,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule451_id1225_at_idx38740
+    ; SELECTED-LABEL: name: test_rule483_id1269_at_idx40852
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXs8_:%[0-9]+]]:dpr = VPMAXs8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VSHLuv4i16_:%[0-9]+]]:dpr = VSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule452_id1226_at_idx38806
+name:            test_rule484_id1270_at_idx40918
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12320,20 +19963,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule452_id1226_at_idx38806
+    ; SELECTED-LABEL: name: test_rule484_id1270_at_idx40918
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VSHLuv2i32_:%[0-9]+]]:dpr = VSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule485_id1271_at_idx40984
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule485_id1271_at_idx40984
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLuv8i16_:%[0-9]+]]:qpr = VSHLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule453_id1227_at_idx38872
+name:            test_rule486_id1272_at_idx41050
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12343,26 +20015,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule453_id1227_at_idx38872
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule486_id1272_at_idx41050
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLuv4i32_:%[0-9]+]]:qpr = VSHLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule454_id1228_at_idx38938
+name:            test_rule487_id1273_at_idx41116
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12378,20 +20050,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule454_id1228_at_idx38938
+    ; SELECTED-LABEL: name: test_rule487_id1273_at_idx41116
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXu8_:%[0-9]+]]:dpr = VPMAXu8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu8_]]
+    ; SELECTED: [[VSHLuv8i8_:%[0-9]+]]:dpr = VSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule455_id1229_at_idx39004
+name:            test_rule488_id1274_at_idx41182
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12401,26 +20073,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule455_id1229_at_idx39004
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXu16_:%[0-9]+]]:dpr = VPMAXu16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule488_id1274_at_idx41182
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLuv16i8_:%[0-9]+]]:qpr = VSHLuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule456_id1230_at_idx39070
+name:            test_rule489_id1275_at_idx41248
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12436,20 +20108,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule456_id1230_at_idx39070
+    ; SELECTED-LABEL: name: test_rule489_id1275_at_idx41248
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXu32_:%[0-9]+]]:dpr = VPMAXu32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VSHLuv1i64_:%[0-9]+]]:dpr = VSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule457_id1231_at_idx39136
+name:            test_rule490_id1276_at_idx41314
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12459,26 +20131,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule457_id1231_at_idx39136
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule490_id1276_at_idx41314
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSHLuv2i64_:%[0-9]+]]:qpr = VSHLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule458_id1232_at_idx39202
+name:            test_rule491_id1310_at_idx41380
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12494,20 +20166,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule458_id1232_at_idx39202
+    ; SELECTED-LABEL: name: test_rule491_id1310_at_idx41380
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
+    ; SELECTED: [[VRSHLsv4i16_:%[0-9]+]]:dpr = VRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule459_id1233_at_idx39268
+name:            test_rule492_id1311_at_idx41446
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12523,20 +20195,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule459_id1233_at_idx39268
+    ; SELECTED-LABEL: name: test_rule492_id1311_at_idx41446
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINs8_:%[0-9]+]]:dpr = VPMINs8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VRSHLsv2i32_:%[0-9]+]]:dpr = VRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule460_id1234_at_idx39334
+name:            test_rule493_id1312_at_idx41512
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12546,26 +20218,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule460_id1234_at_idx39334
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule493_id1312_at_idx41512
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLsv8i16_:%[0-9]+]]:qpr = VRSHLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule461_id1235_at_idx39400
+name:            test_rule494_id1313_at_idx41578
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12575,26 +20247,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule461_id1235_at_idx39400
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule494_id1313_at_idx41578
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLsv4i32_:%[0-9]+]]:qpr = VRSHLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule462_id1236_at_idx39466
+name:            test_rule495_id1314_at_idx41644
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12610,20 +20282,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule462_id1236_at_idx39466
+    ; SELECTED-LABEL: name: test_rule495_id1314_at_idx41644
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINu8_:%[0-9]+]]:dpr = VPMINu8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu8_]]
+    ; SELECTED: [[VRSHLsv8i8_:%[0-9]+]]:dpr = VRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule463_id1237_at_idx39532
+name:            test_rule496_id1315_at_idx41710
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12633,26 +20305,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule463_id1237_at_idx39532
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINu16_:%[0-9]+]]:dpr = VPMINu16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule496_id1315_at_idx41710
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLsv16i8_:%[0-9]+]]:qpr = VRSHLsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule464_id1238_at_idx39598
+name:            test_rule497_id1316_at_idx41776
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12668,20 +20340,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule464_id1238_at_idx39598
+    ; SELECTED-LABEL: name: test_rule497_id1316_at_idx41776
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINu32_:%[0-9]+]]:dpr = VPMINu32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VRSHLsv1i64_:%[0-9]+]]:dpr = VRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule465_id1239_at_idx39664
+name:            test_rule498_id1317_at_idx41842
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12691,26 +20363,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule465_id1239_at_idx39664
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule498_id1317_at_idx41842
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLsv2i64_:%[0-9]+]]:qpr = VRSHLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule466_id1240_at_idx39730
+name:            test_rule499_id1318_at_idx41908
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12726,20 +20398,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule466_id1240_at_idx39730
+    ; SELECTED-LABEL: name: test_rule499_id1318_at_idx41908
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
+    ; SELECTED: [[VRSHLuv4i16_:%[0-9]+]]:dpr = VRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule467_id1247_at_idx39796
+name:            test_rule500_id1319_at_idx41974
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12755,44 +20427,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule467_id1247_at_idx39796
+    ; SELECTED-LABEL: name: test_rule500_id1319_at_idx41974
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRECPSfd:%[0-9]+]]:dpr = VRECPSfd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPSfd]]
+    ; SELECTED: [[VRSHLuv2i32_:%[0-9]+]]:dpr = VRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule468_id1248_at_idx39862
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule468_id1248_at_idx39862
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule469_id1249_at_idx39928
+name:            test_rule501_id1320_at_idx42040
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12802,50 +20450,55 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule469_id1249_at_idx39928
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRECPShd:%[0-9]+]]:dpr = VRECPShd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPShd]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule501_id1320_at_idx42040
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLuv8i16_:%[0-9]+]]:qpr = VRSHLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule470_id1250_at_idx39994
+name:            test_rule502_id1321_at_idx42106
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule470_id1250_at_idx39994
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule502_id1321_at_idx42106
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLuv4i32_:%[0-9]+]]:qpr = VRSHLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule471_id1257_at_idx40060
+name:            test_rule503_id1322_at_idx42172
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12861,44 +20514,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule471_id1257_at_idx40060
+    ; SELECTED-LABEL: name: test_rule503_id1322_at_idx42172
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSQRTSfd:%[0-9]+]]:dpr = VRSQRTSfd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTSfd]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VRSHLuv8i8_:%[0-9]+]]:dpr = VRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule472_id1258_at_idx40126
+name:            test_rule504_id1323_at_idx42238
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule472_id1258_at_idx40126
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule504_id1323_at_idx42238
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLuv16i8_:%[0-9]+]]:qpr = VRSHLuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule473_id1259_at_idx40192
+name:            test_rule505_id1324_at_idx42304
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12914,44 +20572,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule473_id1259_at_idx40192
+    ; SELECTED-LABEL: name: test_rule505_id1324_at_idx42304
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSQRTShd:%[0-9]+]]:dpr = VRSQRTShd [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTShd]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VRSHLuv1i64_:%[0-9]+]]:dpr = VRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule474_id1260_at_idx40258
+name:            test_rule506_id1325_at_idx42370
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule474_id1260_at_idx40258
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule506_id1325_at_idx42370
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSHLuv2i64_:%[0-9]+]]:qpr = VRSHLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule475_id1261_at_idx40324
+name:            test_rule507_id1345_at_idx42436
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12967,20 +20630,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule475_id1261_at_idx40324
+    ; SELECTED-LABEL: name: test_rule507_id1345_at_idx42436
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLsv4i16_:%[0-9]+]]:dpr = VSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv4i16_]]
+    ; SELECTED: [[VQSHLsv4i16_:%[0-9]+]]:dpr = VQSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule476_id1262_at_idx40390
+name:            test_rule508_id1346_at_idx42502
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -12996,68 +20659,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule476_id1262_at_idx40390
+    ; SELECTED-LABEL: name: test_rule508_id1346_at_idx42502
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLsv2i32_:%[0-9]+]]:dpr = VSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv2i32_]]
+    ; SELECTED: [[VQSHLsv2i32_:%[0-9]+]]:dpr = VQSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule477_id1263_at_idx40456
+name:            test_rule509_id1347_at_idx42568
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule477_id1263_at_idx40456
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule509_id1347_at_idx42568
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLsv8i16_:%[0-9]+]]:qpr = VQSHLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule478_id1264_at_idx40522
+name:            test_rule510_id1348_at_idx42634
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule478_id1264_at_idx40522
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule510_id1348_at_idx42634
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLsv4i32_:%[0-9]+]]:qpr = VQSHLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule479_id1265_at_idx40588
+name:            test_rule511_id1349_at_idx42700
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13073,44 +20746,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule479_id1265_at_idx40588
+    ; SELECTED-LABEL: name: test_rule511_id1349_at_idx42700
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLsv8i8_:%[0-9]+]]:dpr = VSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv8i8_]]
+    ; SELECTED: [[VQSHLsv8i8_:%[0-9]+]]:dpr = VQSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule480_id1266_at_idx40654
+name:            test_rule512_id1350_at_idx42766
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule480_id1266_at_idx40654
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule512_id1350_at_idx42766
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLsv16i8_:%[0-9]+]]:qpr = VQSHLsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule481_id1267_at_idx40720
+name:            test_rule513_id1351_at_idx42832
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13126,44 +20804,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule481_id1267_at_idx40720
+    ; SELECTED-LABEL: name: test_rule513_id1351_at_idx42832
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLsv1i64_:%[0-9]+]]:dpr = VSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv1i64_]]
+    ; SELECTED: [[VQSHLsv1i64_:%[0-9]+]]:dpr = VQSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule482_id1268_at_idx40786
+name:            test_rule514_id1352_at_idx42898
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule482_id1268_at_idx40786
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule514_id1352_at_idx42898
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLsv2i64_:%[0-9]+]]:qpr = VQSHLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule483_id1269_at_idx40852
+name:            test_rule515_id1353_at_idx42964
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13179,20 +20862,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule483_id1269_at_idx40852
+    ; SELECTED-LABEL: name: test_rule515_id1353_at_idx42964
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLuv4i16_:%[0-9]+]]:dpr = VSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv4i16_]]
+    ; SELECTED: [[VQSHLuv4i16_:%[0-9]+]]:dpr = VQSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule484_id1270_at_idx40918
+name:            test_rule516_id1354_at_idx43030
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13208,68 +20891,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule484_id1270_at_idx40918
+    ; SELECTED-LABEL: name: test_rule516_id1354_at_idx43030
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLuv2i32_:%[0-9]+]]:dpr = VSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv2i32_]]
+    ; SELECTED: [[VQSHLuv2i32_:%[0-9]+]]:dpr = VQSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule485_id1271_at_idx40984
+name:            test_rule517_id1355_at_idx43096
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule485_id1271_at_idx40984
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule517_id1355_at_idx43096
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLuv8i16_:%[0-9]+]]:qpr = VQSHLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule486_id1272_at_idx41050
+name:            test_rule518_id1356_at_idx43162
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule486_id1272_at_idx41050
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule518_id1356_at_idx43162
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLuv4i32_:%[0-9]+]]:qpr = VQSHLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule487_id1273_at_idx41116
+name:            test_rule519_id1357_at_idx43228
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13285,44 +20978,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule487_id1273_at_idx41116
+    ; SELECTED-LABEL: name: test_rule519_id1357_at_idx43228
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLuv8i8_:%[0-9]+]]:dpr = VSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv8i8_]]
+    ; SELECTED: [[VQSHLuv8i8_:%[0-9]+]]:dpr = VQSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule488_id1274_at_idx41182
+name:            test_rule520_id1358_at_idx43294
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule488_id1274_at_idx41182
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule520_id1358_at_idx43294
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLuv16i8_:%[0-9]+]]:qpr = VQSHLuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule489_id1275_at_idx41248
+name:            test_rule521_id1359_at_idx43360
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13338,44 +21036,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule489_id1275_at_idx41248
+    ; SELECTED-LABEL: name: test_rule521_id1359_at_idx43360
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VSHLuv1i64_:%[0-9]+]]:dpr = VSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv1i64_]]
+    ; SELECTED: [[VQSHLuv1i64_:%[0-9]+]]:dpr = VQSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule490_id1276_at_idx41314
+name:            test_rule522_id1360_at_idx43426
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule490_id1276_at_idx41314
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule522_id1360_at_idx43426
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQSHLuv2i64_:%[0-9]+]]:qpr = VQSHLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule491_id1310_at_idx41380
+name:            test_rule523_id1394_at_idx43492
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13391,20 +21094,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule491_id1310_at_idx41380
+    ; SELECTED-LABEL: name: test_rule523_id1394_at_idx43492
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLsv4i16_:%[0-9]+]]:dpr = VRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv4i16_]]
+    ; SELECTED: [[VQRSHLsv4i16_:%[0-9]+]]:dpr = VQRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule492_id1311_at_idx41446
+name:            test_rule524_id1395_at_idx43558
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13420,68 +21123,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule492_id1311_at_idx41446
+    ; SELECTED-LABEL: name: test_rule524_id1395_at_idx43558
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLsv2i32_:%[0-9]+]]:dpr = VRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv2i32_]]
+    ; SELECTED: [[VQRSHLsv2i32_:%[0-9]+]]:dpr = VQRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule493_id1312_at_idx41512
+name:            test_rule525_id1396_at_idx43624
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule493_id1312_at_idx41512
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule525_id1396_at_idx43624
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLsv8i16_:%[0-9]+]]:qpr = VQRSHLsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule494_id1313_at_idx41578
+name:            test_rule526_id1397_at_idx43690
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule494_id1313_at_idx41578
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule526_id1397_at_idx43690
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLsv4i32_:%[0-9]+]]:qpr = VQRSHLsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule495_id1314_at_idx41644
+name:            test_rule527_id1398_at_idx43756
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13497,44 +21210,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule495_id1314_at_idx41644
+    ; SELECTED-LABEL: name: test_rule527_id1398_at_idx43756
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLsv8i8_:%[0-9]+]]:dpr = VRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv8i8_]]
+    ; SELECTED: [[VQRSHLsv8i8_:%[0-9]+]]:dpr = VQRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule496_id1315_at_idx41710
+name:            test_rule528_id1399_at_idx43822
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule496_id1315_at_idx41710
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule528_id1399_at_idx43822
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLsv16i8_:%[0-9]+]]:qpr = VQRSHLsv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule497_id1316_at_idx41776
+name:            test_rule529_id1400_at_idx43888
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13550,44 +21268,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule497_id1316_at_idx41776
+    ; SELECTED-LABEL: name: test_rule529_id1400_at_idx43888
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLsv1i64_:%[0-9]+]]:dpr = VRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv1i64_]]
+    ; SELECTED: [[VQRSHLsv1i64_:%[0-9]+]]:dpr = VQRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule498_id1317_at_idx41842
+name:            test_rule530_id1401_at_idx43954
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule498_id1317_at_idx41842
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule530_id1401_at_idx43954
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLsv2i64_:%[0-9]+]]:qpr = VQRSHLsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule499_id1318_at_idx41908
+name:            test_rule531_id1402_at_idx44020
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13603,20 +21326,20 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule499_id1318_at_idx41908
+    ; SELECTED-LABEL: name: test_rule531_id1402_at_idx44020
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLuv4i16_:%[0-9]+]]:dpr = VRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv4i16_]]
+    ; SELECTED: [[VQRSHLuv4i16_:%[0-9]+]]:dpr = VQRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv4i16_]]
     %2:fprb(<4 x s16>) = COPY $d17
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule500_id1319_at_idx41974
+name:            test_rule532_id1403_at_idx44086
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13632,68 +21355,78 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule500_id1319_at_idx41974
+    ; SELECTED-LABEL: name: test_rule532_id1403_at_idx44086
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLuv2i32_:%[0-9]+]]:dpr = VRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv2i32_]]
+    ; SELECTED: [[VQRSHLuv2i32_:%[0-9]+]]:dpr = VQRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv2i32_]]
     %2:fprb(<2 x s32>) = COPY $d17
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule501_id1320_at_idx42040
+name:            test_rule533_id1404_at_idx44152
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule501_id1320_at_idx42040
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule533_id1404_at_idx44152
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLuv8i16_:%[0-9]+]]:qpr = VQRSHLuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule502_id1321_at_idx42106
+name:            test_rule534_id1405_at_idx44218
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule502_id1321_at_idx42106
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule534_id1405_at_idx44218
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLuv4i32_:%[0-9]+]]:qpr = VQRSHLuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule503_id1322_at_idx42172
+name:            test_rule535_id1406_at_idx44284
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13709,44 +21442,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule503_id1322_at_idx42172
+    ; SELECTED-LABEL: name: test_rule535_id1406_at_idx44284
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLuv8i8_:%[0-9]+]]:dpr = VRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv8i8_]]
+    ; SELECTED: [[VQRSHLuv8i8_:%[0-9]+]]:dpr = VQRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv8i8_]]
     %2:fprb(<8 x s8>) = COPY $d17
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule504_id1323_at_idx42238
+name:            test_rule536_id1407_at_idx44350
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule504_id1323_at_idx42238
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule536_id1407_at_idx44350
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLuv16i8_:%[0-9]+]]:qpr = VQRSHLuv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule505_id1324_at_idx42304
+name:            test_rule537_id1408_at_idx44416
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13762,44 +21500,49 @@
   bb.0.entry:
     liveins: $d16, $d17
 
-    ; SELECTED-LABEL: name: test_rule505_id1324_at_idx42304
+    ; SELECTED-LABEL: name: test_rule537_id1408_at_idx44416
     ; SELECTED: liveins: $d16, $d17
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
     ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSHLuv1i64_:%[0-9]+]]:dpr = VRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv1i64_]]
+    ; SELECTED: [[VQRSHLuv1i64_:%[0-9]+]]:dpr = VQRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv1i64_]]
     %2:fprb(s64) = COPY $d17
     %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
     $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule506_id1325_at_idx42370
+name:            test_rule538_id1409_at_idx44482
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule506_id1325_at_idx42370
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule538_id1409_at_idx44482
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQRSHLuv2i64_:%[0-9]+]]:qpr = VQRSHLuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule507_id1345_at_idx42436
+name:            test_rule539_id1674_at_idx44548
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13809,26 +21552,26 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule507_id1345_at_idx42436
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLsv4i16_:%[0-9]+]]:dpr = VQSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule539_id1674_at_idx44548
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[AESD:%[0-9]+]]:qpr = AESD [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESD]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule508_id1346_at_idx42502
+name:            test_rule540_id1675_at_idx44608
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -13838,912 +21581,1070 @@
   - { id: 1, class: fprb }
   - { id: 2, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $q8, $q9
 
-    ; SELECTED-LABEL: name: test_rule508_id1346_at_idx42502
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLsv2i32_:%[0-9]+]]:dpr = VQSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule540_id1675_at_idx44608
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[AESE:%[0-9]+]]:qpr = AESE [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESE]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule509_id1347_at_idx42568
+name:            test_rule541_id1678_at_idx44668
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule509_id1347_at_idx42568
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule541_id1678_at_idx44668
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA1SU1_:%[0-9]+]]:qpr = SHA1SU1 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1SU1_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule510_id1348_at_idx42634
+name:            test_rule542_id1679_at_idx44728
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule510_id1348_at_idx42634
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule542_id1679_at_idx44728
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[SHA256SU0_:%[0-9]+]]:qpr = SHA256SU0 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256SU0_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule511_id1349_at_idx42700
+name:            test_rule543_id1712_at_idx44788
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule511_id1349_at_idx42700
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLsv8i8_:%[0-9]+]]:dpr = VQSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule543_id1712_at_idx44788
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SXTAB16_:%[0-9]+]]:gprnopc = SXTAB16 [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SXTAB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtab16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule512_id1350_at_idx42766
+name:            test_rule544_id1717_at_idx44857
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule512_id1350_at_idx42766
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule544_id1717_at_idx44857
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2UXTAB16_:%[0-9]+]]:rgpr = t2UXTAB16 [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2UXTAB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtab16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule513_id1351_at_idx42832
+name:            test_rule545_id1743_at_idx44926
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule545_id1743_at_idx44926
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUAD:%[0-9]+]]:rgpr = t2SMUAD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUAD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuad), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule546_id1744_at_idx44992
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule546_id1744_at_idx44992
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUADX:%[0-9]+]]:rgpr = t2SMUADX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUADX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuadx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule547_id1745_at_idx45058
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule513_id1351_at_idx42832
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLsv1i64_:%[0-9]+]]:dpr = VQSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED-LABEL: name: test_rule547_id1745_at_idx45058
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUSD:%[0-9]+]]:rgpr = t2SMUSD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUSD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule514_id1352_at_idx42898
+name:            test_rule548_id1746_at_idx45124
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule514_id1352_at_idx42898
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule548_id1746_at_idx45124
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2SMUSDX:%[0-9]+]]:rgpr = t2SMUSDX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2SMUSDX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusdx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule515_id1353_at_idx42964
+name:            test_rule549_id1803_at_idx45190
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule515_id1353_at_idx42964
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLuv4i16_:%[0-9]+]]:dpr = VQSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule549_id1803_at_idx45190
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULBB:%[0-9]+]]:gpr = SMULBB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULBB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule516_id1354_at_idx43030
+name:            test_rule550_id1804_at_idx45256
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule516_id1354_at_idx43030
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLuv2i32_:%[0-9]+]]:dpr = VQSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule550_id1804_at_idx45256
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULBT:%[0-9]+]]:gpr = SMULBT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULBT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule517_id1355_at_idx43096
+name:            test_rule551_id1805_at_idx45322
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule517_id1355_at_idx43096
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule551_id1805_at_idx45322
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTB:%[0-9]+]]:gpr = SMULTB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule518_id1356_at_idx43162
+name:            test_rule552_id1806_at_idx45388
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule518_id1356_at_idx43162
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule552_id1806_at_idx45388
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule519_id1357_at_idx43228
+name:            test_rule553_id1807_at_idx45454
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule519_id1357_at_idx43228
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLuv8i8_:%[0-9]+]]:dpr = VQSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule553_id1807_at_idx45454
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULWB:%[0-9]+]]:gpr = SMULWB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULWB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule520_id1358_at_idx43294
+name:            test_rule554_id1808_at_idx45520
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule520_id1358_at_idx43294
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule554_id1808_at_idx45520
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULWT:%[0-9]+]]:gpr = SMULWT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULWT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule521_id1359_at_idx43360
+name:            test_rule555_id1903_at_idx45586
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule521_id1359_at_idx43360
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQSHLuv1i64_:%[0-9]+]]:dpr = VQSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED-LABEL: name: test_rule555_id1903_at_idx45586
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SXTAB16_:%[0-9]+]]:gprnopc = SXTAB16 [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SXTAB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtab16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule522_id1360_at_idx43426
+name:            test_rule556_id1928_at_idx45655
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule522_id1360_at_idx43426
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule556_id1928_at_idx45655
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QADD:%[0-9]+]]:gprnopc = QADD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QADD]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule523_id1394_at_idx43492
+name:            test_rule557_id1929_at_idx45721
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule523_id1394_at_idx43492
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLsv4i16_:%[0-9]+]]:dpr = VQRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule557_id1929_at_idx45721
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[QSUB:%[0-9]+]]:gprnopc = QSUB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[QSUB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule524_id1395_at_idx43558
+name:            test_rule558_id1946_at_idx45787
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule524_id1395_at_idx43558
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLsv2i32_:%[0-9]+]]:dpr = VQRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule558_id1946_at_idx45787
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULBB:%[0-9]+]]:gpr = SMULBB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULBB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule525_id1396_at_idx43624
+name:            test_rule559_id1947_at_idx45853
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule525_id1396_at_idx43624
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule559_id1947_at_idx45853
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULBT:%[0-9]+]]:gpr = SMULBT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULBT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule526_id1397_at_idx43690
+name:            test_rule560_id1948_at_idx45919
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule526_id1397_at_idx43690
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule560_id1948_at_idx45919
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTB:%[0-9]+]]:gpr = SMULTB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule527_id1398_at_idx43756
+name:            test_rule561_id1949_at_idx45985
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule527_id1398_at_idx43756
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLsv8i8_:%[0-9]+]]:dpr = VQRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule561_id1949_at_idx45985
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule528_id1399_at_idx43822
+name:            test_rule562_id1950_at_idx46051
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule528_id1399_at_idx43822
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule562_id1950_at_idx46051
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULWB:%[0-9]+]]:gpr = SMULWB [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULWB]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule529_id1400_at_idx43888
+name:            test_rule563_id1951_at_idx46117
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule529_id1400_at_idx43888
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLsv1i64_:%[0-9]+]]:dpr = VQRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED-LABEL: name: test_rule563_id1951_at_idx46117
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULWT:%[0-9]+]]:gpr = SMULWT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULWT]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule530_id1401_at_idx43954
+name:            test_rule564_id3_at_idx46183
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule530_id1401_at_idx43954
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule564_id3_at_idx46183
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SEL:%[0-9]+]]:gpr = SEL [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule531_id1402_at_idx44020
+name:            test_rule565_id123_at_idx46253
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule531_id1402_at_idx44020
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLuv4i16_:%[0-9]+]]:dpr = VQRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv4i16_]]
-    %2:fprb(<4 x s16>) = COPY $d17
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule565_id123_at_idx46253
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SASX:%[0-9]+]]:gprnopc = SASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule532_id1403_at_idx44086
+name:            test_rule566_id124_at_idx46323
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule532_id1403_at_idx44086
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLuv2i32_:%[0-9]+]]:dpr = VQRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv2i32_]]
-    %2:fprb(<2 x s32>) = COPY $d17
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule566_id124_at_idx46323
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD16_:%[0-9]+]]:gprnopc = SADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule533_id1404_at_idx44152
+name:            test_rule567_id125_at_idx46393
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule533_id1404_at_idx44152
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule567_id125_at_idx46393
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD8_:%[0-9]+]]:gprnopc = SADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule534_id1405_at_idx44218
+name:            test_rule568_id126_at_idx46463
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule534_id1405_at_idx44218
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule568_id126_at_idx46463
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSAX:%[0-9]+]]:gprnopc = SSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule535_id1406_at_idx44284
+name:            test_rule569_id127_at_idx46533
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule535_id1406_at_idx44284
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLuv8i8_:%[0-9]+]]:dpr = VQRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv8i8_]]
-    %2:fprb(<8 x s8>) = COPY $d17
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule569_id127_at_idx46533
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB16_:%[0-9]+]]:gprnopc = SSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule536_id1407_at_idx44350
+name:            test_rule570_id128_at_idx46603
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule536_id1407_at_idx44350
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule570_id128_at_idx46603
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB8_:%[0-9]+]]:gprnopc = SSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule537_id1408_at_idx44416
+name:            test_rule571_id129_at_idx46673
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
-  - { id: 2, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
-  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16, $d17
+    liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule537_id1408_at_idx44416
-    ; SELECTED: liveins: $d16, $d17
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
-    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQRSHLuv1i64_:%[0-9]+]]:dpr = VQRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv1i64_]]
-    %2:fprb(s64) = COPY $d17
-    %1:fprb(s64) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
-    $noreg = PATCHABLE_RET %0(s64)
+    ; SELECTED-LABEL: name: test_rule571_id129_at_idx46673
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UASX:%[0-9]+]]:gprnopc = UASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule538_id1409_at_idx44482
+name:            test_rule572_id130_at_idx46743
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule538_id1409_at_idx44482
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule572_id130_at_idx46743
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD16_:%[0-9]+]]:gprnopc = UADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule539_id1674_at_idx44548
+name:            test_rule573_id131_at_idx46813
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule539_id1674_at_idx44548
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule573_id131_at_idx46813
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD8_:%[0-9]+]]:gprnopc = UADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule540_id1675_at_idx44608
+name:            test_rule574_id132_at_idx46883
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule540_id1675_at_idx44608
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule574_id132_at_idx46883
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAX:%[0-9]+]]:gprnopc = USAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule541_id1678_at_idx44668
+name:            test_rule575_id133_at_idx46953
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule541_id1678_at_idx44668
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule575_id133_at_idx46953
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB16_:%[0-9]+]]:gprnopc = USUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule542_id1679_at_idx44728
+name:            test_rule576_id134_at_idx47023
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule542_id1679_at_idx44728
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule576_id134_at_idx47023
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB8_:%[0-9]+]]:gprnopc = USUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule564_id3_at_idx46183
+name:            test_rule577_id435_at_idx47093
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14759,7 +22660,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule564_id3_at_idx46183
+    ; SELECTED-LABEL: name: test_rule577_id435_at_idx47093
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
@@ -14772,7 +22673,7 @@
 
 ...
 ---
-name:            test_rule565_id123_at_idx46253
+name:            test_rule578_id448_at_idx47163
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14788,7 +22689,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule565_id123_at_idx46253
+    ; SELECTED-LABEL: name: test_rule578_id448_at_idx47163
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14801,7 +22702,7 @@
 
 ...
 ---
-name:            test_rule566_id124_at_idx46323
+name:            test_rule579_id449_at_idx47233
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14817,7 +22718,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule566_id124_at_idx46323
+    ; SELECTED-LABEL: name: test_rule579_id449_at_idx47233
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14830,7 +22731,7 @@
 
 ...
 ---
-name:            test_rule567_id125_at_idx46393
+name:            test_rule580_id450_at_idx47303
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14846,7 +22747,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule567_id125_at_idx46393
+    ; SELECTED-LABEL: name: test_rule580_id450_at_idx47303
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14859,7 +22760,7 @@
 
 ...
 ---
-name:            test_rule568_id126_at_idx46463
+name:            test_rule581_id451_at_idx47373
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14875,7 +22776,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule568_id126_at_idx46463
+    ; SELECTED-LABEL: name: test_rule581_id451_at_idx47373
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14888,7 +22789,7 @@
 
 ...
 ---
-name:            test_rule569_id127_at_idx46533
+name:            test_rule582_id452_at_idx47443
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14904,7 +22805,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule569_id127_at_idx46533
+    ; SELECTED-LABEL: name: test_rule582_id452_at_idx47443
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14917,7 +22818,7 @@
 
 ...
 ---
-name:            test_rule570_id128_at_idx46603
+name:            test_rule583_id453_at_idx47513
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14933,7 +22834,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule570_id128_at_idx46603
+    ; SELECTED-LABEL: name: test_rule583_id453_at_idx47513
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14946,7 +22847,7 @@
 
 ...
 ---
-name:            test_rule571_id129_at_idx46673
+name:            test_rule584_id454_at_idx47583
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14962,7 +22863,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule571_id129_at_idx46673
+    ; SELECTED-LABEL: name: test_rule584_id454_at_idx47583
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -14975,7 +22876,7 @@
 
 ...
 ---
-name:            test_rule572_id130_at_idx46743
+name:            test_rule585_id455_at_idx47653
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -14991,7 +22892,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule572_id130_at_idx46743
+    ; SELECTED-LABEL: name: test_rule585_id455_at_idx47653
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -15004,7 +22905,7 @@
 
 ...
 ---
-name:            test_rule573_id131_at_idx46813
+name:            test_rule586_id456_at_idx47723
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15020,7 +22921,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule573_id131_at_idx46813
+    ; SELECTED-LABEL: name: test_rule586_id456_at_idx47723
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -15033,7 +22934,7 @@
 
 ...
 ---
-name:            test_rule574_id132_at_idx46883
+name:            test_rule587_id457_at_idx47793
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15049,7 +22950,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule574_id132_at_idx46883
+    ; SELECTED-LABEL: name: test_rule587_id457_at_idx47793
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -15062,7 +22963,7 @@
 
 ...
 ---
-name:            test_rule575_id133_at_idx46953
+name:            test_rule588_id458_at_idx47863
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15078,7 +22979,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule575_id133_at_idx46953
+    ; SELECTED-LABEL: name: test_rule588_id458_at_idx47863
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -15091,7 +22992,7 @@
 
 ...
 ---
-name:            test_rule576_id134_at_idx47023
+name:            test_rule589_id459_at_idx47933
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15107,7 +23008,7 @@
   bb.0.entry:
     liveins: $lr, $r0
 
-    ; SELECTED-LABEL: name: test_rule576_id134_at_idx47023
+    ; SELECTED-LABEL: name: test_rule589_id459_at_idx47933
     ; SELECTED: liveins: $lr, $r0
     ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
     ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
@@ -15120,7 +23021,7 @@
 
 ...
 ---
-name:            test_rule577_id435_at_idx47093
+name:            test_rule590_id351_at_idx48003
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15131,25 +23032,23 @@
   - { id: 2, class: gprb }
 liveins:
   - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule577_id435_at_idx47093
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[SEL:%[0-9]+]]:gpr = SEL [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SEL]]
-    %2:gprb(s32) = COPY $r0
+    ; SELECTED-LABEL: name: test_rule590_id351_at_idx48003
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
     %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule578_id448_at_idx47163
+name:            test_rule591_id352_at_idx48061
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15160,398 +23059,573 @@
   - { id: 2, class: gprb }
 liveins:
   - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule578_id448_at_idx47163
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SASX:%[0-9]+]]:gprnopc = SASX [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SASX]]
-    %2:gprb(s32) = COPY $r0
+    ; SELECTED-LABEL: name: test_rule591_id352_at_idx48061
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
     %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule579_id449_at_idx47233
+name:            test_rule592_id684_at_idx48119
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule579_id449_at_idx47233
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SADD16_:%[0-9]+]]:gprnopc = SADD16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SADD16_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+    ; SELECTED-LABEL: name: test_rule592_id684_at_idx48119
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTOSIRD:%[0-9]+]]:spr = VTOSIRD [[COPY]], 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTOSIRD]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtr), %1(s64)
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule580_id450_at_idx47303
+name:            test_rule593_id685_at_idx48173
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$s0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $s0
 
-    ; SELECTED-LABEL: name: test_rule580_id450_at_idx47303
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SADD8_:%[0-9]+]]:gprnopc = SADD8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SADD8_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+    ; SELECTED-LABEL: name: test_rule593_id685_at_idx48173
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VTOSIRS:%[0-9]+]]:spr = VTOSIRS [[COPY]], 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTOSIRS]]
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtr), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule594_id686_at_idx48227
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule594_id686_at_idx48227
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTOUIRD:%[0-9]+]]:spr = VTOUIRD [[COPY]], 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTOUIRD]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtru), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule595_id687_at_idx48281
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule595_id687_at_idx48281
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VTOUIRS:%[0-9]+]]:spr = VTOUIRS [[COPY]], 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTOUIRS]]
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtru), %1(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule581_id451_at_idx47373
+name:            test_rule596_id1201_at_idx48335
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule596_id1201_at_idx48335
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv8i8_:%[0-9]+]]:dpr = VPADDLsv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule597_id1202_at_idx48389
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule597_id1202_at_idx48389
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv4i16_:%[0-9]+]]:dpr = VPADDLsv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule598_id1203_at_idx48443
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule598_id1203_at_idx48443
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv2i32_:%[0-9]+]]:dpr = VPADDLsv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule599_id1204_at_idx48497
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule599_id1204_at_idx48497
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLsv16i8_:%[0-9]+]]:qpr = VPADDLsv16i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv16i8_]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule600_id1205_at_idx48551
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule600_id1205_at_idx48551
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLsv8i16_:%[0-9]+]]:qpr = VPADDLsv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv8i16_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule601_id1206_at_idx48605
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule601_id1206_at_idx48605
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLsv4i32_:%[0-9]+]]:qpr = VPADDLsv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv4i32_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule602_id1207_at_idx48659
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule581_id451_at_idx47373
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SSAX:%[0-9]+]]:gprnopc = SSAX [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SSAX]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule602_id1207_at_idx48659
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv8i8_:%[0-9]+]]:dpr = VPADDLuv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule582_id452_at_idx47443
+name:            test_rule603_id1208_at_idx48713
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule582_id452_at_idx47443
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SSUB16_:%[0-9]+]]:gprnopc = SSUB16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB16_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule603_id1208_at_idx48713
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv4i16_:%[0-9]+]]:dpr = VPADDLuv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule583_id453_at_idx47513
+name:            test_rule604_id1209_at_idx48767
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule583_id453_at_idx47513
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[SSUB8_:%[0-9]+]]:gprnopc = SSUB8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB8_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule604_id1209_at_idx48767
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv2i32_:%[0-9]+]]:dpr = VPADDLuv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
 
 ...
 ---
-name:            test_rule584_id454_at_idx47583
+name:            test_rule605_id1210_at_idx48821
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule584_id454_at_idx47583
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UASX:%[0-9]+]]:gprnopc = UASX [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UASX]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule605_id1210_at_idx48821
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLuv16i8_:%[0-9]+]]:qpr = VPADDLuv16i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv16i8_]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule585_id455_at_idx47653
+name:            test_rule606_id1211_at_idx48875
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule585_id455_at_idx47653
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UADD16_:%[0-9]+]]:gprnopc = UADD16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UADD16_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule606_id1211_at_idx48875
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLuv8i16_:%[0-9]+]]:qpr = VPADDLuv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv8i16_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule586_id456_at_idx47723
+name:            test_rule607_id1212_at_idx48929
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule586_id456_at_idx47723
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UADD8_:%[0-9]+]]:gprnopc = UADD8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UADD8_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule607_id1212_at_idx48929
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VPADDLuv4i32_:%[0-9]+]]:qpr = VPADDLuv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv4i32_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
-name:            test_rule587_id457_at_idx47793
+name:            test_rule608_id1241_at_idx48983
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule587_id457_at_idx47793
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[USAX:%[0-9]+]]:gprnopc = USAX [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[USAX]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule608_id1241_at_idx48983
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule588_id458_at_idx47863
+name:            test_rule609_id1242_at_idx49037
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule588_id458_at_idx47863
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[USUB16_:%[0-9]+]]:gprnopc = USUB16 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[USUB16_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule609_id1242_at_idx49037
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRECPEq:%[0-9]+]]:qpr = VRECPEq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule589_id459_at_idx47933
+name:            test_rule610_id1243_at_idx49091
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
-  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr, $r0
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule589_id459_at_idx47933
-    ; SELECTED: liveins: $lr, $r0
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
-    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[USUB8_:%[0-9]+]]:gprnopc = USUB8 [[COPY1]], [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[USUB8_]]
-    %2:gprb(s32) = COPY $r0
-    %1:gprb(s32) = COPY $lr
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule610_id1243_at_idx49091
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule611_id1244_at_idx49145
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule611_id1244_at_idx49145
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRECPEq:%[0-9]+]]:qpr = VRECPEq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule590_id351_at_idx48003
+name:            test_rule612_id1245_at_idx49199
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule590_id351_at_idx48003
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
-    %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 255
-    %0:gprb(s32) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule612_id1245_at_idx49199
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEhd:%[0-9]+]]:dpr = VRECPEhd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEhd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule591_id352_at_idx48061
+name:            test_rule613_id1246_at_idx49253
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $lr
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule591_id352_at_idx48061
-    ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
-    %1:gprb(s32) = COPY $lr
-    %2:gprb(s32) = G_CONSTANT 65535
-    %0:gprb(s32) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(s32)
+    ; SELECTED-LABEL: name: test_rule613_id1246_at_idx49253
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRECPEhq:%[0-9]+]]:qpr = VRECPEhq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEhq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule596_id1201_at_idx48335
+name:            test_rule614_id1251_at_idx49307
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15565,18 +23639,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule596_id1201_at_idx48335
+    ; SELECTED-LABEL: name: test_rule614_id1251_at_idx49307
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLsv8i8_:%[0-9]+]]:dpr = VPADDLsv8i8 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv8i8_]]
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule597_id1202_at_idx48389
+name:            test_rule615_id1252_at_idx49361
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15585,23 +23659,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule597_id1202_at_idx48389
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLsv4i16_:%[0-9]+]]:dpr = VPADDLsv4i16 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv4i16_]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule615_id1252_at_idx49361
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSQRTEq:%[0-9]+]]:qpr = VRSQRTEq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule598_id1203_at_idx48443
+name:            test_rule616_id1253_at_idx49415
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15615,81 +23689,93 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule598_id1203_at_idx48443
+    ; SELECTED-LABEL: name: test_rule616_id1253_at_idx49415
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLsv2i32_:%[0-9]+]]:dpr = VPADDLsv2i32 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv2i32_]]
+    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(s64)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule599_id1204_at_idx48497
+name:            test_rule617_id1254_at_idx49469
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule599_id1204_at_idx48497
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule617_id1254_at_idx49469
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSQRTEq:%[0-9]+]]:qpr = VRSQRTEq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule600_id1205_at_idx48551
+name:            test_rule618_id1255_at_idx49523
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule600_id1205_at_idx48551
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule618_id1255_at_idx49523
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTEhd:%[0-9]+]]:dpr = VRSQRTEhd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEhd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule601_id1206_at_idx48605
+name:            test_rule619_id1256_at_idx49577
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule601_id1206_at_idx48605
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule619_id1256_at_idx49577
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRSQRTEhq:%[0-9]+]]:qpr = VRSQRTEhq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEhq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule602_id1207_at_idx48659
+name:            test_rule620_id1477_at_idx49631
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15703,18 +23789,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule602_id1207_at_idx48659
+    ; SELECTED-LABEL: name: test_rule620_id1477_at_idx49631
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLuv8i8_:%[0-9]+]]:dpr = VPADDLuv8i8 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv8i8_]]
+    ; SELECTED: [[VQABSv8i8_:%[0-9]+]]:dpr = VQABSv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv8i8_]]
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule603_id1208_at_idx48713
+name:            test_rule621_id1478_at_idx49685
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15728,18 +23814,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule603_id1208_at_idx48713
+    ; SELECTED-LABEL: name: test_rule621_id1478_at_idx49685
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLuv4i16_:%[0-9]+]]:dpr = VPADDLuv4i16 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv4i16_]]
+    ; SELECTED: [[VQABSv4i16_:%[0-9]+]]:dpr = VQABSv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv4i16_]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule604_id1209_at_idx48767
+name:            test_rule622_id1479_at_idx49739
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15753,81 +23839,93 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule604_id1209_at_idx48767
+    ; SELECTED-LABEL: name: test_rule622_id1479_at_idx49739
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VPADDLuv2i32_:%[0-9]+]]:dpr = VPADDLuv2i32 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv2i32_]]
+    ; SELECTED: [[VQABSv2i32_:%[0-9]+]]:dpr = VQABSv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv2i32_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(s64)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule605_id1210_at_idx48821
+name:            test_rule623_id1480_at_idx49793
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule605_id1210_at_idx48821
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule623_id1480_at_idx49793
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQABSv16i8_:%[0-9]+]]:qpr = VQABSv16i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv16i8_]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule606_id1211_at_idx48875
+name:            test_rule624_id1481_at_idx49847
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule606_id1211_at_idx48875
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule624_id1481_at_idx49847
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQABSv8i16_:%[0-9]+]]:qpr = VQABSv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv8i16_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule607_id1212_at_idx48929
+name:            test_rule625_id1482_at_idx49901
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule607_id1212_at_idx48929
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule625_id1482_at_idx49901
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQABSv4i32_:%[0-9]+]]:qpr = VQABSv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv4i32_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule608_id1241_at_idx48983
+name:            test_rule626_id1493_at_idx49955
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15841,39 +23939,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule608_id1241_at_idx48983
+    ; SELECTED-LABEL: name: test_rule626_id1493_at_idx49955
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VQNEGv8i8_:%[0-9]+]]:dpr = VQNEGv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule609_id1242_at_idx49037
+name:            test_rule627_id1494_at_idx50009
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule609_id1242_at_idx49037
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule627_id1494_at_idx50009
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQNEGv4i16_:%[0-9]+]]:dpr = VQNEGv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule610_id1243_at_idx49091
+name:            test_rule628_id1495_at_idx50063
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15887,39 +23989,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule610_id1243_at_idx49091
+    ; SELECTED-LABEL: name: test_rule628_id1495_at_idx50063
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
+    ; SELECTED: [[VQNEGv2i32_:%[0-9]+]]:dpr = VQNEGv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv2i32_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule611_id1244_at_idx49145
+name:            test_rule629_id1496_at_idx50117
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule611_id1244_at_idx49145
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule629_id1496_at_idx50117
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQNEGv16i8_:%[0-9]+]]:qpr = VQNEGv16i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv16i8_]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule612_id1245_at_idx49199
+name:            test_rule630_id1497_at_idx50171
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15928,44 +24034,48 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule612_id1245_at_idx49199
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRECPEhd:%[0-9]+]]:dpr = VRECPEhd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEhd]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule630_id1497_at_idx50171
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQNEGv8i16_:%[0-9]+]]:qpr = VQNEGv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv8i16_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule613_id1246_at_idx49253
+name:            test_rule631_id1498_at_idx50225
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule613_id1246_at_idx49253
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule631_id1498_at_idx50225
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQNEGv4i32_:%[0-9]+]]:qpr = VQNEGv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv4i32_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule614_id1251_at_idx49307
+name:            test_rule632_id1499_at_idx50279
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -15979,39 +24089,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule614_id1251_at_idx49307
+    ; SELECTED-LABEL: name: test_rule632_id1499_at_idx50279
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VCLSv8i8_:%[0-9]+]]:dpr = VCLSv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule615_id1252_at_idx49361
+name:            test_rule633_id1500_at_idx50333
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule615_id1252_at_idx49361
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule633_id1500_at_idx50333
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCLSv4i16_:%[0-9]+]]:dpr = VCLSv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule616_id1253_at_idx49415
+name:            test_rule634_id1501_at_idx50387
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16025,39 +24139,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule616_id1253_at_idx49415
+    ; SELECTED-LABEL: name: test_rule634_id1501_at_idx50387
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
+    ; SELECTED: [[VCLSv2i32_:%[0-9]+]]:dpr = VCLSv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv2i32_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule617_id1254_at_idx49469
+name:            test_rule635_id1502_at_idx50441
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule617_id1254_at_idx49469
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule635_id1502_at_idx50441
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCLSv16i8_:%[0-9]+]]:qpr = VCLSv16i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv16i8_]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule618_id1255_at_idx49523
+name:            test_rule636_id1503_at_idx50495
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16066,44 +24184,48 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule618_id1255_at_idx49523
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRSQRTEhd:%[0-9]+]]:dpr = VRSQRTEhd [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEhd]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule636_id1503_at_idx50495
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCLSv8i16_:%[0-9]+]]:qpr = VCLSv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv8i16_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule619_id1256_at_idx49577
+name:            test_rule637_id1504_at_idx50549
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule619_id1256_at_idx49577
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule637_id1504_at_idx50549
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCLSv4i32_:%[0-9]+]]:qpr = VCLSv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv4i32_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule620_id1477_at_idx49631
+name:            test_rule638_id1548_at_idx50603
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16112,23 +24234,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule620_id1477_at_idx49631
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQABSv8i8_:%[0-9]+]]:dpr = VQABSv8i8 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv8i8_]]
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule638_id1548_at_idx50603
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsv8i8_:%[0-9]+]]:dpr = VQMOVNsv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsv8i8_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule621_id1478_at_idx49685
+name:            test_rule639_id1549_at_idx50657
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16137,23 +24259,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule621_id1478_at_idx49685
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQABSv4i16_:%[0-9]+]]:dpr = VQABSv4i16 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv4i16_]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule639_id1549_at_idx50657
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsv4i16_:%[0-9]+]]:dpr = VQMOVNsv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsv4i16_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule622_id1479_at_idx49739
+name:            test_rule640_id1550_at_idx50711
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16162,86 +24284,98 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule622_id1479_at_idx49739
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQABSv2i32_:%[0-9]+]]:dpr = VQABSv2i32 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv2i32_]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule640_id1550_at_idx50711
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsv2i32_:%[0-9]+]]:dpr = VQMOVNsv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsv2i32_]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule623_id1480_at_idx49793
+name:            test_rule641_id1551_at_idx50765
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule623_id1480_at_idx49793
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule641_id1551_at_idx50765
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNuv8i8_:%[0-9]+]]:dpr = VQMOVNuv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNuv8i8_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule624_id1481_at_idx49847
+name:            test_rule642_id1552_at_idx50819
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule624_id1481_at_idx49847
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule642_id1552_at_idx50819
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNuv4i16_:%[0-9]+]]:dpr = VQMOVNuv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNuv4i16_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule625_id1482_at_idx49901
+name:            test_rule643_id1553_at_idx50873
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule625_id1482_at_idx49901
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule643_id1553_at_idx50873
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNuv2i32_:%[0-9]+]]:dpr = VQMOVNuv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNuv2i32_]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule626_id1493_at_idx49955
+name:            test_rule644_id1554_at_idx50927
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16250,23 +24384,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule626_id1493_at_idx49955
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQNEGv8i8_:%[0-9]+]]:dpr = VQNEGv8i8 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv8i8_]]
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
+    ; SELECTED-LABEL: name: test_rule644_id1554_at_idx50927
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsuv8i8_:%[0-9]+]]:dpr = VQMOVNsuv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsuv8i8_]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
 ...
 ---
-name:            test_rule627_id1494_at_idx50009
+name:            test_rule645_id1555_at_idx50981
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16275,23 +24409,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule627_id1494_at_idx50009
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQNEGv4i16_:%[0-9]+]]:dpr = VQNEGv4i16 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv4i16_]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule645_id1555_at_idx50981
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsuv4i16_:%[0-9]+]]:dpr = VQMOVNsuv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsuv4i16_]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule628_id1495_at_idx50063
+name:            test_rule646_id1556_at_idx51035
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16300,86 +24434,73 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule628_id1495_at_idx50063
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VQNEGv2i32_:%[0-9]+]]:dpr = VQNEGv2i32 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv2i32_]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule646_id1556_at_idx51035
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VQMOVNsuv2i32_:%[0-9]+]]:dpr = VQMOVNsuv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQMOVNsuv2i32_]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule629_id1496_at_idx50117
+name:            test_rule647_id1579_at_idx51089
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule629_id1496_at_idx50117
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $d16
 
-...
----
-name:            test_rule630_id1497_at_idx50171
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule630_id1497_at_idx50171
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule647_id1579_at_idx51089
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANSDf:%[0-9]+]]:dpr = VCVTANSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule631_id1498_at_idx50225
+name:            test_rule648_id1580_at_idx51137
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule631_id1498_at_idx50225
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule648_id1580_at_idx51137
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTANSQf:%[0-9]+]]:qpr = VCVTANSQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule632_id1499_at_idx50279
+name:            test_rule649_id1581_at_idx51185
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16393,18 +24514,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule632_id1499_at_idx50279
+    ; SELECTED-LABEL: name: test_rule649_id1581_at_idx51185
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCLSv8i8_:%[0-9]+]]:dpr = VCLSv8i8 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv8i8_]]
-    %1:fprb(<8 x s8>) = COPY $d16
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    ; SELECTED: [[VCVTANUDf:%[0-9]+]]:dpr = VCVTANUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule633_id1500_at_idx50333
+name:            test_rule650_id1582_at_idx51233
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16413,23 +24534,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule633_id1500_at_idx50333
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCLSv4i16_:%[0-9]+]]:dpr = VCLSv4i16 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv4i16_]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule650_id1582_at_idx51233
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTANUQf:%[0-9]+]]:qpr = VCVTANUQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule634_id1501_at_idx50387
+name:            test_rule651_id1583_at_idx51281
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16443,270 +24564,293 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule634_id1501_at_idx50387
+    ; SELECTED-LABEL: name: test_rule651_id1583_at_idx51281
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCLSv2i32_:%[0-9]+]]:dpr = VCLSv2i32 [[COPY]], 14, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv2i32_]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED: [[VCVTANSDh:%[0-9]+]]:dpr = VCVTANSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule635_id1502_at_idx50441
+name:            test_rule652_id1584_at_idx51329
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule635_id1502_at_idx50441
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $q8
 
-...
----
-name:            test_rule636_id1503_at_idx50495
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule636_id1503_at_idx50495
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule652_id1584_at_idx51329
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTANSQh:%[0-9]+]]:qpr = VCVTANSQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule637_id1504_at_idx50549
+name:            test_rule653_id1585_at_idx51377
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule637_id1504_at_idx50549
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule653_id1585_at_idx51377
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANUDh:%[0-9]+]]:dpr = VCVTANUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule638_id1548_at_idx50603
+name:            test_rule654_id1586_at_idx51425
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule638_id1548_at_idx50603
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule654_id1586_at_idx51425
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTANUQh:%[0-9]+]]:qpr = VCVTANUQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule639_id1549_at_idx50657
+name:            test_rule655_id1587_at_idx51473
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule639_id1549_at_idx50657
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule655_id1587_at_idx51473
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNSDf:%[0-9]+]]:dpr = VCVTNNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule640_id1550_at_idx50711
+name:            test_rule656_id1588_at_idx51521
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule640_id1550_at_idx50711
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule656_id1588_at_idx51521
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTNNSQf:%[0-9]+]]:qpr = VCVTNNSQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule641_id1551_at_idx50765
+name:            test_rule657_id1589_at_idx51569
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule641_id1551_at_idx50765
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule657_id1589_at_idx51569
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNUDf:%[0-9]+]]:dpr = VCVTNNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule642_id1552_at_idx50819
+name:            test_rule658_id1590_at_idx51617
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule642_id1552_at_idx50819
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule658_id1590_at_idx51617
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTNNUQf:%[0-9]+]]:qpr = VCVTNNUQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule643_id1553_at_idx50873
+name:            test_rule659_id1591_at_idx51665
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule643_id1553_at_idx50873
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule659_id1591_at_idx51665
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNSDh:%[0-9]+]]:dpr = VCVTNNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule644_id1554_at_idx50927
+name:            test_rule660_id1592_at_idx51713
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule644_id1554_at_idx50927
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule660_id1592_at_idx51713
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTNNSQh:%[0-9]+]]:qpr = VCVTNNSQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule645_id1555_at_idx50981
+name:            test_rule661_id1593_at_idx51761
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule645_id1555_at_idx50981
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule661_id1593_at_idx51761
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNUDh:%[0-9]+]]:dpr = VCVTNNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule646_id1556_at_idx51035
+name:            test_rule662_id1594_at_idx51809
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule646_id1556_at_idx51035
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule662_id1594_at_idx51809
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTNNUQh:%[0-9]+]]:qpr = VCVTNNUQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule647_id1579_at_idx51089
+name:            test_rule663_id1595_at_idx51857
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16720,39 +24864,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule647_id1579_at_idx51089
+    ; SELECTED-LABEL: name: test_rule663_id1595_at_idx51857
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTANSDf:%[0-9]+]]:dpr = VCVTANSDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDf]]
+    ; SELECTED: [[VCVTPNSDf:%[0-9]+]]:dpr = VCVTPNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule648_id1580_at_idx51137
+name:            test_rule664_id1596_at_idx51905
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule648_id1580_at_idx51137
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule664_id1596_at_idx51905
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTPNSQf:%[0-9]+]]:qpr = VCVTPNSQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule649_id1581_at_idx51185
+name:            test_rule665_id1597_at_idx51953
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16766,39 +24914,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule649_id1581_at_idx51185
+    ; SELECTED-LABEL: name: test_rule665_id1597_at_idx51953
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTANUDf:%[0-9]+]]:dpr = VCVTANUDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDf]]
+    ; SELECTED: [[VCVTPNUDf:%[0-9]+]]:dpr = VCVTPNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule650_id1582_at_idx51233
+name:            test_rule666_id1598_at_idx52001
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule650_id1582_at_idx51233
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule666_id1598_at_idx52001
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTPNUQf:%[0-9]+]]:qpr = VCVTPNUQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule651_id1583_at_idx51281
+name:            test_rule667_id1599_at_idx52049
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16812,39 +24964,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule651_id1583_at_idx51281
+    ; SELECTED-LABEL: name: test_rule667_id1599_at_idx52049
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTANSDh:%[0-9]+]]:dpr = VCVTANSDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDh]]
+    ; SELECTED: [[VCVTPNSDh:%[0-9]+]]:dpr = VCVTPNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule652_id1584_at_idx51329
+name:            test_rule668_id1600_at_idx52097
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule652_id1584_at_idx51329
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule668_id1600_at_idx52097
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTPNSQh:%[0-9]+]]:qpr = VCVTPNSQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule653_id1585_at_idx51377
+name:            test_rule669_id1601_at_idx52145
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16858,39 +25014,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule653_id1585_at_idx51377
+    ; SELECTED-LABEL: name: test_rule669_id1601_at_idx52145
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTANUDh:%[0-9]+]]:dpr = VCVTANUDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDh]]
+    ; SELECTED: [[VCVTPNUDh:%[0-9]+]]:dpr = VCVTPNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule654_id1586_at_idx51425
+name:            test_rule670_id1602_at_idx52193
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule654_id1586_at_idx51425
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule670_id1602_at_idx52193
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTPNUQh:%[0-9]+]]:qpr = VCVTPNUQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule655_id1587_at_idx51473
+name:            test_rule671_id1603_at_idx52241
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16904,39 +25064,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule655_id1587_at_idx51473
+    ; SELECTED-LABEL: name: test_rule671_id1603_at_idx52241
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTNNSDf:%[0-9]+]]:dpr = VCVTNNSDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDf]]
+    ; SELECTED: [[VCVTMNSDf:%[0-9]+]]:dpr = VCVTMNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule656_id1588_at_idx51521
+name:            test_rule672_id1604_at_idx52289
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule656_id1588_at_idx51521
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule672_id1604_at_idx52289
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTMNSQf:%[0-9]+]]:qpr = VCVTMNSQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule657_id1589_at_idx51569
+name:            test_rule673_id1605_at_idx52337
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16950,39 +25114,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule657_id1589_at_idx51569
+    ; SELECTED-LABEL: name: test_rule673_id1605_at_idx52337
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTNNUDf:%[0-9]+]]:dpr = VCVTNNUDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDf]]
+    ; SELECTED: [[VCVTMNUDf:%[0-9]+]]:dpr = VCVTMNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule658_id1590_at_idx51617
+name:            test_rule674_id1606_at_idx52385
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule658_id1590_at_idx51617
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule674_id1606_at_idx52385
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTMNUQf:%[0-9]+]]:qpr = VCVTMNUQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule659_id1591_at_idx51665
+name:            test_rule675_id1607_at_idx52433
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -16996,39 +25164,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule659_id1591_at_idx51665
+    ; SELECTED-LABEL: name: test_rule675_id1607_at_idx52433
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTNNSDh:%[0-9]+]]:dpr = VCVTNNSDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDh]]
+    ; SELECTED: [[VCVTMNSDh:%[0-9]+]]:dpr = VCVTMNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule660_id1592_at_idx51713
+name:            test_rule676_id1608_at_idx52481
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule660_id1592_at_idx51713
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule676_id1608_at_idx52481
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTMNSQh:%[0-9]+]]:qpr = VCVTMNSQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule661_id1593_at_idx51761
+name:            test_rule677_id1609_at_idx52529
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17042,39 +25214,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule661_id1593_at_idx51761
+    ; SELECTED-LABEL: name: test_rule677_id1609_at_idx52529
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTNNUDh:%[0-9]+]]:dpr = VCVTNNUDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDh]]
+    ; SELECTED: [[VCVTMNUDh:%[0-9]+]]:dpr = VCVTMNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule662_id1594_at_idx51809
+name:            test_rule678_id1610_at_idx52577
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule662_id1594_at_idx51809
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule678_id1610_at_idx52577
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTMNUQh:%[0-9]+]]:qpr = VCVTMNUQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule663_id1595_at_idx51857
+name:            test_rule679_id1627_at_idx52625
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17083,44 +25259,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule663_id1595_at_idx51857
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTPNSDf:%[0-9]+]]:dpr = VCVTPNSDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule664_id1596_at_idx51905
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule664_id1596_at_idx51905
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule679_id1627_at_idx52625
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTf2h:%[0-9]+]]:dpr = VCVTf2h [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2h]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule665_id1597_at_idx51953
+name:            test_rule680_id1628_at_idx52679
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17134,39 +25289,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule665_id1597_at_idx51953
+    ; SELECTED-LABEL: name: test_rule680_id1628_at_idx52679
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTPNUDf:%[0-9]+]]:dpr = VCVTPNUDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule666_id1598_at_idx52001
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule666_id1598_at_idx52001
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
+    ; SELECTED: [[VCVTh2f:%[0-9]+]]:qpr = VCVTh2f [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2f]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule667_id1599_at_idx52049
+name:            test_rule681_id1650_at_idx52733
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17180,39 +25314,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule667_id1599_at_idx52049
+    ; SELECTED-LABEL: name: test_rule681_id1650_at_idx52733
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTPNSDh:%[0-9]+]]:dpr = VCVTPNSDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDh]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VRINTNNDf:%[0-9]+]]:dpr = VRINTNNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule668_id1600_at_idx52097
+name:            test_rule682_id1651_at_idx52781
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule668_id1600_at_idx52097
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule682_id1651_at_idx52781
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTNNQf:%[0-9]+]]:qpr = VRINTNNQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule669_id1601_at_idx52145
+name:            test_rule683_id1652_at_idx52829
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17226,39 +25364,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule669_id1601_at_idx52145
+    ; SELECTED-LABEL: name: test_rule683_id1652_at_idx52829
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTPNUDh:%[0-9]+]]:dpr = VCVTPNUDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDh]]
+    ; SELECTED: [[VRINTNNDh:%[0-9]+]]:dpr = VRINTNNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule670_id1602_at_idx52193
+name:            test_rule684_id1653_at_idx52877
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule670_id1602_at_idx52193
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule684_id1653_at_idx52877
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTNNQh:%[0-9]+]]:qpr = VRINTNNQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule671_id1603_at_idx52241
+name:            test_rule685_id1654_at_idx52925
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17272,39 +25414,18 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule671_id1603_at_idx52241
+    ; SELECTED-LABEL: name: test_rule685_id1654_at_idx52925
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTMNSDf:%[0-9]+]]:dpr = VCVTMNSDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDf]]
+    ; SELECTED: [[VRINTXNDf:%[0-9]+]]:dpr = VRINTXNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule672_id1604_at_idx52289
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule672_id1604_at_idx52289
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule673_id1605_at_idx52337
+name:            test_rule686_id1655_at_idx52973
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17313,44 +25434,23 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
-
-    ; SELECTED-LABEL: name: test_rule673_id1605_at_idx52337
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTMNUDf:%[0-9]+]]:dpr = VCVTMNUDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    liveins: $q8
 
-...
----
-name:            test_rule674_id1606_at_idx52385
-alignment:       2
-legalized:       true
-regBankSelected: true
-failedISel:      true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule674_id1606_at_idx52385
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule686_id1655_at_idx52973
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTXNQf:%[0-9]+]]:qpr = VRINTXNQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule675_id1607_at_idx52433
+name:            test_rule687_id1656_at_idx53021
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17364,39 +25464,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule675_id1607_at_idx52433
+    ; SELECTED-LABEL: name: test_rule687_id1656_at_idx53021
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTMNSDh:%[0-9]+]]:dpr = VCVTMNSDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDh]]
+    ; SELECTED: [[VRINTXNDh:%[0-9]+]]:dpr = VRINTXNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule676_id1608_at_idx52481
+name:            test_rule688_id1657_at_idx53069
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule676_id1608_at_idx52481
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule688_id1657_at_idx53069
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTXNQh:%[0-9]+]]:qpr = VRINTXNQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule677_id1609_at_idx52529
+name:            test_rule689_id1658_at_idx53117
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17410,86 +25514,93 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule677_id1609_at_idx52529
+    ; SELECTED-LABEL: name: test_rule689_id1658_at_idx53117
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VCVTMNUDh:%[0-9]+]]:dpr = VCVTMNUDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDh]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED: [[VRINTANDf:%[0-9]+]]:dpr = VRINTANDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule678_id1610_at_idx52577
+name:            test_rule690_id1659_at_idx53165
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule678_id1610_at_idx52577
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+  bb.0.entry:
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule690_id1659_at_idx53165
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTANQf:%[0-9]+]]:qpr = VRINTANQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule679_id1627_at_idx52625
+name:            test_rule691_id1660_at_idx53213
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule679_id1627_at_idx52625
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule691_id1660_at_idx53213
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTANDh:%[0-9]+]]:dpr = VRINTANDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule680_id1628_at_idx52679
+name:            test_rule692_id1661_at_idx53261
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule680_id1628_at_idx52679
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), [[COPY]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule692_id1661_at_idx53261
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTANQh:%[0-9]+]]:qpr = VRINTANQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule681_id1650_at_idx52733
+name:            test_rule693_id1662_at_idx53309
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17503,39 +25614,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule681_id1650_at_idx52733
+    ; SELECTED-LABEL: name: test_rule693_id1662_at_idx53309
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTNNDf:%[0-9]+]]:dpr = VRINTNNDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDf]]
+    ; SELECTED: [[VRINTZNDf:%[0-9]+]]:dpr = VRINTZNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule682_id1651_at_idx52781
+name:            test_rule694_id1663_at_idx53357
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule682_id1651_at_idx52781
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule694_id1663_at_idx53357
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTZNQf:%[0-9]+]]:qpr = VRINTZNQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule683_id1652_at_idx52829
+name:            test_rule695_id1664_at_idx53405
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17549,39 +25664,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule683_id1652_at_idx52829
+    ; SELECTED-LABEL: name: test_rule695_id1664_at_idx53405
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTNNDh:%[0-9]+]]:dpr = VRINTNNDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDh]]
+    ; SELECTED: [[VRINTZNDh:%[0-9]+]]:dpr = VRINTZNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule684_id1653_at_idx52877
+name:            test_rule696_id1665_at_idx53453
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule684_id1653_at_idx52877
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule696_id1665_at_idx53453
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTZNQh:%[0-9]+]]:qpr = VRINTZNQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule685_id1654_at_idx52925
+name:            test_rule697_id1666_at_idx53501
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17595,39 +25714,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule685_id1654_at_idx52925
+    ; SELECTED-LABEL: name: test_rule697_id1666_at_idx53501
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTXNDf:%[0-9]+]]:dpr = VRINTXNDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDf]]
+    ; SELECTED: [[VRINTMNDf:%[0-9]+]]:dpr = VRINTMNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule686_id1655_at_idx52973
+name:            test_rule698_id1667_at_idx53549
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule686_id1655_at_idx52973
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule698_id1667_at_idx53549
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTMNQf:%[0-9]+]]:qpr = VRINTMNQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule687_id1656_at_idx53021
+name:            test_rule699_id1668_at_idx53597
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17641,39 +25764,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule687_id1656_at_idx53021
+    ; SELECTED-LABEL: name: test_rule699_id1668_at_idx53597
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTXNDh:%[0-9]+]]:dpr = VRINTXNDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDh]]
+    ; SELECTED: [[VRINTMNDh:%[0-9]+]]:dpr = VRINTMNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule688_id1657_at_idx53069
+name:            test_rule700_id1669_at_idx53645
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule688_id1657_at_idx53069
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule700_id1669_at_idx53645
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTMNQh:%[0-9]+]]:qpr = VRINTMNQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule689_id1658_at_idx53117
+name:            test_rule701_id1670_at_idx53693
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17687,39 +25814,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule689_id1658_at_idx53117
+    ; SELECTED-LABEL: name: test_rule701_id1670_at_idx53693
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTANDf:%[0-9]+]]:dpr = VRINTANDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDf]]
+    ; SELECTED: [[VRINTPNDf:%[0-9]+]]:dpr = VRINTPNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDf]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
-name:            test_rule690_id1659_at_idx53165
+name:            test_rule702_id1671_at_idx53741
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule690_id1659_at_idx53165
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule702_id1671_at_idx53741
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTPNQf:%[0-9]+]]:qpr = VRINTPNQf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNQf]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
-name:            test_rule691_id1660_at_idx53213
+name:            test_rule703_id1672_at_idx53789
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17733,39 +25864,43 @@
   bb.0.entry:
     liveins: $d16
 
-    ; SELECTED-LABEL: name: test_rule691_id1660_at_idx53213
+    ; SELECTED-LABEL: name: test_rule703_id1672_at_idx53789
     ; SELECTED: liveins: $d16
     ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTANDh:%[0-9]+]]:dpr = VRINTANDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDh]]
+    ; SELECTED: [[VRINTPNDh:%[0-9]+]]:dpr = VRINTPNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDh]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
-name:            test_rule692_id1661_at_idx53261
+name:            test_rule704_id1673_at_idx53837
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule692_id1661_at_idx53261
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule704_id1673_at_idx53837
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VRINTPNQh:%[0-9]+]]:qpr = VRINTPNQh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNQh]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
 ---
-name:            test_rule693_id1662_at_idx53309
+name:            test_rule705_id1676_at_idx53885
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -17774,387 +25909,522 @@
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8
 
-    ; SELECTED-LABEL: name: test_rule693_id1662_at_idx53309
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTZNDf:%[0-9]+]]:dpr = VRINTZNDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule705_id1676_at_idx53885
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[AESIMC:%[0-9]+]]:qpr = AESIMC [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESIMC]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule694_id1663_at_idx53357
+name:            test_rule706_id1677_at_idx53933
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule694_id1663_at_idx53357
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $q8
+
+    ; SELECTED-LABEL: name: test_rule706_id1677_at_idx53933
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[AESMC:%[0-9]+]]:qpr = AESMC [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESMC]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule695_id1664_at_idx53405
+name:            test_rule707_id1711_at_idx53981
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$lr', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule695_id1664_at_idx53405
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTZNDh:%[0-9]+]]:dpr = VRINTZNDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDh]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule707_id1711_at_idx53981
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SXTB16_:%[0-9]+]]:gprnopc = SXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule696_id1665_at_idx53453
+name:            test_rule708_id1902_at_idx54038
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule696_id1665_at_idx53453
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule708_id1902_at_idx54038
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SXTB16_:%[0-9]+]]:gprnopc = SXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule697_id1666_at_idx53501
+name:            test_rule709_id1708_at_idx54095
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$lr', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule697_id1666_at_idx53501
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTMNDf:%[0-9]+]]:dpr = VRINTMNDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule709_id1708_at_idx54095
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 4294901760
+    %0:gprb(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule710_id1897_at_idx54156
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule710_id1897_at_idx54156
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 4294901760
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[COPY]], [[t2MOVi32imm]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 4294901760
+    %0:gprb(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule711_id167_at_idx54217
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule711_id167_at_idx54217
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MVNr]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT -1
+    %0:gprb(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule698_id1667_at_idx53549
+name:            test_rule712_id715_at_idx54278
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule698_id1667_at_idx53549
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    ; SELECTED-LABEL: name: test_rule712_id715_at_idx54278
+    ; SELECTED: [[VMRS:%[0-9]+]]:gprnopc = VMRS 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMRS]]
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule699_id1668_at_idx53597
+name:            test_rule713_id716_at_idx54324
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
+  - { id: 0, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$lr', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule699_id1668_at_idx53597
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTMNDh:%[0-9]+]]:dpr = VRINTMNDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDh]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule713_id716_at_idx54324
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: VMSR [[COPY]], 14, $noreg, implicit-def $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = COPY $lr
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
+    $noreg = PATCHABLE_RET
 
 ...
 ---
-name:            test_rule700_id1669_at_idx53645
+name:            test_rule714_id254_at_idx54370
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule700_id1669_at_idx53645
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    ; SELECTED-LABEL: name: test_rule714_id254_at_idx54370
+    ; SELECTED: CLREX
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+    $noreg = PATCHABLE_RET
 
 ...
 ---
-name:            test_rule701_id1670_at_idx53693
+name:            test_rule715_id587_at_idx54398
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule715_id587_at_idx54398
+    ; SELECTED: CLREX
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule716_id74_at_idx54432
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule701_id1670_at_idx53693
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTPNDf:%[0-9]+]]:dpr = VRINTPNDf [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDf]]
-    %1:fprb(<2 x s32>) = COPY $d16
-    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
+    ; SELECTED-LABEL: name: test_rule716_id74_at_idx54432
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule702_id1671_at_idx53741
+name:            test_rule717_id411_at_idx54511
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule702_id1671_at_idx53741
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule717_id411_at_idx54511
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule703_id1672_at_idx53789
+name:            test_rule718_id412_at_idx54590
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: fprb }
-  - { id: 1, class: fprb }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule703_id1672_at_idx53789
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
-    ; SELECTED: [[VRINTPNDh:%[0-9]+]]:dpr = VRINTPNDh [[COPY]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDh]]
-    %1:fprb(<4 x s16>) = COPY $d16
-    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
+    ; SELECTED-LABEL: name: test_rule718_id412_at_idx54590
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule704_id1673_at_idx53837
+name:            test_rule719_id149_at_idx54666
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule704_id1673_at_idx53837
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule719_id149_at_idx54666
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule705_id1676_at_idx53885
+name:            test_rule720_id485_at_idx54745
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule705_id1676_at_idx53885
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule720_id485_at_idx54745
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule706_id1677_at_idx53933
+name:            test_rule721_id153_at_idx54824
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule706_id1677_at_idx53933
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule721_id153_at_idx54824
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ORRri:%[0-9]+]]:gpr = ORRri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule712_id715_at_idx54278
+name:            test_rule722_id488_at_idx54903
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule712_id715_at_idx54278
-    ; SELECTED: [[VMRS:%[0-9]+]]:gprnopc = VMRS 14, $noreg, implicit $fpscr
-    ; SELECTED: $noreg = PATCHABLE_RET [[VMRS]]
-    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
-    $noreg = PATCHABLE_RET %0(s32)
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule722_id488_at_idx54903
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ORRri:%[0-9]+]]:gpr = ORRri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule713_id716_at_idx54324
+name:            test_rule723_id474_at_idx54982
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
 liveins:
-  - { reg: '$lr', virtual-reg: '%0' }
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule713_id716_at_idx54324
+    ; SELECTED-LABEL: name: test_rule723_id474_at_idx54982
     ; SELECTED: liveins: $lr
-    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
-    ; SELECTED: VMSR [[COPY]], 14, $noreg, implicit-def $fpscr
-    ; SELECTED: $noreg = PATCHABLE_RET
-    %0:gprb(s32) = COPY $lr
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
-    $noreg = PATCHABLE_RET
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2LSLri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule714_id254_at_idx54370
+name:            test_rule724_id98_at_idx55061
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule714_id254_at_idx54370
-    ; SELECTED: CLREX
-    ; SELECTED: $noreg = PATCHABLE_RET
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
-    $noreg = PATCHABLE_RET
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule724_id98_at_idx55061
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SUB %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule715_id587_at_idx54398
+name:            test_rule725_id431_at_idx55140
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule715_id587_at_idx54398
-    ; SELECTED: CLREX
-    ; SELECTED: $noreg = PATCHABLE_RET
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
-    $noreg = PATCHABLE_RET
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule725_id431_at_idx55140
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SUB %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule716_id74_at_idx54432
+name:            test_rule726_id78_at_idx55219
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -18169,19 +26439,19 @@
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule716_id74_at_idx54432
+    ; SELECTED-LABEL: name: test_rule726_id78_at_idx55219
     ; SELECTED: liveins: $lr
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    ; SELECTED: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBri]]
     %2:gprb(s32) = COPY $lr
     %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_ADD %2, %0
+    %1:gprb(s32) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule717_id411_at_idx54511
+name:            test_rule727_id415_at_idx55298
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -18196,19 +26466,19 @@
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule717_id411_at_idx54511
+    ; SELECTED-LABEL: name: test_rule727_id415_at_idx55298
     ; SELECTED: liveins: $lr
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    ; SELECTED: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBri]]
     %2:gprb(s32) = COPY $lr
     %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_ADD %2, %0
+    %1:gprb(s32) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule718_id412_at_idx54590
+name:            test_rule728_id416_at_idx55377
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -18223,19 +26493,19 @@
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule718_id412_at_idx54590
+    ; SELECTED-LABEL: name: test_rule728_id416_at_idx55377
     ; SELECTED: liveins: $lr
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    ; SELECTED: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBri]]
     %2:gprb(s32) = COPY $lr
     %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_ADD %2, %0
+    %1:gprb(s32) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule724_id98_at_idx55061
+name:            test_rule729_id157_at_idx55453
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -18250,19 +26520,19 @@
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule724_id98_at_idx55061
+    ; SELECTED-LABEL: name: test_rule729_id157_at_idx55453
     ; SELECTED: liveins: $lr
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    ; SELECTED: [[EORri:%[0-9]+]]:gpr = EORri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORri]]
     %2:gprb(s32) = COPY $lr
     %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_SUB %0, %2
+    %1:gprb(s32) = G_XOR %2, %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
-name:            test_rule725_id431_at_idx55140
+name:            test_rule730_id491_at_idx55532
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -18277,14 +26547,14 @@
   bb.0.entry:
     liveins: $lr
 
-    ; SELECTED-LABEL: name: test_rule725_id431_at_idx55140
+    ; SELECTED-LABEL: name: test_rule730_id491_at_idx55532
     ; SELECTED: liveins: $lr
     ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
-    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
-    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    ; SELECTED: [[EORri:%[0-9]+]]:gpr = EORri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORri]]
     %2:gprb(s32) = COPY $lr
     %0:gprb(s32) = G_CONSTANT 1
-    %1:gprb(s32) = G_SUB %0, %2
+    %1:gprb(s32) = G_XOR %2, %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...
@@ -18398,28 +26668,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule734_id2175_at_idx55893
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FNEG:%[0-9]+]]:_(<4 x s32>) = G_FNEG [[DEF2]]
-    ; SELECTED: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FNEG]], [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FMA]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FNEG %4
-    %1:_(<4 x s32>) = G_FMA %0, %2, %3
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VFMSfq:%[0-9]+]]:qpr = VFMSfq [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSfq]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FNEG %4
+    %1:fprb(<4 x s32>) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -18562,6 +26837,111 @@
     %1:fprb(s32) = G_FMA %2, %3, %0
     $noreg = PATCHABLE_RET %1(s32)
 
+...
+---
+name:            test_rule739_id173_at_idx56363
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule739_id173_at_idx56363
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule740_id174_at_idx56460
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule740_id174_at_idx56460
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule741_id507_at_idx56557
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule741_id507_at_idx56557
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
 ...
 ---
 name:            test_rule742_id2569_at_idx56651
@@ -18673,28 +27053,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule745_id2572_at_idx56933
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[MUL]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_MUL %3, %4
-    %1:_(<16 x s8>) = G_ADD %0, %2
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv16i8_:%[0-9]+]]:qpr = VMLAv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_MUL %3, %4
+    %1:fprb(<16 x s8>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<16 x s8>)
 
 ...
@@ -18703,28 +27088,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule746_id2573_at_idx57027
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[MUL]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_MUL %3, %4
-    %1:_(<8 x s16>) = G_ADD %0, %2
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv8i16_:%[0-9]+]]:qpr = VMLAv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_MUL %3, %4
+    %1:fprb(<8 x s16>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -18733,28 +27123,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule747_id2574_at_idx57121
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[MUL]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_MUL %3, %4
-    %1:_(<4 x s32>) = G_ADD %0, %2
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv4i32_:%[0-9]+]]:qpr = VMLAv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_MUL %3, %4
+    %1:fprb(<4 x s32>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -18763,30 +27158,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule748_id2545_at_idx57215
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv8i16_:%[0-9]+]]:qpr = VADDWsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ADD %0, %2
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -18795,30 +27189,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule749_id2546_at_idx57297
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv4i32_:%[0-9]+]]:qpr = VADDWsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ADD %0, %2
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -18827,30 +27220,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule750_id2547_at_idx57379
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[SEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv2i64_:%[0-9]+]]:qpr = VADDWsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ADD %0, %2
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -18859,30 +27251,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule751_id2548_at_idx57461
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv8i16_:%[0-9]+]]:qpr = VADDWuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ADD %0, %2
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -18891,30 +27282,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule752_id2549_at_idx57543
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv4i32_:%[0-9]+]]:qpr = VADDWuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ADD %0, %2
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -18923,30 +27313,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule753_id2550_at_idx57625
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv2i64_:%[0-9]+]]:qpr = VADDWuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ADD %0, %2
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ADD %0, %2
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -19060,28 +27449,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule757_id868_at_idx57989
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_MUL %3, %4
-    %1:_(<16 x s8>) = G_ADD %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv16i8_:%[0-9]+]]:qpr = VMLAv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_MUL %3, %4
+    %1:fprb(<16 x s8>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<16 x s8>)
 
 ...
@@ -19090,59 +27484,174 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule758_id869_at_idx58083
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_MUL %3, %4
-    %1:_(<8 x s16>) = G_ADD %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv8i16_:%[0-9]+]]:qpr = VMLAv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_MUL %3, %4
+    %1:fprb(<8 x s16>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
 ---
-name:            test_rule759_id870_at_idx58177
+name:            test_rule759_id870_at_idx58177
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9, $q10
+
+    ; SELECTED-LABEL: name: test_rule759_id870_at_idx58177
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLAv4i32_:%[0-9]+]]:qpr = VMLAv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_MUL %3, %4
+    %1:fprb(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule760_id2483_at_idx58271
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule760_id2483_at_idx58271
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule761_id2484_at_idx58368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule761_id2484_at_idx58368
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule762_id2521_at_idx58465
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule759_id870_at_idx58177
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_MUL %3, %4
-    %1:_(<4 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule762_id2521_at_idx58465
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLA]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
 
 ...
 ---
@@ -19150,30 +27659,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule763_id764_at_idx58559
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv8i16_:%[0-9]+]]:qpr = VADDWsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ADD %2, %0
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19182,30 +27690,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule764_id765_at_idx58641
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv4i32_:%[0-9]+]]:qpr = VADDWsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ADD %2, %0
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -19214,30 +27721,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule765_id766_at_idx58723
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWsv2i64_:%[0-9]+]]:qpr = VADDWsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWsv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ADD %2, %0
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -19246,30 +27752,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule766_id767_at_idx58805
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv8i16_:%[0-9]+]]:qpr = VADDWuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_ADD %2, %0
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19278,30 +27783,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule767_id768_at_idx58887
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv4i32_:%[0-9]+]]:qpr = VADDWuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_ADD %2, %0
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -19310,30 +27814,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule768_id769_at_idx58969
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDWuv2i64_:%[0-9]+]]:qpr = VADDWuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDWuv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_ADD %2, %0
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_ADD %2, %0
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -19377,28 +27880,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule770_id2624_at_idx59145
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[FMUL]], [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FMUL %3, %4
-    %1:_(<8 x s16>) = G_FADD %0, %2
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VFMAhq:%[0-9]+]]:qpr = VFMAhq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAhq]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FMUL %3, %4
+    %1:fprb(<8 x s16>) = G_FADD %0, %2
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19442,28 +27950,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule772_id924_at_idx59333
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[DEF]], [[FMUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FMUL %3, %4
-    %1:_(<8 x s16>) = G_FADD %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VFMAhq:%[0-9]+]]:qpr = VFMAhq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAhq]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FMUL %3, %4
+    %1:fprb(<8 x s16>) = G_FADD %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19631,28 +28144,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule778_id902_at_idx59849
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[FMUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FMUL %3, %4
-    %1:_(<8 x s16>) = G_FSUB %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLShq:%[0-9]+]]:qpr = VMLShq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLShq]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FMUL %3, %4
+    %1:fprb(<8 x s16>) = G_FSUB %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19696,30 +28214,105 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule780_id928_at_idx60037
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[FMUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FMUL %3, %4
-    %1:_(<8 x s16>) = G_FSUB %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLShq:%[0-9]+]]:qpr = VMLShq [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLShq]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FMUL %3, %4
+    %1:fprb(<8 x s16>) = G_FSUB %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
+...
+---
+name:            test_rule781_id175_at_idx60131
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule781_id175_at_idx60131
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[MLS:%[0-9]+]]:gpr = MLS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLS]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule782_id508_at_idx60225
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+  - { reg: '$r1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule782_id508_at_idx60225
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[MLS:%[0-9]+]]:gpr = MLS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLS]]
+    %4:gprb(s32) = COPY $r1
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %3, %4
+    %1:gprb(s32) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
 ...
 ---
 name:            test_rule783_id893_at_idx60319
@@ -19831,28 +28424,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule786_id896_at_idx60601
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<16 x s8>)
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %3:_(<16 x s8>) = IMPLICIT_DEF
-    %4:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_MUL %3, %4
-    %1:_(<16 x s8>) = G_SUB %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLSv16i8_:%[0-9]+]]:qpr = VMLSv16i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv16i8_]]
+    %4:fprb(<16 x s8>) = COPY $q10
+    %3:fprb(<16 x s8>) = COPY $q9
+    %2:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_MUL %3, %4
+    %1:fprb(<16 x s8>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<16 x s8>)
 
 ...
@@ -19861,28 +28459,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule787_id897_at_idx60695
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %3:_(<8 x s16>) = IMPLICIT_DEF
-    %4:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_MUL %3, %4
-    %1:_(<8 x s16>) = G_SUB %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLSv8i16_:%[0-9]+]]:qpr = VMLSv8i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv8i16_]]
+    %4:fprb(<8 x s16>) = COPY $q10
+    %3:fprb(<8 x s16>) = COPY $q9
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_MUL %3, %4
+    %1:fprb(<8 x s16>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19891,28 +28494,33 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
+  - { reg: '$q9', virtual-reg: '%3' }
+  - { reg: '$q10', virtual-reg: '%4' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule788_id898_at_idx60789
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[MUL]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %4:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_MUL %3, %4
-    %1:_(<4 x s32>) = G_SUB %2, %0
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMLSv4i32_:%[0-9]+]]:qpr = VMLSv4i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv4i32_]]
+    %4:fprb(<4 x s32>) = COPY $q10
+    %3:fprb(<4 x s32>) = COPY $q9
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_MUL %3, %4
+    %1:fprb(<4 x s32>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -19921,30 +28529,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule789_id947_at_idx60883
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWsv8i16_:%[0-9]+]]:qpr = VSUBWsv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWsv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_SUB %2, %0
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -19953,30 +28560,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule790_id948_at_idx60965
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWsv4i32_:%[0-9]+]]:qpr = VSUBWsv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWsv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_SUB %2, %0
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -19985,30 +28591,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule791_id949_at_idx61047
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[SEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWsv2i64_:%[0-9]+]]:qpr = VSUBWsv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWsv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_SUB %2, %0
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -20017,30 +28622,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule792_id950_at_idx61129
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWuv8i16_:%[0-9]+]]:qpr = VSUBWuv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWuv8i16_]]
     %3:fprb(<8 x s8>) = COPY $d16
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:_(<8 x s16>) = G_SUB %2, %0
+    %2:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fprb(<8 x s16>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<8 x s16>)
 
 ...
@@ -20049,30 +28653,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule793_id951_at_idx61211
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWuv4i32_:%[0-9]+]]:qpr = VSUBWuv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWuv4i32_]]
     %3:fprb(<4 x s16>) = COPY $d16
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:_(<4 x s32>) = G_SUB %2, %0
+    %2:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fprb(<4 x s32>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
 ...
@@ -20081,30 +28684,29 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
   - { id: 3, class: fprb }
 liveins:
+  - { reg: '$q8', virtual-reg: '%2' }
   - { reg: '$d16', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
-    liveins: $d16
+    liveins: $q8, $d16
 
     ; SELECTED-LABEL: name: test_rule794_id952_at_idx61293
-    ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[ZEXT]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    ; SELECTED: liveins: $q8, $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBWuv2i64_:%[0-9]+]]:qpr = VSUBWuv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBWuv2i64_]]
     %3:fprb(<2 x s32>) = COPY $d16
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:_(<2 x s64>) = G_SUB %2, %0
+    %2:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fprb(<2 x s64>) = G_SUB %2, %0
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
 ...
@@ -20239,6 +28841,99 @@
     %1:fprb(s32) = G_FNEG %0
     $noreg = PATCHABLE_RET %1(s32)
 
+...
+---
+name:            test_rule799_id632_at_idx61727
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule799_id632_at_idx61727
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VNMULH:%[0-9]+]]:hpr = VNMULH [[DEF]], [[DEF1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULH]]
+    %2:fprb(s16) = IMPLICIT_DEF
+    %3:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FMUL %2, %3
+    %1:fprb(s16) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule800_id408_at_idx61809
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule800_id408_at_idx61809
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MOVi]]
+    %0:gprb(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule801_id59_at_idx61856
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule801_id59_at_idx61856
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MOVi]]
+    %0:gprb(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule802_id60_at_idx61903
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule802_id60_at_idx61903
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MOVi]]
+    %0:gprb(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule803_id409_at_idx61947
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule803_id409_at_idx61947
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MOVi]]
+    %0:gprb(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule804_id2081_at_idx61991
@@ -20344,25 +29039,31 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+  - { reg: '$q10', virtual-reg: '%3' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9, $q10
+
     ; SELECTED-LABEL: name: test_rule807_id2173_at_idx62213
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[DEF]], [[DEF1]], [[DEF2]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FMA]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %3:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FMA %1, %2, %3
+    ; SELECTED: liveins: $q8, $q9, $q10
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q10
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY2:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VFMAfq:%[0-9]+]]:qpr = VFMAfq [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAfq]]
+    %3:fprb(<4 x s32>) = COPY $q10
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FMA %1, %2, %3
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -20516,22 +29217,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule813_id749_at_idx62603
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_ADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDv16i8_:%[0-9]+]]:qpr = VADDv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_ADD %1, %2
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -20540,22 +29246,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule814_id750_at_idx62665
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_ADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDv8i16_:%[0-9]+]]:qpr = VADDv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_ADD %1, %2
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -20564,22 +29275,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule815_id751_at_idx62727
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_ADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDv4i32_:%[0-9]+]]:qpr = VADDv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_ADD %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -20617,22 +29333,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule817_id753_at_idx62851
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_ADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDv2i64_:%[0-9]+]]:qpr = VADDv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_ADD %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -20664,6 +29385,64 @@
     %0:gprb(s32) = G_ADD %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule819_id150_at_idx62978
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule819_id150_at_idx62978
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule820_id486_at_idx63043
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule820_id486_at_idx63043
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ANDrr:%[0-9]+]]:gpr = ANDrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule821_id1090_at_idx63108
@@ -20699,24 +29478,58 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule822_id1091_at_idx63170
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_AND %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VANDq:%[0-9]+]]:qpr = VANDq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VANDq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_AND %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
+...
+---
+name:            test_rule823_id479_at_idx63232
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule823_id479_at_idx63232
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2ASRrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule824_id618_at_idx63297
@@ -20775,6 +29588,29 @@
     %0:fprb(s32) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule826_id620_at_idx63421
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule826_id620_at_idx63421
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VADDH:%[0-9]+]]:hpr = VADDH [[DEF]], [[DEF1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDH]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %2:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule827_id754_at_idx63483
@@ -20810,22 +29646,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule828_id755_at_idx63545
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDfq:%[0-9]+]]:qpr = VADDfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -20863,22 +29704,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule830_id757_at_idx63669
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FADD %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VADDhq:%[0-9]+]]:qpr = VADDhq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDhq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -20939,6 +29785,29 @@
     %0:fprb(s32) = G_FDIV %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule833_id626_at_idx63855
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule833_id626_at_idx63855
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VDIVH:%[0-9]+]]:hpr = VDIVH [[DEF]], [[DEF1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVH]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %2:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule834_id627_at_idx63917
@@ -20997,6 +29866,29 @@
     %0:fprb(s32) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule836_id629_at_idx64041
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule836_id629_at_idx64041
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VMULH:%[0-9]+]]:hpr = VMULH [[DEF]], [[DEF1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULH]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %2:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule837_id821_at_idx64103
@@ -21032,22 +29924,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule838_id822_at_idx64165
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FMUL %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULfq:%[0-9]+]]:qpr = VMULfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -21085,22 +29982,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule840_id824_at_idx64289
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FMUL %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULhq:%[0-9]+]]:qpr = VMULhq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULhq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -21161,6 +30063,29 @@
     %0:fprb(s32) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule843_id623_at_idx64475
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule843_id623_at_idx64475
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VSUBH:%[0-9]+]]:hpr = VSUBH [[DEF]], [[DEF1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBH]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %2:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule844_id937_at_idx64537
@@ -21196,22 +30121,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule845_id938_at_idx64599
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FSUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBfq:%[0-9]+]]:qpr = VSUBfq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBfq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -21249,24 +30179,58 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule847_id940_at_idx64723
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FSUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBhq:%[0-9]+]]:qpr = VSUBhq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBhq]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
+...
+---
+name:            test_rule848_id477_at_idx64785
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule848_id477_at_idx64785
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2LSRrr:%[0-9]+]]:rgpr = t2LSRrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2LSRrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule849_id171_at_idx64850
@@ -21447,71 +30411,144 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule855_id816_at_idx65228
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_MUL %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULv16i8_:%[0-9]+]]:qpr = VMULv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_MUL %1, %2
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
 ---
-name:            test_rule856_id817_at_idx65290
+name:            test_rule856_id817_at_idx65290
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule856_id817_at_idx65290
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULv8i16_:%[0-9]+]]:qpr = VMULv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule857_id818_at_idx65352
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q8, $q9
+
+    ; SELECTED-LABEL: name: test_rule857_id818_at_idx65352
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMULv4i32_:%[0-9]+]]:qpr = VMULv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule858_id154_at_idx65414
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule856_id817_at_idx65290
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule858_id154_at_idx65414
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
-name:            test_rule857_id818_at_idx65352
+name:            test_rule859_id489_at_idx65479
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
-    ; SELECTED-LABEL: name: test_rule857_id818_at_idx65352
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule859_id489_at_idx65479
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ORRrr:%[0-9]+]]:gpr = ORRrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
 
 ...
 ---
@@ -21548,22 +30585,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule861_id1095_at_idx65606
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_OR %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VORRq:%[0-9]+]]:qpr = VORRq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VORRq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_OR %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -21624,6 +30666,93 @@
     %0:gprb(s32) = G_SDIV %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule864_id475_at_idx65792
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule864_id475_at_idx65792
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:rgpr = COPY $lr
+    ; SELECTED: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2LSLrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule865_id79_at_idx65857
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule865_id79_at_idx65857
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule866_id417_at_idx65922
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule866_id417_at_idx65922
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule867_id929_at_idx65987
@@ -21717,22 +30846,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule870_id932_at_idx66173
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<16 x s8>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %2:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_SUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBv16i8_:%[0-9]+]]:qpr = VSUBv16i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv16i8_]]
+    %2:fprb(<16 x s8>) = COPY $q9
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_SUB %1, %2
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -21741,22 +30875,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule871_id933_at_idx66235
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %2:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_SUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBv8i16_:%[0-9]+]]:qpr = VSUBv8i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv8i16_]]
+    %2:fprb(<8 x s16>) = COPY $q9
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_SUB %1, %2
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -21765,22 +30904,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule872_id934_at_idx66297
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_SUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBv4i32_:%[0-9]+]]:qpr = VSUBv4i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv4i32_]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_SUB %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -21818,22 +30962,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule874_id936_at_idx66421
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %2:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_SUB %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VSUBv2i64_:%[0-9]+]]:qpr = VSUBv2i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv2i64_]]
+    %2:fprb(<2 x s64>) = COPY $q9
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_SUB %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -21894,6 +31043,64 @@
     %0:gprb(s32) = G_UDIV %1, %2
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule877_id158_at_idx66607
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule877_id158_at_idx66607
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[EORrr:%[0-9]+]]:gpr = EORrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule878_id492_at_idx66672
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule878_id492_at_idx66672
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[EORrr:%[0-9]+]]:gpr = EORrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule879_id1092_at_idx66737
@@ -21929,22 +31136,27 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
+  - { reg: '$q9', virtual-reg: '%2' }
 body:             |
   bb.0.entry:
+    liveins: $q8, $q9
+
     ; SELECTED-LABEL: name: test_rule880_id1093_at_idx66799
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[DEF]], [[DEF1]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %2:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_XOR %1, %2
+    ; SELECTED: liveins: $q8, $q9
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q9
+    ; SELECTED: [[COPY1:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VEORq:%[0-9]+]]:qpr = VEORq [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VEORq]]
+    %2:fprb(<4 x s32>) = COPY $q9
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_XOR %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -21953,10 +31165,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -21966,11 +31177,11 @@
 
     ; SELECTED-LABEL: name: test_rule881_id2253_at_idx66861
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<8 x s16>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv8i16_:%[0-9]+]]:qpr = VMOVLuv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv8i16_]]
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -21979,10 +31190,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -21992,11 +31202,11 @@
 
     ; SELECTED-LABEL: name: test_rule882_id2254_at_idx66909
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv4i32_:%[0-9]+]]:qpr = VMOVLuv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv4i32_]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:_(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -22005,10 +31215,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -22018,11 +31227,11 @@
 
     ; SELECTED-LABEL: name: test_rule883_id2255_at_idx66957
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv2i64_:%[0-9]+]]:qpr = VMOVLuv2i64 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv2i64_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -22417,19 +31626,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule916_id2325_at_idx68477
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -22438,19 +31650,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule917_id2326_at_idx68523
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -22459,19 +31674,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule918_id2327_at_idx68569
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -22480,19 +31698,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule919_id2328_at_idx68615
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -22501,19 +31722,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule921_id2330_at_idx68705
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -22522,19 +31746,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule922_id2331_at_idx68751
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -22543,19 +31770,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule923_id2332_at_idx68797
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -22564,19 +31794,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule925_id2334_at_idx68889
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -22585,19 +31818,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule926_id2335_at_idx68933
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -22606,19 +31842,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule927_id2336_at_idx68979
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -22627,19 +31866,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule928_id2337_at_idx69025
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -22648,19 +31890,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule931_id2340_at_idx69163
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -22669,19 +31914,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule932_id2341_at_idx69209
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -22690,19 +31938,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule933_id2342_at_idx69255
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -22999,19 +32250,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule972_id2381_at_idx71149
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -23020,19 +32274,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule973_id2382_at_idx71199
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -23041,19 +32298,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule974_id2383_at_idx71249
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<2 x s64>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -23062,19 +32322,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule976_id2385_at_idx71349
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23083,19 +32346,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule977_id2386_at_idx71399
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23104,19 +32370,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule978_id2387_at_idx71449
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23125,19 +32394,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule980_id2389_at_idx71549
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23146,19 +32418,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule981_id2390_at_idx71599
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23167,19 +32442,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule982_id2391_at_idx71649
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<16 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
-    %1:_(<16 x s8>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<16 x s8>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_BITCAST %1(<16 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23188,19 +32466,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule985_id2394_at_idx71799
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s64>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -23209,19 +32490,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule986_id2395_at_idx71849
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -23230,19 +32514,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule987_id2396_at_idx71899
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<16 x s8>) = G_BITCAST %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<16 x s8>)
 
 ...
@@ -23320,6 +32607,23 @@
     %0:gprb(s32) = G_BSWAP %1
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1001_id595_at_idx72599
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1001_id595_at_idx72599
+    ; SELECTED: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[t2MOVi]]
+    %0:gprb(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule1002_id661_at_idx72634
@@ -23370,6 +32674,26 @@
     %0:fprb(s32) = G_FNEG %1
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1004_id663_at_idx72734
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1004_id663_at_idx72734
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VNEGH:%[0-9]+]]:hpr = VNEGH [[DEF]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGH]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %0:fprb(s16) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule1005_id1489_at_idx72784
@@ -23401,19 +32725,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1006_id1490_at_idx72834
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FNEG:%[0-9]+]]:_(<4 x s32>) = G_FNEG [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FNEG %1
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VNEGf32q:%[0-9]+]]:qpr = VNEGf32q [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGf32q]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FNEG %1
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23447,19 +32775,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1008_id1492_at_idx72934
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FNEG:%[0-9]+]]:_(<8 x s16>) = G_FNEG [[DEF]]
-    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FNEG %1
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VNEGhq:%[0-9]+]]:qpr = VNEGhq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGhq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FNEG %1
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23518,19 +32850,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1013_id1567_at_idx73216
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FPTOSI:%[0-9]+]]:_(<4 x s32>) = G_FPTOSI [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOSI]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTf2sq:%[0-9]+]]:qpr = VCVTf2sq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2sq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23564,19 +32900,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1015_id1575_at_idx73316
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FPTOSI:%[0-9]+]]:_(<8 x s16>) = G_FPTOSI [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOSI]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTh2sq:%[0-9]+]]:qpr = VCVTh2sq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2sq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23631,6 +32971,27 @@
     %0:gprb(s32) = G_FPTOSI %1(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1018_id2057_at_idx73502
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1018_id2057_at_idx73502
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VTOSIZH:%[0-9]+]]:spr = VTOSIZH [[DEF]], 14, $noreg
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY [[VTOSIZH]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %0:gprb(s32) = G_FPTOSI %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule1019_id1564_at_idx73570
@@ -23662,19 +33023,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1020_id1568_at_idx73620
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[FPTOUI:%[0-9]+]]:_(<4 x s32>) = G_FPTOUI [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOUI]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTf2uq:%[0-9]+]]:qpr = VCVTf2uq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2uq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23708,19 +33073,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1022_id1576_at_idx73720
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[FPTOUI:%[0-9]+]]:_(<8 x s16>) = G_FPTOUI [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOUI]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTh2uq:%[0-9]+]]:qpr = VCVTh2uq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2uq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23775,6 +33144,27 @@
     %0:gprb(s32) = G_FPTOUI %1(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1025_id2062_at_idx73906
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1025_id2062_at_idx73906
+    ; SELECTED: [[DEF:%[0-9]+]]:hpr = IMPLICIT_DEF
+    ; SELECTED: [[VTOUIZH:%[0-9]+]]:spr = VTOUIZH [[DEF]], 14, $noreg
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY [[VTOUIZH]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s16) = IMPLICIT_DEF
+    %0:gprb(s32) = G_FPTOUI %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
 ...
 ---
 name:            test_rule1026_id660_at_idx73974
@@ -23800,16 +33190,67 @@
     %0:fprb(s32) = G_FPTRUNC %1(s64)
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1027_id2033_at_idx74024
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1027_id2033_at_idx74024
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:hpr = COPY [[VCVTBSH]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s16) = G_FPTRUNC %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1028_id2037_at_idx74092
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1028_id2037_at_idx74092
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTBDH:%[0-9]+]]:spr = VCVTBDH [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:hpr = COPY [[VCVTBDH]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s16) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule1029_id1557_at_idx74160
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -23819,11 +33260,11 @@
 
     ; SELECTED-LABEL: name: test_rule1029_id1557_at_idx74160
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<8 x s16>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLsv8i16_:%[0-9]+]]:qpr = VMOVLsv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLsv8i16_]]
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_SEXT %1(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -23832,10 +33273,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -23845,11 +33285,11 @@
 
     ; SELECTED-LABEL: name: test_rule1030_id1558_at_idx74210
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLsv4i32_:%[0-9]+]]:qpr = VMOVLsv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLsv4i32_]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:_(<4 x s32>) = G_SEXT %1(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_SEXT %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23858,10 +33298,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -23871,11 +33310,11 @@
 
     ; SELECTED-LABEL: name: test_rule1031_id1559_at_idx74260
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLsv2i64_:%[0-9]+]]:qpr = VMOVLsv2i64 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLsv2i64_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_SEXT %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
@@ -23909,19 +33348,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1033_id1569_at_idx74360
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[SITOFP:%[0-9]+]]:_(<4 x s32>) = G_SITOFP [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[SITOFP]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTs2fq:%[0-9]+]]:qpr = VCVTs2fq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTs2fq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_SITOFP %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -23955,19 +33398,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1035_id1577_at_idx74460
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[SITOFP:%[0-9]+]]:_(<8 x s16>) = G_SITOFP [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[SITOFP]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTs2hq:%[0-9]+]]:qpr = VCVTs2hq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTs2hq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_SITOFP %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -24022,24 +33469,54 @@
     %0:fprb(s32) = G_SITOFP %1(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1038_id2047_at_idx74642
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1038_id2047_at_idx74642
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VSITOH:%[0-9]+]]:hpr = VSITOH [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSITOH]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s16) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule1039_id1545_at_idx74708
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1039_id1545_at_idx74708
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<8 x s8>) = G_TRUNC [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<8 x s8>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMOVNv8i8_:%[0-9]+]]:dpr = VMOVNv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVNv8i8_]]
+    %1:fprb(<8 x s16>) = COPY $q8
     %0:fprb(<8 x s8>) = G_TRUNC %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s8>)
 
@@ -24049,18 +33526,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1040_id1546_at_idx74758
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<4 x s16>) = G_TRUNC [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<4 x s16>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMOVNv4i16_:%[0-9]+]]:dpr = VMOVNv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVNv4i16_]]
+    %1:fprb(<4 x s32>) = COPY $q8
     %0:fprb(<4 x s16>) = G_TRUNC %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
@@ -24070,18 +33551,22 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fprb }
-  - { id: 1, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1041_id1547_at_idx74808
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
-    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<2 x s32>) = G_TRUNC [[DEF]](<2 x s64>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<2 x s32>)
-    %1:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VMOVNv2i32_:%[0-9]+]]:dpr = VMOVNv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVNv2i32_]]
+    %1:fprb(<2 x s64>) = COPY $q8
     %0:fprb(<2 x s32>) = G_TRUNC %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
@@ -24116,19 +33601,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1043_id1570_at_idx74908
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
-    ; SELECTED: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[DEF]](<4 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[UITOFP]](<4 x s32>)
-    %1:_(<4 x s32>) = IMPLICIT_DEF
-    %0:_(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTu2fq:%[0-9]+]]:qpr = VCVTu2fq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTu2fq]]
+    %1:fprb(<4 x s32>) = COPY $q8
+    %0:fprb(<4 x s32>) = G_UITOFP %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -24162,19 +33651,23 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$q8', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
+    liveins: $q8
+
     ; SELECTED-LABEL: name: test_rule1045_id1578_at_idx75008
-    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
-    ; SELECTED: [[UITOFP:%[0-9]+]]:_(<8 x s16>) = G_UITOFP [[DEF]](<8 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[UITOFP]](<8 x s16>)
-    %1:_(<8 x s16>) = IMPLICIT_DEF
-    %0:_(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+    ; SELECTED: liveins: $q8
+    ; SELECTED: [[COPY:%[0-9]+]]:qpr = COPY $q8
+    ; SELECTED: [[VCVTu2hq:%[0-9]+]]:qpr = VCVTu2hq [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTu2hq]]
+    %1:fprb(<8 x s16>) = COPY $q8
+    %0:fprb(<8 x s16>) = G_UITOFP %1(<8 x s16>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -24229,16 +33722,41 @@
     %0:fprb(s32) = G_UITOFP %1(s32)
     $noreg = PATCHABLE_RET %0(s32)
 
+...
+---
+name:            test_rule1048_id2052_at_idx75190
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1048_id2052_at_idx75190
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VUITOH:%[0-9]+]]:hpr = VUITOH [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VUITOH]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s16) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
 ...
 ---
 name:            test_rule1049_id1560_at_idx75256
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -24248,11 +33766,11 @@
 
     ; SELECTED-LABEL: name: test_rule1049_id1560_at_idx75256
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv8i16_:%[0-9]+]]:qpr = VMOVLuv8i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv8i16_]]
     %1:fprb(<8 x s8>) = COPY $d16
-    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
     $noreg = PATCHABLE_RET %0(<8 x s16>)
 
 ...
@@ -24261,10 +33779,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -24274,11 +33791,11 @@
 
     ; SELECTED-LABEL: name: test_rule1050_id1561_at_idx75306
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv4i32_:%[0-9]+]]:qpr = VMOVLuv4i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv4i32_]]
     %1:fprb(<4 x s16>) = COPY $d16
-    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
@@ -24287,10 +33804,9 @@
 alignment:       2
 legalized:       true
 regBankSelected: true
-failedISel:      true
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: _ }
+  - { id: 0, class: fprb }
   - { id: 1, class: fprb }
 liveins:
   - { reg: '$d16', virtual-reg: '%1' }
@@ -24300,11 +33816,11 @@
 
     ; SELECTED-LABEL: name: test_rule1051_id1562_at_idx75356
     ; SELECTED: liveins: $d16
-    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
-    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
-    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMOVLuv2i64_:%[0-9]+]]:qpr = VMOVLuv2i64 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVLuv2i64_]]
     %1:fprb(<2 x s32>) = COPY $d16
-    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir
+++ test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir
@@ -1,6 +1,6 @@
 # NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
 # RUN: llc -mtriple arm-- -run-pass instruction-select-testgen \
-# RUN:     -testgen-exclude-rules=2,3,18,19,20,21,22,23,24,25,26,27,28,29,30,39,40,41,42,47,48,49,50,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,79,80,93,94,95,96,98,99,100,101,102,103,104,105,106,107,108,109,122,123,125,126,127,128,184,185,186,187,190,191,212,219,220,221,222,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,592,593,594,595,707,708,709,710,711,719,720,721,722,723,726,727,728,729,730,739,740,741,760,761,762,781,782,799,800,801,802,803,819,820,823,826,833,836,843,848,858,859,864,865,866,877,878,1001,1004,1010,1011,1018,1025,1027,1028,1038,1048 \
+# RUN:     -testgen-exclude-rules=1010,1011 \
 # RUN:     -testgen-set-all-features -verify-machineinstrs -simplify-mir %s \
 # RUN:     -o - 2>&1 | FileCheck %s --check-prefix=TESTGEND
 #
@@ -90,6 +90,80 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule2
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:         - { id: 9, class: gprb }
+# TESTGEND:         - { id: 10, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%9' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %9:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %10:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 24
+# TESTGEND:           %3:gprb(s32) = G_LSHR %9, %10
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %8
+# TESTGEND:           %1:gprb(s32) = G_SHL %9, %7
+# TESTGEND:           %0:gprb(s32) = G_ASHR %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule3
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:         - { id: 9, class: gprb }
+# TESTGEND:         - { id: 10, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%9' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %9:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %10:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 24
+# TESTGEND:           %3:gprb(s32) = G_LSHR %9, %10
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %8
+# TESTGEND:           %1:gprb(s32) = G_SHL %9, %7
+# TESTGEND:           %0:gprb(s32) = G_ASHR %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule4
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -458,7 +532,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule31
+# TESTGEND-LABEL: name:            test_rule18
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -467,20 +541,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ASHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule32
+# TESTGEND-LABEL: name:            test_rule19
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -489,20 +576,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ASHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule33
+# TESTGEND-LABEL: name:            test_rule20
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -511,20 +611,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_LSHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule34
+# TESTGEND-LABEL: name:            test_rule21
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -533,20 +646,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_LSHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule35
+# TESTGEND-LABEL: name:            test_rule22
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -555,20 +681,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SHL %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule36
+# TESTGEND-LABEL: name:            test_rule23
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -577,20 +716,33 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%6' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%7' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %7:gprb(s32) = COPY $r0
+# TESTGEND:           %6:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %3:gprb(s32) = G_AND %7, %8
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SHL %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule37
+# TESTGEND-LABEL: name:            test_rule24
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -598,19 +750,34 @@
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %8:gprb(s32) = COPY $r0
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_ASHR %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule38
+# TESTGEND-LABEL: name:            test_rule25
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -618,19 +785,34 @@
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %8:gprb(s32) = COPY $r0
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_ASHR %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule43
+# TESTGEND-LABEL: name:            test_rule26
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -642,24 +824,30 @@
 # TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
+# TESTGEND:           %8:gprb(s32) = COPY $r0
 # TESTGEND:           %5:gprb(s32) = COPY $lr
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
 # TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %2:gprb(s32) = G_LSHR %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule44
+# TESTGEND-LABEL: name:            test_rule27
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -671,24 +859,30 @@
 # TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
+# TESTGEND:           %8:gprb(s32) = COPY $r0
 # TESTGEND:           %5:gprb(s32) = COPY $lr
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
 # TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %2:gprb(s32) = G_LSHR %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule45
+# TESTGEND-LABEL: name:            test_rule28
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -700,24 +894,30 @@
 # TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
+# TESTGEND:           %8:gprb(s32) = COPY $r0
 # TESTGEND:           %5:gprb(s32) = COPY $lr
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
 # TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %2:gprb(s32) = G_SHL %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule46
+# TESTGEND-LABEL: name:            test_rule29
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -729,24 +929,30 @@
 # TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%8' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
+# TESTGEND:           %8:gprb(s32) = COPY $r0
 # TESTGEND:           %5:gprb(s32) = COPY $lr
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
 # TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %2:gprb(s32) = G_SHL %8, %3
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule51
+# TESTGEND-LABEL: name:            test_rule30
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -755,29 +961,21 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
-# TESTGEND:         - { id: 5, class: gprb }
-# TESTGEND:         - { id: 6, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
-# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
-# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtab16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule52
+# TESTGEND-LABEL: name:            test_rule31
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -786,29 +984,20 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
-# TESTGEND:         - { id: 5, class: gprb }
-# TESTGEND:         - { id: 6, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %5:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
-# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
-# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule69
+# TESTGEND-LABEL: name:            test_rule32
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -817,26 +1006,20 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule70
+# TESTGEND-LABEL: name:            test_rule33
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -845,26 +1028,20 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule71
+# TESTGEND-LABEL: name:            test_rule34
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -873,26 +1050,20 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule72
+# TESTGEND-LABEL: name:            test_rule35
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -901,286 +1072,5467 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
-# TESTGEND:         - { id: 4, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:gprb(s32) = COPY $r0
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule73
+# TESTGEND-LABEL: name:            test_rule36
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule74
+# TESTGEND-LABEL: name:            test_rule37
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule75
+# TESTGEND-LABEL: name:            test_rule38
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule76
+# TESTGEND-LABEL: name:            test_rule39
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %5(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule77
+# TESTGEND-LABEL: name:            test_rule40
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: _ }
-# TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
-#
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %5(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule78
+# TESTGEND-LABEL: name:            test_rule41
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: _ }
-# TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
-#
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %4:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %5(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule81
+# TESTGEND-LABEL: name:            test_rule42
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %5:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mrc2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %5(s32)
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule43
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule44
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule45
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule46
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule47
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%7' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %7:gprb(s32) = COPY $r1
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %2:gprb(s32) = G_ASHR %7, %8
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           %3:gprb(s32) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule48
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%7' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %7:gprb(s32) = COPY $r1
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %2:gprb(s32) = G_ASHR %7, %8
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           %3:gprb(s32) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule49
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%7' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %7:gprb(s32) = COPY $r1
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %2:gprb(s32) = G_ASHR %7, %8
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           %3:gprb(s32) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule50
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%7' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %7:gprb(s32) = COPY $r1
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %2:gprb(s32) = G_ASHR %7, %8
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           %3:gprb(s32) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule51
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
+# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule52
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
+# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule53
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %1:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule54
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %1:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule55
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %1:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule56
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %1:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule57
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ASHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule58
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ASHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule59
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_LSHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule60
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_LSHR %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule61
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SHL %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule62
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %6:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SHL %6, %2
+# TESTGEND:           %0:gprb(s32) = G_AND %4, %5
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule63
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_ASHR %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule64
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_ASHR %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule65
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_LSHR %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule66
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_LSHR %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule67
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_SHL %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule68
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %4:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %2:gprb(s32) = G_AND %5, %6
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_SHL %4, %1
+# TESTGEND:           %3:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule69
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule70
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule71
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule72
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule73
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule74
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule75
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule76
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule77
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $q8
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule78
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $q8
+#
+# TESTGEND:           %4:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule79
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %2(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %0(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule80
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %2(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %0(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule81
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule82
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule83
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule84
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule85
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule86
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule87
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule88
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule89
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule90
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule91
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule92
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule93
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule94
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule95
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule96
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %3(s32), %3(s32)
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule97
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule98
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_AND %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule99
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_AND %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule100
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_AND %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule101
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_AND %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule102
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule103
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule104
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule105
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_AND %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule106
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule107
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule108
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %4, %1
+# TESTGEND:           %2:gprb(s32) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule109
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %4
+# TESTGEND:           %2:gprb(s32) = G_OR %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule110
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule111
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule112
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule113
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule114
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule115
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule116
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule117
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule118
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule119
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule120
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule121
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule122
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule123
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule124
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 249
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule125
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule126
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat16), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule127
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule128
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usat16), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule129
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule130
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule131
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule132
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule133
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule134
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule135
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule136
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule137
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule138
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule139
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule140
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule141
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule142
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule143
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule144
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule145
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule146
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule147
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule148
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule149
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule150
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule151
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule152
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule153
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule154
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule155
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule156
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule157
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule158
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule159
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule160
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule161
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule162
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule163
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule164
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule165
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule166
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule167
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule168
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule169
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule170
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule171
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule172
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule173
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule174
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule175
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule176
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule177
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule178
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule179
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule180
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule181
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule182
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule183
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule184
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule185
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule186
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule187
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule188
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule189
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule190
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule191
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule192
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule193
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule194
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule195
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule196
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule197
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule198
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FNEG %4
+# TESTGEND:           %2:fprb(s64) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule199
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FNEG %4
+# TESTGEND:           %2:fprb(s32) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule200
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:fprb(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule201
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:fprb(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule202
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:fprb(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule203
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule204
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule205
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule206
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:fprb(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule207
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:fprb(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule208
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:fprb(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule209
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule210
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule211
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule212
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule213
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FMA %1, %3, %4
+# TESTGEND:           %2:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule214
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FMA %1, %3, %4
+# TESTGEND:           %2:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule215
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FMA %3, %1, %4
+# TESTGEND:           %2:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule216
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FMA %3, %1, %4
+# TESTGEND:           %2:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule217
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule218
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule219
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlad), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule220
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smladx), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule221
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsd), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule222
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsdx), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule223
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule224
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule225
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule226
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule227
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule228
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlad), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule229
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smladx), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule230
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsd), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule231
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlsdx), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule232
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule82
+# TESTGEND-LABEL: name:            test_rule233
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0, $r1
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule83
+# TESTGEND-LABEL: name:            test_rule234
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule235
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule236
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule237
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule238
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule239
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlabt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule240
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule241
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlatt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule242
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawb), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule243
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smlawt), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule84
+# TESTGEND-LABEL: name:            test_rule244
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule85
+# TESTGEND-LABEL: name:            test_rule245
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -1190,25 +6542,23 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17, $d18
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule86
+# TESTGEND-LABEL: name:            test_rule246
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -1218,183 +6568,176 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17, $d18
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule87
+# TESTGEND-LABEL: name:            test_rule248
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d18
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule88
+# TESTGEND-LABEL: name:            test_rule249
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule89
+# TESTGEND-LABEL: name:            test_rule250
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9, $q10
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule90
+# TESTGEND-LABEL: name:            test_rule251
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9, $q10
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule91
+# TESTGEND-LABEL: name:            test_rule253
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9, $q10
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %3:fprb(<2 x s64>) = COPY $q10
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule92
+# TESTGEND-LABEL: name:            test_rule254
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule97
+# TESTGEND-LABEL: name:            test_rule255
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -1403,935 +6746,1010 @@
 # TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
-# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule110
+# TESTGEND-LABEL: name:            test_rule256
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule111
+# TESTGEND-LABEL: name:            test_rule257
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule112
+# TESTGEND-LABEL: name:            test_rule258
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule113
+# TESTGEND-LABEL: name:            test_rule259
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule114
+# TESTGEND-LABEL: name:            test_rule260
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule115
+# TESTGEND-LABEL: name:            test_rule261
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %3
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule116
+# TESTGEND-LABEL: name:            test_rule262
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule117
+# TESTGEND-LABEL: name:            test_rule263
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule118
+# TESTGEND-LABEL: name:            test_rule264
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule119
+# TESTGEND-LABEL: name:            test_rule265
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule120
+# TESTGEND-LABEL: name:            test_rule266
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule121
+# TESTGEND-LABEL: name:            test_rule267
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %3, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule124
+# TESTGEND-LABEL: name:            test_rule268
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 249
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule129
+# TESTGEND-LABEL: name:            test_rule269
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule130
+# TESTGEND-LABEL: name:            test_rule270
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule131
+# TESTGEND-LABEL: name:            test_rule271
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule132
+# TESTGEND-LABEL: name:            test_rule272
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule133
+# TESTGEND-LABEL: name:            test_rule273
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule134
+# TESTGEND-LABEL: name:            test_rule274
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule135
+# TESTGEND-LABEL: name:            test_rule275
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule136
+# TESTGEND-LABEL: name:            test_rule276
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule137
+# TESTGEND-LABEL: name:            test_rule277
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule138
+# TESTGEND-LABEL: name:            test_rule278
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule139
+# TESTGEND-LABEL: name:            test_rule279
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule140
+# TESTGEND-LABEL: name:            test_rule280
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usad8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule141
+# TESTGEND-LABEL: name:            test_rule281
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32b), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule142
+# TESTGEND-LABEL: name:            test_rule282
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule143
+# TESTGEND-LABEL: name:            test_rule283
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32h), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule144
+# TESTGEND-LABEL: name:            test_rule284
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32ch), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule145
+# TESTGEND-LABEL: name:            test_rule285
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32w), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule146
+# TESTGEND-LABEL: name:            test_rule286
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cw), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule147
+# TESTGEND-LABEL: name:            test_rule287
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule148
+# TESTGEND-LABEL: name:            test_rule288
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule149
+# TESTGEND-LABEL: name:            test_rule289
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule150
+# TESTGEND-LABEL: name:            test_rule290
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule151
+# TESTGEND-LABEL: name:            test_rule291
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule152
+# TESTGEND-LABEL: name:            test_rule292
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule153
+# TESTGEND-LABEL: name:            test_rule293
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule154
+# TESTGEND-LABEL: name:            test_rule294
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule155
+# TESTGEND-LABEL: name:            test_rule295
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule156
+# TESTGEND-LABEL: name:            test_rule296
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule157
+# TESTGEND-LABEL: name:            test_rule297
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule158
+# TESTGEND-LABEL: name:            test_rule298
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uqsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule159
+# TESTGEND-LABEL: name:            test_rule299
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -2341,835 +7759,756 @@
 # TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule160
+# TESTGEND-LABEL: name:            test_rule300
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
-# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule161
+# TESTGEND-LABEL: name:            test_rule301
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule162
+# TESTGEND-LABEL: name:            test_rule302
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule163
+# TESTGEND-LABEL: name:            test_rule303
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule164
+# TESTGEND-LABEL: name:            test_rule304
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.shsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule165
+# TESTGEND-LABEL: name:            test_rule305
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule166
+# TESTGEND-LABEL: name:            test_rule306
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
-#
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
-# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule167
+# TESTGEND-LABEL: name:            test_rule307
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule168
+# TESTGEND-LABEL: name:            test_rule308
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule169
+# TESTGEND-LABEL: name:            test_rule309
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule170
+# TESTGEND-LABEL: name:            test_rule310
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uhsub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule171
+# TESTGEND-LABEL: name:            test_rule311
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usad8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule172
+# TESTGEND-LABEL: name:            test_rule312
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
-# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuad), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule173
+# TESTGEND-LABEL: name:            test_rule313
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuadx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule174
+# TESTGEND-LABEL: name:            test_rule314
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule175
+# TESTGEND-LABEL: name:            test_rule315
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusdx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule176
+# TESTGEND-LABEL: name:            test_rule316
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32b), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule177
+# TESTGEND-LABEL: name:            test_rule317
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule178
+# TESTGEND-LABEL: name:            test_rule318
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
-# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32h), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule179
+# TESTGEND-LABEL: name:            test_rule319
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
-#
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
-# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32ch), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule180
+# TESTGEND-LABEL: name:            test_rule320
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
-# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32w), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule181
+# TESTGEND-LABEL: name:            test_rule321
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.crc32cw), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule182
+# TESTGEND-LABEL: name:            test_rule322
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule183
+# TESTGEND-LABEL: name:            test_rule323
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule188
+# TESTGEND-LABEL: name:            test_rule324
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
-# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule189
+# TESTGEND-LABEL: name:            test_rule325
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
-# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
-# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule192
+# TESTGEND-LABEL: name:            test_rule326
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule193
+# TESTGEND-LABEL: name:            test_rule327
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule194
+# TESTGEND-LABEL: name:            test_rule328
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule195
+# TESTGEND-LABEL: name:            test_rule329
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule196
+# TESTGEND-LABEL: name:            test_rule330
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule197
+# TESTGEND-LABEL: name:            test_rule331
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule198
+# TESTGEND-LABEL: name:            test_rule332
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3178,28 +8517,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %5:fprb(s64) = COPY $d18
-# TESTGEND:           %4:fprb(s64) = COPY $d17
-# TESTGEND:           %3:fprb(s64) = COPY $d16
-# TESTGEND:           %1:fprb(s64) = G_FNEG %5
-# TESTGEND:           %0:fprb(s64) = G_FNEG %4
-# TESTGEND:           %2:fprb(s64) = G_FMA %0, %3, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule199
+# TESTGEND-LABEL: name:            test_rule333
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3208,364 +8540,297 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $s0, $s2, $s4
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %5:fprb(s32) = COPY $s4
-# TESTGEND:           %4:fprb(s32) = COPY $s2
-# TESTGEND:           %3:fprb(s32) = COPY $s0
-# TESTGEND:           %1:fprb(s32) = G_FNEG %5
-# TESTGEND:           %0:fprb(s32) = G_FNEG %4
-# TESTGEND:           %2:fprb(s32) = G_FMA %0, %3, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule200
+# TESTGEND-LABEL: name:            test_rule334
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule201
+# TESTGEND-LABEL: name:            test_rule335
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule202
+# TESTGEND-LABEL: name:            test_rule336
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule203
+# TESTGEND-LABEL: name:            test_rule337
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule204
+# TESTGEND-LABEL: name:            test_rule338
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule205
+# TESTGEND-LABEL: name:            test_rule339
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule206
+# TESTGEND-LABEL: name:            test_rule340
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule207
+# TESTGEND-LABEL: name:            test_rule341
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule208
+# TESTGEND-LABEL: name:            test_rule342
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule209
+# TESTGEND-LABEL: name:            test_rule343
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-# TESTGEND:           %2:_(<8 x s16>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule210
+# TESTGEND-LABEL: name:            test_rule344
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-# TESTGEND:           %2:_(<4 x s32>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule211
+# TESTGEND-LABEL: name:            test_rule345
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-# TESTGEND:           %2:_(<2 x s64>) = G_SUB %0, %1
-# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule213
+# TESTGEND-LABEL: name:            test_rule346
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3574,28 +8839,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %5:fprb(s64) = COPY $d18
-# TESTGEND:           %4:fprb(s64) = COPY $d17
-# TESTGEND:           %3:fprb(s64) = COPY $d16
-# TESTGEND:           %1:fprb(s64) = G_FNEG %5
-# TESTGEND:           %0:fprb(s64) = G_FMA %1, %3, %4
-# TESTGEND:           %2:fprb(s64) = G_FNEG %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule214
+# TESTGEND-LABEL: name:            test_rule347
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3604,28 +8862,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $s0, $s2, $s4
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %5:fprb(s32) = COPY $s4
-# TESTGEND:           %4:fprb(s32) = COPY $s2
-# TESTGEND:           %3:fprb(s32) = COPY $s0
-# TESTGEND:           %1:fprb(s32) = G_FNEG %5
-# TESTGEND:           %0:fprb(s32) = G_FMA %1, %3, %4
-# TESTGEND:           %2:fprb(s32) = G_FNEG %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule215
+# TESTGEND-LABEL: name:            test_rule348
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3634,28 +8885,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %5:fprb(s64) = COPY $d18
-# TESTGEND:           %4:fprb(s64) = COPY $d17
-# TESTGEND:           %3:fprb(s64) = COPY $d16
-# TESTGEND:           %1:fprb(s64) = G_FNEG %5
-# TESTGEND:           %0:fprb(s64) = G_FMA %3, %1, %4
-# TESTGEND:           %2:fprb(s64) = G_FNEG %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule216
+# TESTGEND-LABEL: name:            test_rule349
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3664,80 +8908,67 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
-# TESTGEND:         - { id: 4, class: fprb }
-# TESTGEND:         - { id: 5, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
-# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
-# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $s0, $s2, $s4
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %5:fprb(s32) = COPY $s4
-# TESTGEND:           %4:fprb(s32) = COPY $s2
-# TESTGEND:           %3:fprb(s32) = COPY $s0
-# TESTGEND:           %1:fprb(s32) = G_FNEG %5
-# TESTGEND:           %0:fprb(s32) = G_FMA %3, %1, %4
-# TESTGEND:           %2:fprb(s32) = G_FNEG %0
-# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule217
+# TESTGEND-LABEL: name:            test_rule350
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0, $r1
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:gprb(s32) = COPY $r1
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule218
+# TESTGEND-LABEL: name:            test_rule351
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
-# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0, $r1
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:gprb(s32) = COPY $r1
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule223
+# TESTGEND-LABEL: name:            test_rule352
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3746,108 +8977,113 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule224
+# TESTGEND-LABEL: name:            test_rule353
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule225
+# TESTGEND-LABEL: name:            test_rule354
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule226
+# TESTGEND-LABEL: name:            test_rule355
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule227
+# TESTGEND-LABEL: name:            test_rule356
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule244
+# TESTGEND-LABEL: name:            test_rule357
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3856,24 +9092,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule245
+# TESTGEND-LABEL: name:            test_rule358
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3882,24 +9115,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d18
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule246
+# TESTGEND-LABEL: name:            test_rule359
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3908,24 +9138,21 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d18
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule248
+# TESTGEND-LABEL: name:            test_rule360
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -3934,108 +9161,113 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
-# TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
-# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17, $d18
+# TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %3:fprb(s64) = COPY $d18
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule249
+# TESTGEND-LABEL: name:            test_rule361
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule250
+# TESTGEND-LABEL: name:            test_rule362
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule251
+# TESTGEND-LABEL: name:            test_rule363
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule253
+# TESTGEND-LABEL: name:            test_rule364
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule322
+# TESTGEND-LABEL: name:            test_rule365
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4051,14 +9283,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule323
+# TESTGEND-LABEL: name:            test_rule366
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4068,58 +9300,66 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule324
+# TESTGEND-LABEL: name:            test_rule367
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule325
+# TESTGEND-LABEL: name:            test_rule368
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule326
+# TESTGEND-LABEL: name:            test_rule369
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4129,39 +9369,43 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule327
+# TESTGEND-LABEL: name:            test_rule370
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule328
+# TESTGEND-LABEL: name:            test_rule371
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4179,12 +9423,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule329
+# TESTGEND-LABEL: name:            test_rule372
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4202,50 +9446,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule330
+# TESTGEND-LABEL: name:            test_rule373
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule331
+# TESTGEND-LABEL: name:            test_rule374
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule332
+# TESTGEND-LABEL: name:            test_rule375
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4263,31 +9515,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule333
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule334
+# TESTGEND-LABEL: name:            test_rule376
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4303,14 +9536,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule335
+# TESTGEND-LABEL: name:            test_rule377
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4326,52 +9559,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule336
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule337
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule338
+# TESTGEND-LABEL: name:            test_rule378
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4387,33 +9582,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule339
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule340
+# TESTGEND-LABEL: name:            test_rule379
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4431,12 +9607,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule341
+# TESTGEND-LABEL: name:            test_rule380
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4454,50 +9630,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule342
+# TESTGEND-LABEL: name:            test_rule381
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule343
+# TESTGEND-LABEL: name:            test_rule382
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule344
+# TESTGEND-LABEL: name:            test_rule383
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4515,31 +9699,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule345
+# TESTGEND-LABEL: name:            test_rule384
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule346
+# TESTGEND-LABEL: name:            test_rule385
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4557,12 +9745,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule347
+# TESTGEND-LABEL: name:            test_rule386
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4580,50 +9768,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule348
+# TESTGEND-LABEL: name:            test_rule387
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule349
+# TESTGEND-LABEL: name:            test_rule388
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule350
+# TESTGEND-LABEL: name:            test_rule389
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4641,31 +9837,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule351
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule352
+# TESTGEND-LABEL: name:            test_rule390
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4675,39 +9852,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
-#
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule353
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule354
+# TESTGEND-LABEL: name:            test_rule391
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4725,12 +9883,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule355
+# TESTGEND-LABEL: name:            test_rule392
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4748,50 +9906,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule356
+# TESTGEND-LABEL: name:            test_rule393
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule357
+# TESTGEND-LABEL: name:            test_rule394
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule358
+# TESTGEND-LABEL: name:            test_rule395
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4809,31 +9975,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule359
+# TESTGEND-LABEL: name:            test_rule396
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule360
+# TESTGEND-LABEL: name:            test_rule397
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4851,88 +10021,127 @@
 #
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule361
+# TESTGEND-LABEL: name:            test_rule398
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule399
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule362
+# TESTGEND-LABEL: name:            test_rule400
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule363
+# TESTGEND-LABEL: name:            test_rule401
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule364
+# TESTGEND-LABEL: name:            test_rule402
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule365
+# TESTGEND-LABEL: name:            test_rule403
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4950,31 +10159,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule366
+# TESTGEND-LABEL: name:            test_rule404
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule367
+# TESTGEND-LABEL: name:            test_rule405
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -4990,14 +10203,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule368
+# TESTGEND-LABEL: name:            test_rule406
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5007,58 +10220,66 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule369
+# TESTGEND-LABEL: name:            test_rule407
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule370
+# TESTGEND-LABEL: name:            test_rule408
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule371
+# TESTGEND-LABEL: name:            test_rule409
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5068,20 +10289,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule372
+# TESTGEND-LABEL: name:            test_rule410
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5099,81 +10320,87 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule373
+# TESTGEND-LABEL: name:            test_rule411
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule374
+# TESTGEND-LABEL: name:            test_rule412
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule375
+# TESTGEND-LABEL: name:            test_rule413
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule376
+# TESTGEND-LABEL: name:            test_rule414
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
@@ -5183,21 +10410,43 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule377
+# TESTGEND-LABEL: name:            test_rule415
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule416
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
@@ -5209,36 +10458,35 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule378
+# TESTGEND-LABEL: name:            test_rule417
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule379
+# TESTGEND-LABEL: name:            test_rule418
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5256,12 +10504,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule380
+# TESTGEND-LABEL: name:            test_rule419
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5279,50 +10527,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule381
+# TESTGEND-LABEL: name:            test_rule420
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule382
+# TESTGEND-LABEL: name:            test_rule421
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule383
+# TESTGEND-LABEL: name:            test_rule422
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5340,31 +10596,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule384
+# TESTGEND-LABEL: name:            test_rule423
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule385
+# TESTGEND-LABEL: name:            test_rule424
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5382,12 +10642,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule386
+# TESTGEND-LABEL: name:            test_rule425
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5405,50 +10665,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule387
+# TESTGEND-LABEL: name:            test_rule426
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule388
+# TESTGEND-LABEL: name:            test_rule427
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule389
+# TESTGEND-LABEL: name:            test_rule428
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5466,31 +10734,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule390
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule391
+# TESTGEND-LABEL: name:            test_rule429
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5500,20 +10749,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule392
+# TESTGEND-LABEL: name:            test_rule430
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5531,50 +10780,35 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule393
+# TESTGEND-LABEL: name:            test_rule431
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule394
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule395
+# TESTGEND-LABEL: name:            test_rule432
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5590,33 +10824,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule396
+# TESTGEND-LABEL: name:            test_rule433
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule397
+# TESTGEND-LABEL: name:            test_rule434
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5632,33 +10870,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule398
+# TESTGEND-LABEL: name:            test_rule435
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule399
+# TESTGEND-LABEL: name:            test_rule436
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5674,14 +10916,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule400
+# TESTGEND-LABEL: name:            test_rule437
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5699,50 +10941,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule401
+# TESTGEND-LABEL: name:            test_rule438
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule402
+# TESTGEND-LABEL: name:            test_rule439
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule403
+# TESTGEND-LABEL: name:            test_rule440
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5758,33 +11008,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule404
+# TESTGEND-LABEL: name:            test_rule441
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule405
+# TESTGEND-LABEL: name:            test_rule442
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5794,96 +11048,112 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule406
+# TESTGEND-LABEL: name:            test_rule443
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule407
+# TESTGEND-LABEL: name:            test_rule444
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule408
+# TESTGEND-LABEL: name:            test_rule445
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule409
+# TESTGEND-LABEL: name:            test_rule446
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule410
+# TESTGEND-LABEL: name:            test_rule447
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5900,32 +11170,36 @@
 # TESTGEND:           liveins: $d16, $d17
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule411
+# TESTGEND-LABEL: name:            test_rule448
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule412
+# TESTGEND-LABEL: name:            test_rule449
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5935,39 +11209,43 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule413
+# TESTGEND-LABEL: name:            test_rule450
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule414
+# TESTGEND-LABEL: name:            test_rule451
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -5983,33 +11261,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule415
+# TESTGEND-LABEL: name:            test_rule452
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule416
+# TESTGEND-LABEL: name:            test_rule453
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6025,33 +11307,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule417
+# TESTGEND-LABEL: name:            test_rule454
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule418
+# TESTGEND-LABEL: name:            test_rule455
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6069,12 +11355,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule419
+# TESTGEND-LABEL: name:            test_rule456
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6092,50 +11378,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule420
+# TESTGEND-LABEL: name:            test_rule457
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule421
+# TESTGEND-LABEL: name:            test_rule458
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule422
+# TESTGEND-LABEL: name:            test_rule459
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6153,31 +11447,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule423
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule424
+# TESTGEND-LABEL: name:            test_rule460
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6195,12 +11470,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule425
+# TESTGEND-LABEL: name:            test_rule461
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6218,50 +11493,12 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule426
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule427
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule428
+# TESTGEND-LABEL: name:            test_rule462
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6279,31 +11516,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule429
+# TESTGEND-LABEL: name:            test_rule463
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule430
+# TESTGEND-LABEL: name:            test_rule464
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6321,31 +11562,35 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule431
+# TESTGEND-LABEL: name:            test_rule465
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule432
+# TESTGEND-LABEL: name:            test_rule466
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6363,31 +11608,35 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule433
+# TESTGEND-LABEL: name:            test_rule467
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule434
+# TESTGEND-LABEL: name:            test_rule468
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6397,20 +11646,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule435
+# TESTGEND-LABEL: name:            test_rule469
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6428,12 +11677,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule436
+# TESTGEND-LABEL: name:            test_rule470
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6443,20 +11692,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule437
+# TESTGEND-LABEL: name:            test_rule471
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6474,12 +11723,12 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule438
+# TESTGEND-LABEL: name:            test_rule472
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6489,20 +11738,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule439
+# TESTGEND-LABEL: name:            test_rule473
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6518,14 +11767,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule440
+# TESTGEND-LABEL: name:            test_rule474
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6535,20 +11784,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule441
+# TESTGEND-LABEL: name:            test_rule475
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6564,71 +11813,83 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule442
+# TESTGEND-LABEL: name:            test_rule476
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule443
+# TESTGEND-LABEL: name:            test_rule477
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule444
+# TESTGEND-LABEL: name:            test_rule478
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule445
+# TESTGEND-LABEL: name:            test_rule479
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6645,13 +11906,13 @@
 # TESTGEND:           liveins: $d16, $d17
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule446
+# TESTGEND-LABEL: name:            test_rule480
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6661,20 +11922,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule447
+# TESTGEND-LABEL: name:            test_rule481
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6690,71 +11951,60 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule448
+# TESTGEND-LABEL: name:            test_rule482
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule449
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule450
+# TESTGEND-LABEL: name:            test_rule483
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule451
+# TESTGEND-LABEL: name:            test_rule484
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6770,14 +12020,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule452
+# TESTGEND-LABEL: name:            test_rule485
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6787,20 +12037,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule453
+# TESTGEND-LABEL: name:            test_rule486
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6810,20 +12060,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule454
+# TESTGEND-LABEL: name:            test_rule487
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6841,12 +12091,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule455
+# TESTGEND-LABEL: name:            test_rule488
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6856,20 +12106,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule456
+# TESTGEND-LABEL: name:            test_rule489
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6885,14 +12135,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule457
+# TESTGEND-LABEL: name:            test_rule490
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6902,20 +12152,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule458
+# TESTGEND-LABEL: name:            test_rule491
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6933,12 +12183,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule459
+# TESTGEND-LABEL: name:            test_rule492
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6954,14 +12204,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule460
+# TESTGEND-LABEL: name:            test_rule493
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6971,20 +12221,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule461
+# TESTGEND-LABEL: name:            test_rule494
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -6994,20 +12244,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule462
+# TESTGEND-LABEL: name:            test_rule495
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7025,12 +12275,12 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule463
+# TESTGEND-LABEL: name:            test_rule496
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7040,20 +12290,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule464
+# TESTGEND-LABEL: name:            test_rule497
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7069,14 +12319,14 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule465
+# TESTGEND-LABEL: name:            test_rule498
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7086,20 +12336,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule466
+# TESTGEND-LABEL: name:            test_rule499
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7117,12 +12367,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule467
+# TESTGEND-LABEL: name:            test_rule500
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7140,31 +12390,12 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule468
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
-#
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule469
+# TESTGEND-LABEL: name:            test_rule501
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7174,39 +12405,43 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule470
+# TESTGEND-LABEL: name:            test_rule502
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule471
+# TESTGEND-LABEL: name:            test_rule503
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7222,33 +12457,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule472
+# TESTGEND-LABEL: name:            test_rule504
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule473
+# TESTGEND-LABEL: name:            test_rule505
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7264,33 +12503,37 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16, $d17
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule474
+# TESTGEND-LABEL: name:            test_rule506
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule475
+# TESTGEND-LABEL: name:            test_rule507
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7308,12 +12551,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule476
+# TESTGEND-LABEL: name:            test_rule508
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7331,50 +12574,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule477
+# TESTGEND-LABEL: name:            test_rule509
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule478
+# TESTGEND-LABEL: name:            test_rule510
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule479
+# TESTGEND-LABEL: name:            test_rule511
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7392,31 +12643,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule480
+# TESTGEND-LABEL: name:            test_rule512
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule481
+# TESTGEND-LABEL: name:            test_rule513
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7434,31 +12689,35 @@
 #
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule482
+# TESTGEND-LABEL: name:            test_rule514
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule483
+# TESTGEND-LABEL: name:            test_rule515
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7476,12 +12735,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule484
+# TESTGEND-LABEL: name:            test_rule516
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7499,50 +12758,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule485
+# TESTGEND-LABEL: name:            test_rule517
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule486
+# TESTGEND-LABEL: name:            test_rule518
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule487
+# TESTGEND-LABEL: name:            test_rule519
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7560,31 +12827,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule488
+# TESTGEND-LABEL: name:            test_rule520
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule489
+# TESTGEND-LABEL: name:            test_rule521
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7602,31 +12873,35 @@
 #
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule490
+# TESTGEND-LABEL: name:            test_rule522
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule491
+# TESTGEND-LABEL: name:            test_rule523
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7644,12 +12919,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule492
+# TESTGEND-LABEL: name:            test_rule524
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7667,50 +12942,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule493
+# TESTGEND-LABEL: name:            test_rule525
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule494
+# TESTGEND-LABEL: name:            test_rule526
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule495
+# TESTGEND-LABEL: name:            test_rule527
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7728,31 +13011,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule496
+# TESTGEND-LABEL: name:            test_rule528
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule497
+# TESTGEND-LABEL: name:            test_rule529
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7770,31 +13057,35 @@
 #
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule498
+# TESTGEND-LABEL: name:            test_rule530
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule499
+# TESTGEND-LABEL: name:            test_rule531
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7812,12 +13103,12 @@
 #
 # TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule500
+# TESTGEND-LABEL: name:            test_rule532
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7835,50 +13126,58 @@
 #
 # TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule501
+# TESTGEND-LABEL: name:            test_rule533
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule502
+# TESTGEND-LABEL: name:            test_rule534
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule503
+# TESTGEND-LABEL: name:            test_rule535
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7896,31 +13195,35 @@
 #
 # TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule504
+# TESTGEND-LABEL: name:            test_rule536
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule505
+# TESTGEND-LABEL: name:            test_rule537
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7938,31 +13241,35 @@
 #
 # TESTGEND:           %2:fprb(s64) = COPY $d17
 # TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule506
+# TESTGEND-LABEL: name:            test_rule538
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule507
+# TESTGEND-LABEL: name:            test_rule539
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7972,20 +13279,20 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule508
+# TESTGEND-LABEL: name:            test_rule540
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -7995,722 +13302,848 @@
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $q8, $q9
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule509
+# TESTGEND-LABEL: name:            test_rule541
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule542
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule543
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtab16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule510
+# TESTGEND-LABEL: name:            test_rule544
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtab16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule511
+# TESTGEND-LABEL: name:            test_rule545
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuad), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule512
+# TESTGEND-LABEL: name:            test_rule546
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smuadx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule513
+# TESTGEND-LABEL: name:            test_rule547
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule514
+# TESTGEND-LABEL: name:            test_rule548
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smusdx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule515
+# TESTGEND-LABEL: name:            test_rule549
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule516
+# TESTGEND-LABEL: name:            test_rule550
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule517
+# TESTGEND-LABEL: name:            test_rule551
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule518
+# TESTGEND-LABEL: name:            test_rule552
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule519
+# TESTGEND-LABEL: name:            test_rule553
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule520
+# TESTGEND-LABEL: name:            test_rule554
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule521
+# TESTGEND-LABEL: name:            test_rule555
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtab16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule522
+# TESTGEND-LABEL: name:            test_rule556
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule523
+# TESTGEND-LABEL: name:            test_rule557
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.qsub), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule524
+# TESTGEND-LABEL: name:            test_rule558
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule525
+# TESTGEND-LABEL: name:            test_rule559
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulbt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule526
+# TESTGEND-LABEL: name:            test_rule560
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule527
+# TESTGEND-LABEL: name:            test_rule561
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smultt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule528
+# TESTGEND-LABEL: name:            test_rule562
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule529
+# TESTGEND-LABEL: name:            test_rule563
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.smulwt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule530
+# TESTGEND-LABEL: name:            test_rule564
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule531
+# TESTGEND-LABEL: name:            test_rule565
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule532
+# TESTGEND-LABEL: name:            test_rule566
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule533
+# TESTGEND-LABEL: name:            test_rule567
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule534
+# TESTGEND-LABEL: name:            test_rule568
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule535
+# TESTGEND-LABEL: name:            test_rule569
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule536
+# TESTGEND-LABEL: name:            test_rule570
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule537
+# TESTGEND-LABEL: name:            test_rule571
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16, $d17
+# TESTGEND:           liveins: $lr, $r0
 #
-# TESTGEND:           %2:fprb(s64) = COPY $d17
-# TESTGEND:           %1:fprb(s64) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule538
+# TESTGEND-LABEL: name:            test_rule572
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule539
+# TESTGEND-LABEL: name:            test_rule573
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule540
+# TESTGEND-LABEL: name:            test_rule574
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule541
+# TESTGEND-LABEL: name:            test_rule575
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule542
+# TESTGEND-LABEL: name:            test_rule576
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule564
+# TESTGEND-LABEL: name:            test_rule577
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8733,7 +14166,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule565
+# TESTGEND-LABEL: name:            test_rule578
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8756,7 +14189,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule566
+# TESTGEND-LABEL: name:            test_rule579
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8779,7 +14212,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule567
+# TESTGEND-LABEL: name:            test_rule580
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8802,7 +14235,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule568
+# TESTGEND-LABEL: name:            test_rule581
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8825,7 +14258,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule569
+# TESTGEND-LABEL: name:            test_rule582
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8848,7 +14281,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule570
+# TESTGEND-LABEL: name:            test_rule583
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8871,7 +14304,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule571
+# TESTGEND-LABEL: name:            test_rule584
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8894,7 +14327,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule572
+# TESTGEND-LABEL: name:            test_rule585
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8917,7 +14350,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule573
+# TESTGEND-LABEL: name:            test_rule586
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8940,7 +14373,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule574
+# TESTGEND-LABEL: name:            test_rule587
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8963,7 +14396,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule575
+# TESTGEND-LABEL: name:            test_rule588
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -8986,7 +14419,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule576
+# TESTGEND-LABEL: name:            test_rule589
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9009,7 +14442,7 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule577
+# TESTGEND-LABEL: name:            test_rule590
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9020,339 +14453,480 @@
 # TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
 # TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule578
+# TESTGEND-LABEL: name:            test_rule591
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule592
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtr), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule593
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtr), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule594
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtru), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule595
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.vcvtru), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule596
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule597
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule598
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule599
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule600
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule579
+# TESTGEND-LABEL: name:            test_rule601
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule580
+# TESTGEND-LABEL: name:            test_rule602
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule581
+# TESTGEND-LABEL: name:            test_rule603
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule582
+# TESTGEND-LABEL: name:            test_rule604
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule583
+# TESTGEND-LABEL: name:            test_rule605
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule584
+# TESTGEND-LABEL: name:            test_rule606
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule585
+# TESTGEND-LABEL: name:            test_rule607
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule586
+# TESTGEND-LABEL: name:            test_rule608
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule587
+# TESTGEND-LABEL: name:            test_rule609
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule588
+# TESTGEND-LABEL: name:            test_rule610
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule589
+# TESTGEND-LABEL: name:            test_rule611
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
-# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr, $r0
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %2:gprb(s32) = COPY $r0
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule590
+# TESTGEND-LABEL: name:            test_rule612
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule591
+# TESTGEND-LABEL: name:            test_rule613
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: gprb }
-# TESTGEND:         - { id: 1, class: gprb }
-# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $lr
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:gprb(s32) = COPY $lr
-# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
-# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule596
+# TESTGEND-LABEL: name:            test_rule614
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9366,13 +14940,13 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule597
+# TESTGEND-LABEL: name:            test_rule615
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9381,18 +14955,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule598
+# TESTGEND-LABEL: name:            test_rule616
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9407,63 +14981,72 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule599
+# TESTGEND-LABEL: name:            test_rule617
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule600
+# TESTGEND-LABEL: name:            test_rule618
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule601
+# TESTGEND-LABEL: name:            test_rule619
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule602
+# TESTGEND-LABEL: name:            test_rule620
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9478,12 +15061,12 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule603
+# TESTGEND-LABEL: name:            test_rule621
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9498,12 +15081,12 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule604
+# TESTGEND-LABEL: name:            test_rule622
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9518,63 +15101,72 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule605
+# TESTGEND-LABEL: name:            test_rule623
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule606
+# TESTGEND-LABEL: name:            test_rule624
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule607
+# TESTGEND-LABEL: name:            test_rule625
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule608
+# TESTGEND-LABEL: name:            test_rule626
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9588,30 +15180,33 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule609
+# TESTGEND-LABEL: name:            test_rule627
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule610
+# TESTGEND-LABEL: name:            test_rule628
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9626,29 +15221,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule611
+# TESTGEND-LABEL: name:            test_rule629
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule612
+# TESTGEND-LABEL: name:            test_rule630
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9657,35 +15255,38 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule613
+# TESTGEND-LABEL: name:            test_rule631
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule614
+# TESTGEND-LABEL: name:            test_rule632
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9699,30 +15300,33 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule615
+# TESTGEND-LABEL: name:            test_rule633
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule616
+# TESTGEND-LABEL: name:            test_rule634
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9737,29 +15341,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule617
+# TESTGEND-LABEL: name:            test_rule635
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule618
+# TESTGEND-LABEL: name:            test_rule636
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9768,35 +15375,38 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule619
+# TESTGEND-LABEL: name:            test_rule637
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule620
+# TESTGEND-LABEL: name:            test_rule638
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9805,18 +15415,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule621
+# TESTGEND-LABEL: name:            test_rule639
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9825,18 +15435,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule622
+# TESTGEND-LABEL: name:            test_rule640
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9845,69 +15455,58 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule623
+# TESTGEND-LABEL: name:            test_rule641
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule624
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule625
+# TESTGEND-LABEL: name:            test_rule642
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule626
+# TESTGEND-LABEL: name:            test_rule643
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9916,18 +15515,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule627
+# TESTGEND-LABEL: name:            test_rule644
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9936,18 +15535,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule628
+# TESTGEND-LABEL: name:            test_rule645
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -9956,69 +15555,58 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule629
+# TESTGEND-LABEL: name:            test_rule646
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule630
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule631
+# TESTGEND-LABEL: name:            test_rule647
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule632
+# TESTGEND-LABEL: name:            test_rule648
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10027,18 +15615,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule633
+# TESTGEND-LABEL: name:            test_rule649
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10052,13 +15640,13 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule634
+# TESTGEND-LABEL: name:            test_rule650
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10067,222 +15655,258 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule635
+# TESTGEND-LABEL: name:            test_rule651
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule636
+# TESTGEND-LABEL: name:            test_rule652
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule637
+# TESTGEND-LABEL: name:            test_rule653
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule638
+# TESTGEND-LABEL: name:            test_rule654
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule639
+# TESTGEND-LABEL: name:            test_rule655
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule640
+# TESTGEND-LABEL: name:            test_rule656
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule641
+# TESTGEND-LABEL: name:            test_rule657
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule642
+# TESTGEND-LABEL: name:            test_rule658
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule643
+# TESTGEND-LABEL: name:            test_rule659
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule644
+# TESTGEND-LABEL: name:            test_rule660
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule645
+# TESTGEND-LABEL: name:            test_rule661
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule646
+# TESTGEND-LABEL: name:            test_rule662
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule647
+# TESTGEND-LABEL: name:            test_rule663
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10297,29 +15921,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule648
+# TESTGEND-LABEL: name:            test_rule664
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule649
+# TESTGEND-LABEL: name:            test_rule665
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10334,29 +15961,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule650
+# TESTGEND-LABEL: name:            test_rule666
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule651
+# TESTGEND-LABEL: name:            test_rule667
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10371,29 +16001,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule652
+# TESTGEND-LABEL: name:            test_rule668
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule653
+# TESTGEND-LABEL: name:            test_rule669
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10408,29 +16041,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule654
+# TESTGEND-LABEL: name:            test_rule670
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule655
+# TESTGEND-LABEL: name:            test_rule671
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10445,29 +16081,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule656
+# TESTGEND-LABEL: name:            test_rule672
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule657
+# TESTGEND-LABEL: name:            test_rule673
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10482,29 +16121,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule658
+# TESTGEND-LABEL: name:            test_rule674
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule659
+# TESTGEND-LABEL: name:            test_rule675
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10519,29 +16161,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule660
+# TESTGEND-LABEL: name:            test_rule676
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule661
+# TESTGEND-LABEL: name:            test_rule677
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10556,29 +16201,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule662
+# TESTGEND-LABEL: name:            test_rule678
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule663
+# TESTGEND-LABEL: name:            test_rule679
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10587,35 +16235,38 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule664
+# TESTGEND-LABEL: name:            test_rule680
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule665
+# TESTGEND-LABEL: name:            test_rule681
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10630,29 +16281,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule666
+# TESTGEND-LABEL: name:            test_rule682
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule667
+# TESTGEND-LABEL: name:            test_rule683
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10667,29 +16321,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule668
+# TESTGEND-LABEL: name:            test_rule684
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule669
+# TESTGEND-LABEL: name:            test_rule685
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10703,30 +16360,33 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule670
+# TESTGEND-LABEL: name:            test_rule686
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule671
+# TESTGEND-LABEL: name:            test_rule687
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10740,30 +16400,33 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule672
+# TESTGEND-LABEL: name:            test_rule688
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule673
+# TESTGEND-LABEL: name:            test_rule689
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10778,29 +16441,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule674
+# TESTGEND-LABEL: name:            test_rule690
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule675
+# TESTGEND-LABEL: name:            test_rule691
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10815,29 +16481,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule676
+# TESTGEND-LABEL: name:            test_rule692
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule677
+# TESTGEND-LABEL: name:            test_rule693
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10851,68 +16520,73 @@
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $d16
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule678
+# TESTGEND-LABEL: name:            test_rule694
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule679
+# TESTGEND-LABEL: name:            test_rule695
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule680
+# TESTGEND-LABEL: name:            test_rule696
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule681
+# TESTGEND-LABEL: name:            test_rule697
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10927,29 +16601,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule682
+# TESTGEND-LABEL: name:            test_rule698
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule683
+# TESTGEND-LABEL: name:            test_rule699
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -10964,29 +16641,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule684
+# TESTGEND-LABEL: name:            test_rule700
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule685
+# TESTGEND-LABEL: name:            test_rule701
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11001,29 +16681,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule686
+# TESTGEND-LABEL: name:            test_rule702
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule687
+# TESTGEND-LABEL: name:            test_rule703
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11038,29 +16721,32 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule688
+# TESTGEND-LABEL: name:            test_rule704
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule689
+# TESTGEND-LABEL: name:            test_rule705
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11069,35 +16755,18 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
-#
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:       ...
-# TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule690
-# TESTGEND:       alignment:       2
-# TESTGEND:       legalized:       true
-# TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
-# TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:       body:             |
-# TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule691
+# TESTGEND-LABEL: name:            test_rule706
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11106,348 +16775,401 @@
 # TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule692
+# TESTGEND-LABEL: name:            test_rule707
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule693
+# TESTGEND-LABEL: name:            test_rule708
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.sxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule694
+# TESTGEND-LABEL: name:            test_rule709
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %0:gprb(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule695
+# TESTGEND-LABEL: name:            test_rule710
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 4294901760
+# TESTGEND:           %0:gprb(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule696
+# TESTGEND-LABEL: name:            test_rule711
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule697
+# TESTGEND-LABEL: name:            test_rule712
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { id: 0, class: gprb }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
-#
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule698
+# TESTGEND-LABEL: name:            test_rule713
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%0' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %0:gprb(s32) = COPY $lr
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule699
+# TESTGEND-LABEL: name:            test_rule714
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
-# TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
-#
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+# TESTGEND:           $noreg = PATCHABLE_RET
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule700
+# TESTGEND-LABEL: name:            test_rule715
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
-# TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+# TESTGEND:           $noreg = PATCHABLE_RET
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule701
+# TESTGEND-LABEL: name:            test_rule716
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule702
+# TESTGEND-LABEL: name:            test_rule717
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule703
+# TESTGEND-LABEL: name:            test_rule718
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule704
+# TESTGEND-LABEL: name:            test_rule719
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule705
+# TESTGEND-LABEL: name:            test_rule720
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule706
+# TESTGEND-LABEL: name:            test_rule721
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule712
+# TESTGEND-LABEL: name:            test_rule722
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule713
+# TESTGEND-LABEL: name:            test_rule723
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
 # TESTGEND:       liveins:
-# TESTGEND:         - { reg: '$lr', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
 # TESTGEND:           liveins: $lr
 #
-# TESTGEND:           %0:gprb(s32) = COPY $lr
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule714
+# TESTGEND-LABEL: name:            test_rule724
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule715
+# TESTGEND-LABEL: name:            test_rule725
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
 # TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
-# TESTGEND:           $noreg = PATCHABLE_RET
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule716
+# TESTGEND-LABEL: name:            test_rule726
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11464,12 +17186,12 @@
 #
 # TESTGEND:           %2:gprb(s32) = COPY $lr
 # TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           %1:gprb(s32) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule717
+# TESTGEND-LABEL: name:            test_rule727
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11486,12 +17208,12 @@
 #
 # TESTGEND:           %2:gprb(s32) = COPY $lr
 # TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           %1:gprb(s32) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule718
+# TESTGEND-LABEL: name:            test_rule728
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11508,12 +17230,12 @@
 #
 # TESTGEND:           %2:gprb(s32) = COPY $lr
 # TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           %1:gprb(s32) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule724
+# TESTGEND-LABEL: name:            test_rule729
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11530,12 +17252,12 @@
 #
 # TESTGEND:           %2:gprb(s32) = COPY $lr
 # TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           %1:gprb(s32) = G_XOR %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
-# TESTGEND-LABEL: name:            test_rule725
+# TESTGEND-LABEL: name:            test_rule730
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
@@ -11552,7 +17274,7 @@
 #
 # TESTGEND:           %2:gprb(s32) = COPY $lr
 # TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
-# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           %1:gprb(s32) = G_XOR %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
 #
 # TESTGEND:       ...
@@ -11645,21 +17367,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FNEG %4
-# TESTGEND:           %1:_(<4 x s32>) = G_FMA %0, %2, %3
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fprb(<4 x s32>) = G_FMA %0, %2, %3
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -11776,6 +17503,90 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule739
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule740
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule741
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule742
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -11864,21 +17675,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -11887,21 +17703,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -11910,21 +17731,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -11933,23 +17759,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -11958,23 +17784,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -11983,23 +17809,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -12008,23 +17834,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12033,23 +17859,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12058,23 +17884,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -12167,21 +17993,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<16 x s8>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -12190,21 +18021,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12213,46 +18049,135 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule760
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule761
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule762
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule763
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12261,23 +18186,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12286,23 +18211,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -12311,23 +18236,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12336,23 +18261,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12361,23 +18286,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_ADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -12414,21 +18339,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_FADD %0, %2
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_FADD %0, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12465,21 +18395,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_FADD %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_FADD %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12616,21 +18551,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_FSUB %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_FSUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12667,25 +18607,86 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_FSUB %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_FSUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule781
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule782
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r1
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gprb(s32) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule783
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -12774,21 +18775,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<16 x s8>) = G_SUB %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<16 x s8>) = COPY $q10
+# TESTGEND:           %3:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<16 x s8>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -12797,21 +18803,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<8 x s16>) = COPY $q10
+# TESTGEND:           %3:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s16>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12820,21 +18831,26 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
-# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%4' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
-# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %4:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s32>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12843,23 +18859,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12868,23 +18884,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12893,23 +18909,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -12918,23 +18934,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s16>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -12943,23 +18959,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s32>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -12968,23 +18984,23 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
 # TESTGEND:         - { id: 3, class: fprb }
 # TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%2' }
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $d16
+# TESTGEND:           liveins: $q8, $d16
 #
 # TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-# TESTGEND:           %1:_(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s64>) = G_SUB %2, %0
 # TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -13095,6 +19111,82 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule799
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %3:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FMUL %2, %3
+# TESTGEND:           %1:fprb(s16) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule800
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule801
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule802
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule803
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule804
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13177,19 +19269,24 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
-# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q10', virtual-reg: '%3' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FMA %1, %2, %3
+# TESTGEND:           liveins: $q8, $q9, $q10
+#
+# TESTGEND:           %3:fprb(<4 x s32>) = COPY $q10
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FMA %1, %2, %3
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -13313,17 +19410,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_ADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -13332,17 +19433,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -13351,17 +19456,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -13393,17 +19502,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -13431,6 +19544,52 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule819
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule820
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule821
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13458,21 +19617,48 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_AND %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_AND %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule823
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule824
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13519,6 +19705,24 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule826
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %2:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule827
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13546,17 +19750,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -13588,17 +19796,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FADD %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FADD %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -13649,6 +19861,24 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule833
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %2:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule834
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13695,6 +19925,24 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule836
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %2:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule837
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -13722,17 +19970,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FMUL %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -13764,17 +20016,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FMUL %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -13816,12 +20072,30 @@
 # TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           liveins: $s0, $s2
-#
-# TESTGEND:           %2:fprb(s32) = COPY $s2
-# TESTGEND:           %1:fprb(s32) = COPY $s0
-# TESTGEND:           %0:fprb(s32) = G_FSUB %1, %2
-# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule843
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %2:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
@@ -13852,17 +20126,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FSUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -13894,21 +20172,48 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FSUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FSUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule848
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule849
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -14051,17 +20356,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_MUL %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_MUL %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -14070,17 +20379,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_MUL %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -14089,21 +20402,71 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_MUL %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule858
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule859
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule860
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -14131,17 +20494,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_OR %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_OR %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14192,6 +20559,75 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule864
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule865
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule866
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule867
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -14265,17 +20701,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<16 x s8>) = COPY $q9
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_SUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -14284,17 +20724,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<8 x s16>) = COPY $q9
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -14303,17 +20747,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14345,17 +20793,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<2 x s64>) = COPY $q9
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SUB %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14406,6 +20858,52 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule877
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule878
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule879
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -14433,17 +20931,21 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
-# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q9', virtual-reg: '%2' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_XOR %1, %2
+# TESTGEND:           liveins: $q8, $q9
+#
+# TESTGEND:           %2:fprb(<4 x s32>) = COPY $q9
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_XOR %1, %2
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14452,10 +20954,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -14464,7 +20965,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -14473,10 +20974,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -14485,7 +20985,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:_(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14494,10 +20994,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -14506,7 +21005,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14835,15 +21334,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14852,15 +21354,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14869,15 +21374,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14886,15 +21394,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -14903,15 +21414,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14920,15 +21434,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14937,15 +21454,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14954,15 +21474,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -14971,15 +21494,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -14988,15 +21514,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15005,15 +21534,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15022,15 +21554,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15039,15 +21574,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15056,15 +21594,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15313,15 +21854,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -15330,15 +21874,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -15347,15 +21894,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<2 x s64>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -15364,15 +21914,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15381,15 +21934,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15398,15 +21954,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15415,15 +21974,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15432,15 +21994,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15449,15 +22014,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<16 x s8>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_BITCAST %1(<16 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15466,15 +22034,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15483,15 +22054,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15500,15 +22074,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<16 x s8>) = G_BITCAST %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
 #
 # TESTGEND:       ...
@@ -15573,6 +22150,20 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1001
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1002
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -15613,6 +22204,22 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1004
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(s16) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1005
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -15637,15 +22244,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FNEG %1
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FNEG %1
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15674,15 +22284,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FNEG %1
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FNEG %1
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15731,15 +22344,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15768,15 +22384,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15821,6 +22440,22 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1018
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_FPTOSI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1019
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -15845,15 +22480,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -15882,15 +22520,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15935,6 +22576,22 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1025
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:fprb(s16) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_FPTOUI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1026
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
@@ -15955,14 +22612,53 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1027
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s16) = G_FPTRUNC %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1028
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s16) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1029
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -15971,7 +22667,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SEXT %1(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -15980,10 +22676,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -15992,7 +22687,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SEXT %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -16001,10 +22696,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -16013,7 +22707,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_SEXT %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...
@@ -16042,15 +22736,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_SITOFP %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -16079,15 +22776,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_SITOFP %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -16132,18 +22832,41 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1038
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s16) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1039
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
 # TESTGEND:           %0:fprb(<8 x s8>) = G_TRUNC %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
 #
@@ -16153,14 +22876,17 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
 # TESTGEND:           %0:fprb(<4 x s16>) = G_TRUNC %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
 #
@@ -16170,14 +22896,17 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
 # TESTGEND:         - { id: 0, class: fprb }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<2 x s64>) = COPY $q8
 # TESTGEND:           %0:fprb(<2 x s32>) = G_TRUNC %1(<2 x s64>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
 #
@@ -16207,15 +22936,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<4 x s32>) = COPY $q8
+# TESTGEND:           %0:fprb(<4 x s32>) = G_UITOFP %1(<4 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -16244,15 +22976,18 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
-# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q8', virtual-reg: '%1' }
 # TESTGEND:       body:             |
 # TESTGEND:         bb.0.entry:
-# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
-# TESTGEND:           %0:_(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+# TESTGEND:           liveins: $q8
+#
+# TESTGEND:           %1:fprb(<8 x s16>) = COPY $q8
+# TESTGEND:           %0:fprb(<8 x s16>) = G_UITOFP %1(<8 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -16297,14 +23032,33 @@
 #
 # TESTGEND:       ...
 # TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1048
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s16) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
 # TESTGEND-LABEL: name:            test_rule1049
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -16313,7 +23067,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
-# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %0:fprb(<8 x s16>) = G_ZEXT %1(<8 x s8>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
 #
 # TESTGEND:       ...
@@ -16322,10 +23076,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -16334,7 +23087,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
-# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %0:fprb(<4 x s32>) = G_ZEXT %1(<4 x s16>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
 #
 # TESTGEND:       ...
@@ -16343,10 +23096,9 @@
 # TESTGEND:       alignment:       2
 # TESTGEND:       legalized:       true
 # TESTGEND:       regBankSelected: true
-# TESTGEND:       failedISel:      true
 # TESTGEND:       tracksRegLiveness: true
 # TESTGEND:       registers:
-# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 0, class: fprb }
 # TESTGEND:         - { id: 1, class: fprb }
 # TESTGEND:       liveins:
 # TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
@@ -16355,7 +23107,7 @@
 # TESTGEND:           liveins: $d16
 #
 # TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
-# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %0:fprb(<2 x s64>) = G_ZEXT %1(<2 x s32>)
 # TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
 #
 # TESTGEND:       ...