Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
@@ -0,0 +1,24364 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+#
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple arm-- -run-pass instruction-select \
+# RUN:     -testgen-set-all-features -disable-gisel-legality-check \
+# RUN:     -verify-machineinstrs -simplify-mir %s -o - 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=SELECTED
+#
+# Test if this file is in sync with the current state of the selector:
+# RUN: cat %s | FileCheck --check-prefix=TESTGEND \
+# RUN:     %S/arm-instruction-select-testgen-testgend.mir
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "arm--"
+
+  define void @test_return() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule0_id2693_at_idx0() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1_id2724_at_idx167() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule4_id1713_at_idx668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule5_id1912_at_idx757() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule6_id2704_at_idx846() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule7_id2705_at_idx939() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule8_id2732_at_idx1032() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule9_id2733_at_idx1125() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule10_id1819_at_idx1218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule11_id1820_at_idx1311() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule12_id1999_at_idx1404() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule13_id2000_at_idx1497() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule14_id255_at_idx1590() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule15_id256_at_idx1768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule16_id610_at_idx1940() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule17_id611_at_idx2118() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule31_id1816_at_idx4333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule32_id1817_at_idx4394() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule33_id1818_at_idx4455() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule34_id1996_at_idx4516() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule35_id1997_at_idx4577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule36_id1998_at_idx4638() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule37_id1714_at_idx4699() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule38_id1911_at_idx4756() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule43_id265_at_idx5471() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule44_id266_at_idx5637() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule45_id606_at_idx5797() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule46_id607_at_idx5963() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule51_id188_at_idx6729() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule52_id519_at_idx6847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule69_id267_at_idx9081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule70_id268_at_idx9211() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule71_id608_at_idx9335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule72_id609_at_idx9465() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule73_id2758_at_idx9595() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule74_id2759_at_idx9697() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule75_id2760_at_idx9799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule76_id2761_at_idx9901() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule77_id2778_at_idx10003() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule78_id2779_at_idx10103() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule81_id2145_at_idx10393() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule82_id2146_at_idx10495() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule83_id2147_at_idx10597() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule84_id2148_at_idx10699() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule85_id2153_at_idx10801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule86_id2154_at_idx10903() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule87_id2155_at_idx11005() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule88_id2156_at_idx11107() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule89_id2161_at_idx11209() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule90_id2162_at_idx11309() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule91_id2168_at_idx11409() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule92_id2169_at_idx11509() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule97_id203_at_idx11989() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule110_id2651_at_idx13351() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule111_id2652_at_idx13469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule112_id2653_at_idx13587() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule113_id2654_at_idx13705() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule114_id2655_at_idx13823() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule115_id2656_at_idx13941() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule116_id1150_at_idx14059() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule117_id1151_at_idx14177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule118_id1152_at_idx14295() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule119_id1153_at_idx14413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule120_id1154_at_idx14531() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule121_id1155_at_idx14649() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule124_id350_at_idx14917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule129_id2_at_idx15279() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule130_id10_at_idx15340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule131_id11_at_idx15401() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule132_id237_at_idx15456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule133_id238_at_idx15511() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule134_id239_at_idx15566() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule135_id285_at_idx15621() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule136_id349_at_idx15682() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule137_id498_at_idx15737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule138_id572_at_idx15792() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule139_id573_at_idx15853() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule140_id574_at_idx15914() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule141_id592_at_idx15975() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule142_id593_at_idx16036() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule143_id1611_at_idx16097() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule144_id1612_at_idx16174() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule145_id1613_at_idx16251() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule146_id1614_at_idx16328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule147_id1615_at_idx16405() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule148_id1616_at_idx16482() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule149_id1617_at_idx16559() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule150_id1618_at_idx16636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule151_id1619_at_idx16713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule152_id1620_at_idx16790() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule153_id1621_at_idx16867() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule154_id1622_at_idx16944() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule155_id1623_at_idx17021() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule156_id1624_at_idx17098() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule157_id1625_at_idx17175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule158_id1626_at_idx17252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule159_id1684_at_idx17329() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule160_id2639_at_idx17403() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule161_id2640_at_idx17501() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule162_id2641_at_idx17599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule163_id2642_at_idx17697() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule164_id2643_at_idx17795() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule165_id2644_at_idx17893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule166_id2645_at_idx17991() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule167_id2646_at_idx18089() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule168_id2647_at_idx18187() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule169_id2648_at_idx18285() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule170_id2649_at_idx18383() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule171_id2650_at_idx18481() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule172_id1138_at_idx18579() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule173_id1139_at_idx18677() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule174_id1140_at_idx18775() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule175_id1141_at_idx18873() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule176_id1142_at_idx18971() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule177_id1143_at_idx19069() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule178_id1144_at_idx19167() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule179_id1145_at_idx19265() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule180_id1146_at_idx19363() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule181_id1147_at_idx19461() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule182_id1148_at_idx19559() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule183_id1149_at_idx19657() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule188_id336_at_idx20127() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule189_id542_at_idx20205() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule192_id1132_at_idx20469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule193_id1133_at_idx20555() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule194_id1134_at_idx20641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule195_id1135_at_idx20727() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule196_id1136_at_idx20813() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule197_id1137_at_idx20899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule198_id2094_at_idx20985() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule199_id2095_at_idx21099() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule200_id758_at_idx21213() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule201_id759_at_idx21315() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule202_id760_at_idx21417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule203_id761_at_idx21519() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule204_id762_at_idx21621() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule205_id763_at_idx21723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule206_id941_at_idx21825() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule207_id942_at_idx21927() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule208_id943_at_idx22029() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule209_id944_at_idx22131() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule210_id945_at_idx22233() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule211_id946_at_idx22335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule213_id2100_at_idx22498() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule214_id2101_at_idx22612() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule215_id2102_at_idx22726() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule216_id2103_at_idx22840() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule217_id148_at_idx22954() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule218_id473_at_idx23032() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule223_id1649_at_idx23422() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule224_id1680_at_idx23500() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule225_id1681_at_idx23572() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule226_id1682_at_idx23644() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule227_id1683_at_idx23716() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule244_id2181_at_idx25036() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule245_id2182_at_idx25114() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule246_id2183_at_idx25192() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule248_id2185_at_idx25348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule249_id2188_at_idx25426() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule250_id2189_at_idx25504() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule251_id2190_at_idx25582() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule253_id2192_at_idx25738() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule322_id770_at_idx30232() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule323_id771_at_idx30298() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule324_id772_at_idx30364() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule325_id773_at_idx30430() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule326_id774_at_idx30496() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule327_id775_at_idx30562() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule328_id776_at_idx30628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule329_id777_at_idx30694() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule330_id778_at_idx30760() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule331_id779_at_idx30826() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule332_id780_at_idx30892() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule333_id781_at_idx30958() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule334_id782_at_idx31024() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule335_id783_at_idx31090() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule336_id784_at_idx31156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule337_id785_at_idx31222() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule338_id786_at_idx31288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule339_id787_at_idx31354() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule340_id788_at_idx31420() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule341_id789_at_idx31486() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule342_id790_at_idx31552() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule343_id791_at_idx31618() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule344_id792_at_idx31684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule345_id793_at_idx31750() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule346_id794_at_idx31816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule347_id795_at_idx31882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule348_id796_at_idx31948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule349_id797_at_idx32014() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule350_id798_at_idx32080() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule351_id799_at_idx32146() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule352_id800_at_idx32212() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule353_id801_at_idx32278() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule354_id802_at_idx32344() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule355_id803_at_idx32410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule356_id804_at_idx32476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule357_id805_at_idx32542() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule358_id806_at_idx32608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule359_id807_at_idx32674() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule360_id808_at_idx32740() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule361_id809_at_idx32806() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule362_id810_at_idx32872() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule363_id811_at_idx32938() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule364_id812_at_idx33004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule365_id819_at_idx33070() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule366_id820_at_idx33136() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule367_id833_at_idx33202() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule368_id834_at_idx33268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule369_id835_at_idx33334() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule370_id836_at_idx33400() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule371_id841_at_idx33466() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule372_id842_at_idx33532() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule373_id843_at_idx33598() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule374_id844_at_idx33664() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule375_id855_at_idx33730() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule376_id856_at_idx33796() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule377_id861_at_idx33856() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule378_id862_at_idx33922() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule379_id953_at_idx33988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule380_id954_at_idx34054() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule381_id955_at_idx34120() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule382_id956_at_idx34186() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule383_id957_at_idx34252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule384_id958_at_idx34318() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule385_id959_at_idx34384() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule386_id960_at_idx34450() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule387_id961_at_idx34516() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule388_id962_at_idx34582() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule389_id963_at_idx34648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule390_id964_at_idx34714() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule391_id965_at_idx34780() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule392_id966_at_idx34846() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule393_id967_at_idx34912() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule394_id968_at_idx34978() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule395_id969_at_idx35044() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule396_id970_at_idx35110() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule397_id971_at_idx35176() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule398_id972_at_idx35242() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule399_id973_at_idx35308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule400_id974_at_idx35374() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule401_id975_at_idx35440() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule402_id976_at_idx35506() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule403_id977_at_idx35572() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule404_id978_at_idx35638() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule405_id979_at_idx35704() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule406_id980_at_idx35770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule407_id981_at_idx35836() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule408_id982_at_idx35902() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule409_id983_at_idx35968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule410_id1076_at_idx36034() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule411_id1077_at_idx36100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule412_id1078_at_idx36166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule413_id1079_at_idx36232() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule414_id1080_at_idx36298() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule415_id1081_at_idx36364() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule416_id1082_at_idx36430() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule417_id1083_at_idx36496() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule418_id1116_at_idx36562() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule419_id1117_at_idx36628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule420_id1118_at_idx36694() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule421_id1119_at_idx36760() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule422_id1120_at_idx36826() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule423_id1121_at_idx36892() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule424_id1122_at_idx36958() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule425_id1123_at_idx37024() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule426_id1124_at_idx37090() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule427_id1125_at_idx37156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule428_id1126_at_idx37222() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule429_id1127_at_idx37288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule430_id1128_at_idx37354() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule431_id1129_at_idx37420() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule432_id1130_at_idx37486() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule433_id1131_at_idx37552() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule434_id1196_at_idx37618() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule435_id1197_at_idx37684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule436_id1198_at_idx37750() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule437_id1199_at_idx37816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule438_id1200_at_idx37882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule439_id1213_at_idx37948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule440_id1214_at_idx38014() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule441_id1215_at_idx38080() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule442_id1216_at_idx38146() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule443_id1217_at_idx38212() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule444_id1218_at_idx38278() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule445_id1219_at_idx38344() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule446_id1220_at_idx38410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule447_id1221_at_idx38476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule448_id1222_at_idx38542() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule449_id1223_at_idx38608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule450_id1224_at_idx38674() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule451_id1225_at_idx38740() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule452_id1226_at_idx38806() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule453_id1227_at_idx38872() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule454_id1228_at_idx38938() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule455_id1229_at_idx39004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule456_id1230_at_idx39070() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule457_id1231_at_idx39136() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule458_id1232_at_idx39202() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule459_id1233_at_idx39268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule460_id1234_at_idx39334() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule461_id1235_at_idx39400() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule462_id1236_at_idx39466() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule463_id1237_at_idx39532() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule464_id1238_at_idx39598() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule465_id1239_at_idx39664() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule466_id1240_at_idx39730() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule467_id1247_at_idx39796() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule468_id1248_at_idx39862() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule469_id1249_at_idx39928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule470_id1250_at_idx39994() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule471_id1257_at_idx40060() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule472_id1258_at_idx40126() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule473_id1259_at_idx40192() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule474_id1260_at_idx40258() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule475_id1261_at_idx40324() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule476_id1262_at_idx40390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule477_id1263_at_idx40456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule478_id1264_at_idx40522() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule479_id1265_at_idx40588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule480_id1266_at_idx40654() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule481_id1267_at_idx40720() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule482_id1268_at_idx40786() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule483_id1269_at_idx40852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule484_id1270_at_idx40918() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule485_id1271_at_idx40984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule486_id1272_at_idx41050() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule487_id1273_at_idx41116() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule488_id1274_at_idx41182() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule489_id1275_at_idx41248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule490_id1276_at_idx41314() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule491_id1310_at_idx41380() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule492_id1311_at_idx41446() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule493_id1312_at_idx41512() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule494_id1313_at_idx41578() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule495_id1314_at_idx41644() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule496_id1315_at_idx41710() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule497_id1316_at_idx41776() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule498_id1317_at_idx41842() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule499_id1318_at_idx41908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule500_id1319_at_idx41974() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule501_id1320_at_idx42040() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule502_id1321_at_idx42106() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule503_id1322_at_idx42172() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule504_id1323_at_idx42238() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule505_id1324_at_idx42304() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule506_id1325_at_idx42370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule507_id1345_at_idx42436() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule508_id1346_at_idx42502() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule509_id1347_at_idx42568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule510_id1348_at_idx42634() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule511_id1349_at_idx42700() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule512_id1350_at_idx42766() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule513_id1351_at_idx42832() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule514_id1352_at_idx42898() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule515_id1353_at_idx42964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule516_id1354_at_idx43030() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule517_id1355_at_idx43096() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule518_id1356_at_idx43162() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule519_id1357_at_idx43228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule520_id1358_at_idx43294() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule521_id1359_at_idx43360() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule522_id1360_at_idx43426() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule523_id1394_at_idx43492() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule524_id1395_at_idx43558() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule525_id1396_at_idx43624() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule526_id1397_at_idx43690() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule527_id1398_at_idx43756() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule528_id1399_at_idx43822() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule529_id1400_at_idx43888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule530_id1401_at_idx43954() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule531_id1402_at_idx44020() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule532_id1403_at_idx44086() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule533_id1404_at_idx44152() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule534_id1405_at_idx44218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule535_id1406_at_idx44284() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule536_id1407_at_idx44350() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule537_id1408_at_idx44416() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule538_id1409_at_idx44482() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule539_id1674_at_idx44548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule540_id1675_at_idx44608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule541_id1678_at_idx44668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule542_id1679_at_idx44728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule564_id3_at_idx46183() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule565_id123_at_idx46253() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule566_id124_at_idx46323() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule567_id125_at_idx46393() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule568_id126_at_idx46463() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule569_id127_at_idx46533() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule570_id128_at_idx46603() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule571_id129_at_idx46673() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule572_id130_at_idx46743() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule573_id131_at_idx46813() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule574_id132_at_idx46883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule575_id133_at_idx46953() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule576_id134_at_idx47023() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule577_id435_at_idx47093() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule578_id448_at_idx47163() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule579_id449_at_idx47233() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule580_id450_at_idx47303() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule581_id451_at_idx47373() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule582_id452_at_idx47443() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule583_id453_at_idx47513() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule584_id454_at_idx47583() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule585_id455_at_idx47653() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule586_id456_at_idx47723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule587_id457_at_idx47793() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule588_id458_at_idx47863() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule589_id459_at_idx47933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule590_id351_at_idx48003() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule591_id352_at_idx48061() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule596_id1201_at_idx48335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule597_id1202_at_idx48389() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule598_id1203_at_idx48443() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule599_id1204_at_idx48497() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule600_id1205_at_idx48551() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule601_id1206_at_idx48605() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule602_id1207_at_idx48659() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule603_id1208_at_idx48713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule604_id1209_at_idx48767() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule605_id1210_at_idx48821() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule606_id1211_at_idx48875() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule607_id1212_at_idx48929() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule608_id1241_at_idx48983() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule609_id1242_at_idx49037() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule610_id1243_at_idx49091() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule611_id1244_at_idx49145() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule612_id1245_at_idx49199() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule613_id1246_at_idx49253() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule614_id1251_at_idx49307() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule615_id1252_at_idx49361() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule616_id1253_at_idx49415() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule617_id1254_at_idx49469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule618_id1255_at_idx49523() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule619_id1256_at_idx49577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule620_id1477_at_idx49631() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule621_id1478_at_idx49685() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule622_id1479_at_idx49739() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule623_id1480_at_idx49793() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule624_id1481_at_idx49847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule625_id1482_at_idx49901() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule626_id1493_at_idx49955() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule627_id1494_at_idx50009() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule628_id1495_at_idx50063() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule629_id1496_at_idx50117() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule630_id1497_at_idx50171() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule631_id1498_at_idx50225() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule632_id1499_at_idx50279() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule633_id1500_at_idx50333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule634_id1501_at_idx50387() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule635_id1502_at_idx50441() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule636_id1503_at_idx50495() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule637_id1504_at_idx50549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule638_id1548_at_idx50603() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule639_id1549_at_idx50657() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule640_id1550_at_idx50711() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule641_id1551_at_idx50765() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule642_id1552_at_idx50819() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule643_id1553_at_idx50873() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule644_id1554_at_idx50927() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule645_id1555_at_idx50981() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule646_id1556_at_idx51035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule647_id1579_at_idx51089() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule648_id1580_at_idx51137() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule649_id1581_at_idx51185() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule650_id1582_at_idx51233() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule651_id1583_at_idx51281() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule652_id1584_at_idx51329() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule653_id1585_at_idx51377() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule654_id1586_at_idx51425() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule655_id1587_at_idx51473() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule656_id1588_at_idx51521() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule657_id1589_at_idx51569() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule658_id1590_at_idx51617() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule659_id1591_at_idx51665() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule660_id1592_at_idx51713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule661_id1593_at_idx51761() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule662_id1594_at_idx51809() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule663_id1595_at_idx51857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule664_id1596_at_idx51905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule665_id1597_at_idx51953() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule666_id1598_at_idx52001() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule667_id1599_at_idx52049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule668_id1600_at_idx52097() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule669_id1601_at_idx52145() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule670_id1602_at_idx52193() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule671_id1603_at_idx52241() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule672_id1604_at_idx52289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule673_id1605_at_idx52337() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule674_id1606_at_idx52385() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule675_id1607_at_idx52433() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule676_id1608_at_idx52481() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule677_id1609_at_idx52529() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule678_id1610_at_idx52577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule679_id1627_at_idx52625() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule680_id1628_at_idx52679() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule681_id1650_at_idx52733() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule682_id1651_at_idx52781() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule683_id1652_at_idx52829() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule684_id1653_at_idx52877() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule685_id1654_at_idx52925() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule686_id1655_at_idx52973() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule687_id1656_at_idx53021() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule688_id1657_at_idx53069() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule689_id1658_at_idx53117() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule690_id1659_at_idx53165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule691_id1660_at_idx53213() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule692_id1661_at_idx53261() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule693_id1662_at_idx53309() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule694_id1663_at_idx53357() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule695_id1664_at_idx53405() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule696_id1665_at_idx53453() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule697_id1666_at_idx53501() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule698_id1667_at_idx53549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule699_id1668_at_idx53597() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule700_id1669_at_idx53645() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule701_id1670_at_idx53693() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule702_id1671_at_idx53741() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule703_id1672_at_idx53789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule704_id1673_at_idx53837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule705_id1676_at_idx53885() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule706_id1677_at_idx53933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule712_id715_at_idx54278() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule713_id716_at_idx54324() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule714_id254_at_idx54370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule715_id587_at_idx54398() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule716_id74_at_idx54432() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule717_id411_at_idx54511() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule718_id412_at_idx54590() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule724_id98_at_idx55061() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule725_id431_at_idx55140() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule731_id2086_at_idx55611() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule732_id2087_at_idx55705() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule733_id2174_at_idx55799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule734_id2175_at_idx55893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule735_id2088_at_idx55987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule736_id2089_at_idx56081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule737_id2098_at_idx56175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule738_id2099_at_idx56269() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule742_id2569_at_idx56651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule743_id2570_at_idx56745() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule744_id2571_at_idx56839() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule745_id2572_at_idx56933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule746_id2573_at_idx57027() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule747_id2574_at_idx57121() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule748_id2545_at_idx57215() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule749_id2546_at_idx57297() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule750_id2547_at_idx57379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule751_id2548_at_idx57461() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule752_id2549_at_idx57543() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule753_id2550_at_idx57625() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule754_id865_at_idx57707() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule755_id866_at_idx57801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule756_id867_at_idx57895() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule757_id868_at_idx57989() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule758_id869_at_idx58083() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule759_id870_at_idx58177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule763_id764_at_idx58559() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule764_id765_at_idx58641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule765_id766_at_idx58723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule766_id767_at_idx58805() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule767_id768_at_idx58887() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule768_id769_at_idx58969() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule769_id2623_at_idx59051() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule770_id2624_at_idx59145() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule771_id923_at_idx59239() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule772_id924_at_idx59333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule773_id2029_at_idx59427() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule774_id2030_at_idx59509() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule775_id2736_at_idx59591() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule776_id2737_at_idx59673() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule777_id901_at_idx59755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule778_id902_at_idx59849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule779_id927_at_idx59943() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule780_id928_at_idx60037() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule783_id893_at_idx60319() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule784_id894_at_idx60413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule785_id895_at_idx60507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule786_id896_at_idx60601() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule787_id897_at_idx60695() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule788_id898_at_idx60789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule789_id947_at_idx60883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule790_id948_at_idx60965() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule791_id949_at_idx61047() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule792_id950_at_idx61129() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule793_id951_at_idx61211() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule794_id952_at_idx61293() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule795_id2092_at_idx61375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule796_id2093_at_idx61469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule797_id630_at_idx61563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule798_id631_at_idx61645() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule804_id2081_at_idx61991() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule805_id2082_at_idx62065() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule806_id2172_at_idx62139() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule807_id2173_at_idx62213() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule808_id75_at_idx62287() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule809_id413_at_idx62352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule810_id746_at_idx62417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule811_id747_at_idx62479() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule812_id748_at_idx62541() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule813_id749_at_idx62603() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule814_id750_at_idx62665() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule815_id751_at_idx62727() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule816_id752_at_idx62789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule817_id753_at_idx62851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule818_id2503_at_idx62913() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule821_id1090_at_idx63108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule822_id1091_at_idx63170() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule824_id618_at_idx63297() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule825_id619_at_idx63359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule827_id754_at_idx63483() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule828_id755_at_idx63545() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule829_id756_at_idx63607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule830_id757_at_idx63669() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule831_id624_at_idx63731() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule832_id625_at_idx63793() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule834_id627_at_idx63917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule835_id628_at_idx63979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule837_id821_at_idx64103() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule838_id822_at_idx64165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule839_id823_at_idx64227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule840_id824_at_idx64289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule841_id621_at_idx64351() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule842_id622_at_idx64413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule844_id937_at_idx64537() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule845_id938_at_idx64599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule846_id939_at_idx64661() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule847_id940_at_idx64723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule849_id171_at_idx64850() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule850_id172_at_idx64915() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule851_id506_at_idx64980() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule852_id813_at_idx65042() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule853_id814_at_idx65104() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule854_id815_at_idx65166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule855_id816_at_idx65228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule856_id817_at_idx65290() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule857_id818_at_idx65352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule860_id1094_at_idx65544() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule861_id1095_at_idx65606() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule862_id197_at_idx65668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule863_id536_at_idx65730() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule867_id929_at_idx65987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule868_id930_at_idx66049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule869_id931_at_idx66111() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule870_id932_at_idx66173() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule871_id933_at_idx66235() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule872_id934_at_idx66297() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule873_id935_at_idx66359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule874_id936_at_idx66421() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule875_id198_at_idx66483() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule876_id537_at_idx66545() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule879_id1092_at_idx66737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule880_id1093_at_idx66799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule881_id2253_at_idx66861() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule882_id2254_at_idx66909() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule883_id2255_at_idx66957() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule884_id678_at_idx67005() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule885_id679_at_idx67055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule886_id2295_at_idx67105() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule887_id2296_at_idx67151() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule888_id2297_at_idx67197() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule889_id2298_at_idx67243() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule891_id2300_at_idx67333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule892_id2301_at_idx67379() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule893_id2302_at_idx67425() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule895_id2304_at_idx67517() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule896_id2305_at_idx67561() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule897_id2306_at_idx67607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule898_id2307_at_idx67653() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule901_id2310_at_idx67791() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule902_id2311_at_idx67837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule903_id2312_at_idx67883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule916_id2325_at_idx68477() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule917_id2326_at_idx68523() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule918_id2327_at_idx68569() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule919_id2328_at_idx68615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule921_id2330_at_idx68705() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule922_id2331_at_idx68751() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule923_id2332_at_idx68797() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule925_id2334_at_idx68889() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule926_id2335_at_idx68933() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule927_id2336_at_idx68979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule928_id2337_at_idx69025() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule931_id2340_at_idx69163() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule932_id2341_at_idx69209() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule933_id2342_at_idx69255() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule946_id2355_at_idx69849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule947_id2356_at_idx69899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule948_id2357_at_idx69949() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule950_id2359_at_idx70049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule951_id2360_at_idx70099() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule952_id2361_at_idx70149() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule954_id2363_at_idx70249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule955_id2364_at_idx70299() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule956_id2365_at_idx70349() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule959_id2368_at_idx70499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule960_id2369_at_idx70549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule961_id2370_at_idx70599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule972_id2381_at_idx71149() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule973_id2382_at_idx71199() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule974_id2383_at_idx71249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule976_id2385_at_idx71349() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule977_id2386_at_idx71399() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule978_id2387_at_idx71449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule980_id2389_at_idx71549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule981_id2390_at_idx71599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule982_id2391_at_idx71649() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule985_id2394_at_idx71799() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule986_id2395_at_idx71849() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule987_id2396_at_idx71899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule998_id201_at_idx72449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule999_id334_at_idx72499() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1000_id540_at_idx72549() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1002_id661_at_idx72634() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1003_id662_at_idx72684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1005_id1489_at_idx72784() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1006_id1490_at_idx72834() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1007_id1491_at_idx72884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1008_id1492_at_idx72934() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1009_id659_at_idx72984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1012_id1563_at_idx73166() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1013_id1567_at_idx73216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1014_id1571_at_idx73266() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1015_id1575_at_idx73316() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1016_id2053_at_idx73366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1017_id2055_at_idx73434() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1019_id1564_at_idx73570() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1020_id1568_at_idx73620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1021_id1572_at_idx73670() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1022_id1576_at_idx73720() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1023_id2058_at_idx73770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1024_id2060_at_idx73838() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1026_id660_at_idx73974() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1029_id1557_at_idx74160() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1030_id1558_at_idx74210() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1031_id1559_at_idx74260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1032_id1565_at_idx74310() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1033_id1569_at_idx74360() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1034_id1573_at_idx74410() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1035_id1577_at_idx74460() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1036_id2043_at_idx74510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1037_id2045_at_idx74576() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1039_id1545_at_idx74708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1040_id1546_at_idx74758() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1041_id1547_at_idx74808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1042_id1566_at_idx74858() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1043_id1570_at_idx74908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1044_id1574_at_idx74958() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1045_id1578_at_idx75008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1046_id2048_at_idx75058() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1047_id2050_at_idx75124() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1049_id1560_at_idx75256() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1050_id1561_at_idx75306() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1051_id1562_at_idx75356() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1052_id34_at_idx75406() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1053_id291_at_idx75428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1054_id590_at_idx75461() {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            test_return
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_return
+    ; SELECTED: $noreg = PATCHABLE_RET
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule0_id2693_at_idx0
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule0_id2693_at_idx0
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %10:gprb(s32) = G_CONSTANT 24
+    %5:gprb(s32) = G_CONSTANT 255
+    %7:gprb(s32) = G_CONSTANT 8
+    %3:gprb(s32) = G_SHL %9, %10
+    %2:gprb(s32) = G_ASHR %3, %8
+    %1:gprb(s32) = G_LSHR %9, %7
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule1_id2724_at_idx167
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+  - { id: 7, class: gprb }
+  - { id: 8, class: gprb }
+  - { id: 9, class: gprb }
+  - { id: 10, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%9' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1_id2724_at_idx167
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %9:gprb(s32) = COPY $lr
+    %8:gprb(s32) = G_CONSTANT 16
+    %10:gprb(s32) = G_CONSTANT 24
+    %5:gprb(s32) = G_CONSTANT 255
+    %7:gprb(s32) = G_CONSTANT 8
+    %3:gprb(s32) = G_SHL %9, %10
+    %2:gprb(s32) = G_ASHR %3, %8
+    %1:gprb(s32) = G_LSHR %9, %7
+    %0:gprb(s32) = G_AND %1, %5
+    %4:gprb(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %4(s32)
+
+...
+---
+name:            test_rule4_id1713_at_idx668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule4_id1713_at_idx668
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %4:gprb(s32) = G_CONSTANT 8
+    %0:gprb(s32) = G_LSHR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule5_id1912_at_idx757
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule5_id1912_at_idx757
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %4:gprb(s32) = G_CONSTANT 8
+    %0:gprb(s32) = G_LSHR %3, %4
+    %1:gprb(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule6_id2704_at_idx846
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule6_id2704_at_idx846
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule7_id2705_at_idx939
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule7_id2705_at_idx939
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule8_id2732_at_idx1032
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule8_id2732_at_idx1032
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule9_id2733_at_idx1125
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule9_id2733_at_idx1125
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule10_id1819_at_idx1218
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule10_id1819_at_idx1218
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule11_id1820_at_idx1311
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule11_id1820_at_idx1311
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule12_id1999_at_idx1404
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule12_id1999_at_idx1404
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAB:%[0-9]+]]:gprnopc = UXTAB [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAB]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule13_id2000_at_idx1497
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+  - { reg: '$r0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule13_id2000_at_idx1497
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UXTAH:%[0-9]+]]:gprnopc = UXTAH [[COPY1]], [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTAH]]
+    %3:gprb(s32) = COPY $r0
+    %2:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %3, %4
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule14_id255_at_idx1590
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule14_id255_at_idx1590
+    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule15_id256_at_idx1768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule15_id256_at_idx1768
+    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule16_id610_at_idx1940
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule16_id610_at_idx1940
+    ; SELECTED: CDP 1, 1, 1, 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule17_id611_at_idx2118
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule17_id611_at_idx2118
+    ; SELECTED: CDP2 1, 1, 1, 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = G_CONSTANT 1
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule31_id1816_at_idx4333
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule31_id1816_at_idx4333
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule32_id1817_at_idx4394
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule32_id1817_at_idx4394
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule33_id1818_at_idx4455
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule33_id1818_at_idx4455
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule34_id1996_at_idx4516
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule34_id1996_at_idx4516
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule35_id1997_at_idx4577
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule35_id1997_at_idx4577
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule36_id1998_at_idx4638
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule36_id1998_at_idx4638
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16711935
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule37_id1714_at_idx4699
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule37_id1714_at_idx4699
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule38_id1911_at_idx4756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule38_id1911_at_idx4756
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB16_:%[0-9]+]]:gprnopc = UXTB16 [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB16_]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule43_id265_at_idx5471
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule43_id265_at_idx5471
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule44_id266_at_idx5637
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule44_id266_at_idx5637
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule45_id606_at_idx5797
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule45_id606_at_idx5797
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR 1, 1, [[COPY]], 1, 1, 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule46_id607_at_idx5963
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule46_id607_at_idx5963
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: MCR2 1, 1, [[COPY]], 1, 1, 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %5:gprb(s32) = COPY $lr
+    %4:gprb(s32) = G_CONSTANT 1
+    %3:gprb(s32) = G_CONSTANT 1
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule51_id188_at_idx6729
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule51_id188_at_idx6729
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 16
+    %4:gprb(s32) = G_CONSTANT 16
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_ASHR %3, %4
+    %2:gprb(s32) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule52_id519_at_idx6847
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+  - { id: 5, class: gprb }
+  - { id: 6, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule52_id519_at_idx6847
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SMULTT:%[0-9]+]]:gpr = SMULTT [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULTT]]
+    %5:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %6:gprb(s32) = G_CONSTANT 16
+    %4:gprb(s32) = G_CONSTANT 16
+    %1:gprb(s32) = G_ASHR %5, %6
+    %0:gprb(s32) = G_ASHR %3, %4
+    %2:gprb(s32) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule69_id267_at_idx9081
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule69_id267_at_idx9081
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule70_id268_at_idx9211
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule70_id268_at_idx9211
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule71_id608_at_idx9335
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule71_id608_at_idx9335
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR 1, 1, [[COPY1]], [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule72_id609_at_idx9465
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+  - { reg: '$r0', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule72_id609_at_idx9465
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: MCRR2 1, 1, [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %4:gprb(s32) = COPY $r0
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_CONSTANT 1
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule73_id2758_at_idx9595
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule73_id2758_at_idx9595
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule74_id2759_at_idx9697
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule74_id2759_at_idx9697
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule75_id2760_at_idx9799
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule75_id2760_at_idx9799
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule76_id2761_at_idx9901
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule76_id2761_at_idx9901
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule77_id2778_at_idx10003
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: _ }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule77_id2778_at_idx10003
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<4 x s32>), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule78_id2779_at_idx10103
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: _ }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule78_id2779_at_idx10103
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[INT]](<2 x s64>), [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %4:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule81_id2145_at_idx10393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule81_id2145_at_idx10393
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv4i16_:%[0-9]+]]:dpr = VQRDMLAHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule82_id2146_at_idx10495
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule82_id2146_at_idx10495
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLAHv2i32_:%[0-9]+]]:dpr = VQRDMLAHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLAHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule83_id2147_at_idx10597
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule83_id2147_at_idx10597
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<8 x s16>), [[INT]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule84_id2148_at_idx10699
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule84_id2148_at_idx10699
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule85_id2153_at_idx10801
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule85_id2153_at_idx10801
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLSHv4i16_:%[0-9]+]]:dpr = VQRDMLSHv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule86_id2154_at_idx10903
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule86_id2154_at_idx10903
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMLSHv2i32_:%[0-9]+]]:dpr = VQRDMLSHv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMLSHv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule87_id2155_at_idx11005
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule87_id2155_at_idx11005
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<8 x s16>), [[INT]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule88_id2156_at_idx11107
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule88_id2156_at_idx11107
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule89_id2161_at_idx11209
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule89_id2161_at_idx11209
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule90_id2162_at_idx11309
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule90_id2162_at_idx11309
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<2 x s64>), [[INT]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule91_id2168_at_idx11409
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule91_id2168_at_idx11409
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[INT]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule92_id2169_at_idx11509
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule92_id2169_at_idx11509
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[INT1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<2 x s64>), [[INT]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT1]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule97_id203_at_idx11989
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule97_id203_at_idx11989
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule110_id2651_at_idx13351
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule110_id2651_at_idx13351
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule111_id2652_at_idx13469
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule111_id2652_at_idx13469
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule112_id2653_at_idx13587
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule112_id2653_at_idx13587
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:_(<2 x s64>) = IMPLICIT_DEF
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule113_id2654_at_idx13705
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule113_id2654_at_idx13705
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule114_id2655_at_idx13823
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule114_id2655_at_idx13823
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule115_id2656_at_idx13941
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule115_id2656_at_idx13941
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:_(<2 x s64>) = IMPLICIT_DEF
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule116_id1150_at_idx14059
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule116_id1150_at_idx14059
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule117_id1151_at_idx14177
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule117_id1151_at_idx14177
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule118_id1152_at_idx14295
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule118_id1152_at_idx14295
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:_(<2 x s64>) = IMPLICIT_DEF
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule119_id1153_at_idx14413
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule119_id1153_at_idx14413
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %5:fprb(<8 x s8>) = COPY $d17
+    %4:fprb(<8 x s8>) = COPY $d16
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule120_id1154_at_idx14531
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule120_id1154_at_idx14531
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %5:fprb(<4 x s16>) = COPY $d17
+    %4:fprb(<4 x s16>) = COPY $d16
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule121_id1155_at_idx14649
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%4' }
+  - { reg: '$d17', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule121_id1155_at_idx14649
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %5:fprb(<2 x s32>) = COPY $d17
+    %4:fprb(<2 x s32>) = COPY $d16
+    %3:_(<2 x s64>) = IMPLICIT_DEF
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule124_id350_at_idx14917
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule124_id350_at_idx14917
+    ; SELECTED: t__brkdiv0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 249
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule129_id2_at_idx15279
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule129_id2_at_idx15279
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule130_id10_at_idx15340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule130_id10_at_idx15340
+    ; SELECTED: DBG 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule131_id11_at_idx15401
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule131_id11_at_idx15401
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule132_id237_at_idx15456
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule132_id237_at_idx15456
+    ; SELECTED: DMB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule133_id238_at_idx15511
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule133_id238_at_idx15511
+    ; SELECTED: DSB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule134_id239_at_idx15566
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule134_id239_at_idx15566
+    ; SELECTED: ISB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule135_id285_at_idx15621
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule135_id285_at_idx15621
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule136_id349_at_idx15682
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule136_id349_at_idx15682
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule137_id498_at_idx15737
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule137_id498_at_idx15737
+    ; SELECTED: UDF 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule138_id572_at_idx15792
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule138_id572_at_idx15792
+    ; SELECTED: DMB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule139_id573_at_idx15853
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule139_id573_at_idx15853
+    ; SELECTED: DSB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule140_id574_at_idx15914
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule140_id574_at_idx15914
+    ; SELECTED: ISB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule141_id592_at_idx15975
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule141_id592_at_idx15975
+    ; SELECTED: HINT 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule142_id593_at_idx16036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule142_id593_at_idx16036
+    ; SELECTED: DBG 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule143_id1611_at_idx16097
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule143_id1611_at_idx16097
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2xsd:%[0-9]+]]:dpr = VCVTf2xsd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xsd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule144_id1612_at_idx16174
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule144_id1612_at_idx16174
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2xud:%[0-9]+]]:dpr = VCVTf2xud [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2xud]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule145_id1613_at_idx16251
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule145_id1613_at_idx16251
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxs2fd:%[0-9]+]]:dpr = VCVTxs2fd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2fd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule146_id1614_at_idx16328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule146_id1614_at_idx16328
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxu2fd:%[0-9]+]]:dpr = VCVTxu2fd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2fd]]
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule147_id1615_at_idx16405
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule147_id1615_at_idx16405
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2xsd:%[0-9]+]]:dpr = VCVTh2xsd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xsd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule148_id1616_at_idx16482
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule148_id1616_at_idx16482
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2xud:%[0-9]+]]:dpr = VCVTh2xud [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2xud]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule149_id1617_at_idx16559
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule149_id1617_at_idx16559
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxs2hd:%[0-9]+]]:dpr = VCVTxs2hd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxs2hd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule150_id1618_at_idx16636
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule150_id1618_at_idx16636
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTxu2hd:%[0-9]+]]:dpr = VCVTxu2hd [[COPY]], 1, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTxu2hd]]
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s32) = G_CONSTANT 1
+    %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule151_id1619_at_idx16713
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule151_id1619_at_idx16713
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), [[DEF]](<4 x s32>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule152_id1620_at_idx16790
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule152_id1620_at_idx16790
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), [[DEF]](<4 x s32>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule153_id1621_at_idx16867
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule153_id1621_at_idx16867
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), [[DEF]](<4 x s32>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule154_id1622_at_idx16944
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule154_id1622_at_idx16944
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), [[DEF]](<4 x s32>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule155_id1623_at_idx17021
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule155_id1623_at_idx17021
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), [[DEF]](<8 x s16>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule156_id1624_at_idx17098
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule156_id1624_at_idx17098
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), [[DEF]](<8 x s16>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule157_id1625_at_idx17175
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule157_id1625_at_idx17175
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), [[DEF]](<8 x s16>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule158_id1626_at_idx17252
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule158_id1626_at_idx17252
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT 1
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), [[DEF]](<8 x s16>), [[C]](s32)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule159_id1684_at_idx17329
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule159_id1684_at_idx17329
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SPACE:%[0-9]+]]:gpr = SPACE 1, [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SPACE]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule160_id2639_at_idx17403
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule160_id2639_at_idx17403
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule161_id2640_at_idx17501
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule161_id2640_at_idx17501
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule162_id2641_at_idx17599
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule162_id2641_at_idx17599
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule163_id2642_at_idx17697
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule163_id2642_at_idx17697
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+    %1:_(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule164_id2643_at_idx17795
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule164_id2643_at_idx17795
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule165_id2644_at_idx17893
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule165_id2644_at_idx17893
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule166_id2645_at_idx17991
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule166_id2645_at_idx17991
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule167_id2646_at_idx18089
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule167_id2646_at_idx18089
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule168_id2647_at_idx18187
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule168_id2647_at_idx18187
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule169_id2648_at_idx18285
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule169_id2648_at_idx18285
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+    %1:_(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule170_id2649_at_idx18383
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule170_id2649_at_idx18383
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule171_id2650_at_idx18481
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule171_id2650_at_idx18481
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[INT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule172_id1138_at_idx18579
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule172_id1138_at_idx18579
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv8i8_:%[0-9]+]]:dpr = VABAsv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule173_id1139_at_idx18677
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule173_id1139_at_idx18677
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv4i16_:%[0-9]+]]:dpr = VABAsv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule174_id1140_at_idx18775
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule174_id1140_at_idx18775
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAsv2i32_:%[0-9]+]]:dpr = VABAsv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAsv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule175_id1141_at_idx18873
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule175_id1141_at_idx18873
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+    %1:_(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule176_id1142_at_idx18971
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule176_id1142_at_idx18971
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule177_id1143_at_idx19069
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule177_id1143_at_idx19069
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule178_id1144_at_idx19167
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule178_id1144_at_idx19167
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv8i8_:%[0-9]+]]:dpr = VABAuv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fprb(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule179_id1145_at_idx19265
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule179_id1145_at_idx19265
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv4i16_:%[0-9]+]]:dpr = VABAuv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fprb(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule180_id1146_at_idx19363
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule180_id1146_at_idx19363
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABAuv2i32_:%[0-9]+]]:dpr = VABAuv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABAuv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fprb(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule181_id1147_at_idx19461
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule181_id1147_at_idx19461
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+    %1:_(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule182_id1148_at_idx19559
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule182_id1148_at_idx19559
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+    %1:_(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule183_id1149_at_idx19657
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule183_id1149_at_idx19657
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[INT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+    %1:_(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule188_id336_at_idx20127
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule188_id336_at_idx20127
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule189_id542_at_idx20205
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule189_id542_at_idx20205
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REVSH:%[0-9]+]]:gpr = REVSH [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVSH]]
+    %3:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 16
+    %0:gprb(s32) = G_BSWAP %3
+    %1:gprb(s32) = G_ASHR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule192_id1132_at_idx20469
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule192_id1132_at_idx20469
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule193_id1133_at_idx20555
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule193_id1133_at_idx20555
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule194_id1134_at_idx20641
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule194_id1134_at_idx20641
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule195_id1135_at_idx20727
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule195_id1135_at_idx20727
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[INT]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule196_id1136_at_idx20813
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule196_id1136_at_idx20813
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[INT]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule197_id1137_at_idx20899
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule197_id1137_at_idx20899
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[INT]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule198_id2094_at_idx20985
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule198_id2094_at_idx20985
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FNEG %4
+    %2:fprb(s64) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule199_id2095_at_idx21099
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule199_id2095_at_idx21099
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY]], [[COPY1]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FNEG %4
+    %2:fprb(s32) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule200_id758_at_idx21213
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule200_id758_at_idx21213
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule201_id759_at_idx21315
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule201_id759_at_idx21315
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule202_id760_at_idx21417
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule202_id760_at_idx21417
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY1]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule203_id761_at_idx21519
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule203_id761_at_idx21519
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:_(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule204_id762_at_idx21621
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule204_id762_at_idx21621
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:_(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule205_id763_at_idx21723
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule205_id763_at_idx21723
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY1]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:_(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule206_id941_at_idx21825
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule206_id941_at_idx21825
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:_(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule207_id942_at_idx21927
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule207_id942_at_idx21927
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY1]](<4 x s16>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:_(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule208_id943_at_idx22029
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule208_id943_at_idx22029
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[SEXT1:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY1]](<2 x s32>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[SEXT1]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:_(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule209_id944_at_idx22131
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule209_id944_at_idx22131
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %4:fprb(<8 x s8>) = COPY $d17
+    %3:fprb(<8 x s8>) = COPY $d16
+    %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:_(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule210_id945_at_idx22233
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule210_id945_at_idx22233
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %4:fprb(<4 x s16>) = COPY $d17
+    %3:fprb(<4 x s16>) = COPY $d16
+    %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:_(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule211_id946_at_idx22335
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule211_id946_at_idx22335
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ZEXT1:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY1]](<2 x s32>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[ZEXT1]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    %4:fprb(<2 x s32>) = COPY $d17
+    %3:fprb(<2 x s32>) = COPY $d16
+    %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:_(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule213_id2100_at_idx22498
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule213_id2100_at_idx22498
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FMA %1, %3, %4
+    %2:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule214_id2101_at_idx22612
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule214_id2101_at_idx22612
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FMA %1, %3, %4
+    %2:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule215_id2102_at_idx22726
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+  - { reg: '$d17', virtual-reg: '%4' }
+  - { reg: '$d18', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule215_id2102_at_idx22726
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
+    %5:fprb(s64) = COPY $d18
+    %4:fprb(s64) = COPY $d17
+    %3:fprb(s64) = COPY $d16
+    %1:fprb(s64) = G_FNEG %5
+    %0:fprb(s64) = G_FMA %3, %1, %4
+    %2:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule216_id2103_at_idx22840
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+  - { reg: '$s4', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule216_id2103_at_idx22840
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
+    %5:fprb(s32) = COPY $s4
+    %4:fprb(s32) = COPY $s2
+    %3:fprb(s32) = COPY $s0
+    %1:fprb(s32) = G_FNEG %5
+    %0:fprb(s32) = G_FMA %3, %1, %4
+    %2:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule217_id148_at_idx22954
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule217_id148_at_idx22954
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule218_id473_at_idx23032
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+  - { reg: '$r1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0, $r1
+
+    ; SELECTED-LABEL: name: test_rule218_id473_at_idx23032
+    ; SELECTED: liveins: $lr, $r0, $r1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[USADA8_:%[0-9]+]]:gpr = USADA8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USADA8_]]
+    %3:gprb(s32) = COPY $r1
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule223_id1649_at_idx23422
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule223_id1649_at_idx23422
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTBX1_:%[0-9]+]]:dpr = VTBX1 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VTBX1_]]
+    %3:fprb(<8 x s8>) = COPY $d18
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule224_id1680_at_idx23500
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule224_id1680_at_idx23500
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule225_id1681_at_idx23572
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule225_id1681_at_idx23572
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule226_id1682_at_idx23644
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule226_id1682_at_idx23644
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule227_id1683_at_idx23716
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule227_id1683_at_idx23716
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule244_id2181_at_idx25036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule244_id2181_at_idx25036
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<8 x s8>) = COPY $d18
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule245_id2182_at_idx25114
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule245_id2182_at_idx25114
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<4 x s16>) = COPY $d18
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule246_id2183_at_idx25192
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule246_id2183_at_idx25192
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(<2 x s32>) = COPY $d18
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule248_id2185_at_idx25348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule248_id2185_at_idx25348
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VBSLd:%[0-9]+]]:dpr = VBSLd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VBSLd]]
+    %3:fprb(s64) = COPY $d18
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule249_id2188_at_idx25426
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule249_id2188_at_idx25426
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>), [[DEF2]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule250_id2189_at_idx25504
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule250_id2189_at_idx25504
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>), [[DEF2]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule251_id2190_at_idx25582
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule251_id2190_at_idx25582
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>), [[DEF2]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule253_id2192_at_idx25738
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule253_id2192_at_idx25738
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>), [[DEF2]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %3:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule322_id770_at_idx30232
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule322_id770_at_idx30232
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv4i16_:%[0-9]+]]:dpr = VHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule323_id771_at_idx30298
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule323_id771_at_idx30298
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv2i32_:%[0-9]+]]:dpr = VHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule324_id772_at_idx30364
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule324_id772_at_idx30364
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule325_id773_at_idx30430
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule325_id773_at_idx30430
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule326_id774_at_idx30496
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule326_id774_at_idx30496
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDsv8i8_:%[0-9]+]]:dpr = VHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule327_id775_at_idx30562
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule327_id775_at_idx30562
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule328_id776_at_idx30628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule328_id776_at_idx30628
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv4i16_:%[0-9]+]]:dpr = VHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule329_id777_at_idx30694
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule329_id777_at_idx30694
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv2i32_:%[0-9]+]]:dpr = VHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule330_id778_at_idx30760
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule330_id778_at_idx30760
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule331_id779_at_idx30826
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule331_id779_at_idx30826
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule332_id780_at_idx30892
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule332_id780_at_idx30892
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHADDuv8i8_:%[0-9]+]]:dpr = VHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule333_id781_at_idx30958
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule333_id781_at_idx30958
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule334_id782_at_idx31024
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule334_id782_at_idx31024
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv4i16_:%[0-9]+]]:dpr = VRHADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule335_id783_at_idx31090
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule335_id783_at_idx31090
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv2i32_:%[0-9]+]]:dpr = VRHADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule336_id784_at_idx31156
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule336_id784_at_idx31156
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule337_id785_at_idx31222
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule337_id785_at_idx31222
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule338_id786_at_idx31288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule338_id786_at_idx31288
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDsv8i8_:%[0-9]+]]:dpr = VRHADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule339_id787_at_idx31354
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule339_id787_at_idx31354
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule340_id788_at_idx31420
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule340_id788_at_idx31420
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv4i16_:%[0-9]+]]:dpr = VRHADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule341_id789_at_idx31486
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule341_id789_at_idx31486
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv2i32_:%[0-9]+]]:dpr = VRHADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule342_id790_at_idx31552
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule342_id790_at_idx31552
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule343_id791_at_idx31618
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule343_id791_at_idx31618
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule344_id792_at_idx31684
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule344_id792_at_idx31684
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRHADDuv8i8_:%[0-9]+]]:dpr = VRHADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRHADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule345_id793_at_idx31750
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule345_id793_at_idx31750
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule346_id794_at_idx31816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule346_id794_at_idx31816
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv4i16_:%[0-9]+]]:dpr = VQADDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule347_id795_at_idx31882
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule347_id795_at_idx31882
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv2i32_:%[0-9]+]]:dpr = VQADDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule348_id796_at_idx31948
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule348_id796_at_idx31948
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule349_id797_at_idx32014
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule349_id797_at_idx32014
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule350_id798_at_idx32080
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule350_id798_at_idx32080
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv8i8_:%[0-9]+]]:dpr = VQADDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule351_id799_at_idx32146
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule351_id799_at_idx32146
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule352_id800_at_idx32212
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule352_id800_at_idx32212
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDsv1i64_:%[0-9]+]]:dpr = VQADDsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule353_id801_at_idx32278
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule353_id801_at_idx32278
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule354_id802_at_idx32344
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule354_id802_at_idx32344
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv4i16_:%[0-9]+]]:dpr = VQADDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule355_id803_at_idx32410
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule355_id803_at_idx32410
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv2i32_:%[0-9]+]]:dpr = VQADDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule356_id804_at_idx32476
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule356_id804_at_idx32476
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule357_id805_at_idx32542
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule357_id805_at_idx32542
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule358_id806_at_idx32608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule358_id806_at_idx32608
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv8i8_:%[0-9]+]]:dpr = VQADDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule359_id807_at_idx32674
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule359_id807_at_idx32674
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule360_id808_at_idx32740
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule360_id808_at_idx32740
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQADDuv1i64_:%[0-9]+]]:dpr = VQADDuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQADDuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule361_id809_at_idx32806
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule361_id809_at_idx32806
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule362_id810_at_idx32872
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule362_id810_at_idx32872
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule363_id811_at_idx32938
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule363_id811_at_idx32938
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule364_id812_at_idx33004
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule364_id812_at_idx33004
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule365_id819_at_idx33070
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule365_id819_at_idx33070
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULpd:%[0-9]+]]:dpr = VMULpd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULpd]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule366_id820_at_idx33136
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule366_id820_at_idx33136
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule367_id833_at_idx33202
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule367_id833_at_idx33202
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQDMULHv4i16_:%[0-9]+]]:dpr = VQDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule368_id834_at_idx33268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule368_id834_at_idx33268
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQDMULHv2i32_:%[0-9]+]]:dpr = VQDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQDMULHv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule369_id835_at_idx33334
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule369_id835_at_idx33334
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule370_id836_at_idx33400
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule370_id836_at_idx33400
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule371_id841_at_idx33466
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule371_id841_at_idx33466
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMULHv4i16_:%[0-9]+]]:dpr = VQRDMULHv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule372_id842_at_idx33532
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule372_id842_at_idx33532
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRDMULHv2i32_:%[0-9]+]]:dpr = VQRDMULHv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRDMULHv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule373_id843_at_idx33598
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule373_id843_at_idx33598
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule374_id844_at_idx33664
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule374_id844_at_idx33664
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule375_id855_at_idx33730
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule375_id855_at_idx33730
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), [[COPY1]](<8 x s8>), [[COPY]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule376_id856_at_idx33796
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule376_id856_at_idx33796
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), [[COPY1]](s64), [[COPY]](s64)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule377_id861_at_idx33856
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule377_id861_at_idx33856
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<4 x s16>), [[COPY]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule378_id862_at_idx33922
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule378_id862_at_idx33922
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), [[COPY1]](<2 x s32>), [[COPY]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule379_id953_at_idx33988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule379_id953_at_idx33988
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBsv4i16_:%[0-9]+]]:dpr = VHSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule380_id954_at_idx34054
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule380_id954_at_idx34054
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBsv2i32_:%[0-9]+]]:dpr = VHSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule381_id955_at_idx34120
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule381_id955_at_idx34120
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule382_id956_at_idx34186
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule382_id956_at_idx34186
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule383_id957_at_idx34252
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule383_id957_at_idx34252
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBsv8i8_:%[0-9]+]]:dpr = VHSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule384_id958_at_idx34318
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule384_id958_at_idx34318
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule385_id959_at_idx34384
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule385_id959_at_idx34384
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBuv4i16_:%[0-9]+]]:dpr = VHSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule386_id960_at_idx34450
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule386_id960_at_idx34450
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBuv2i32_:%[0-9]+]]:dpr = VHSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule387_id961_at_idx34516
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule387_id961_at_idx34516
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule388_id962_at_idx34582
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule388_id962_at_idx34582
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule389_id963_at_idx34648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule389_id963_at_idx34648
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VHSUBuv8i8_:%[0-9]+]]:dpr = VHSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VHSUBuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule390_id964_at_idx34714
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule390_id964_at_idx34714
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule391_id965_at_idx34780
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule391_id965_at_idx34780
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBsv4i16_:%[0-9]+]]:dpr = VQSUBsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule392_id966_at_idx34846
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule392_id966_at_idx34846
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBsv2i32_:%[0-9]+]]:dpr = VQSUBsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule393_id967_at_idx34912
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule393_id967_at_idx34912
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule394_id968_at_idx34978
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule394_id968_at_idx34978
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule395_id969_at_idx35044
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule395_id969_at_idx35044
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBsv8i8_:%[0-9]+]]:dpr = VQSUBsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule396_id970_at_idx35110
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule396_id970_at_idx35110
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule397_id971_at_idx35176
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule397_id971_at_idx35176
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBsv1i64_:%[0-9]+]]:dpr = VQSUBsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule398_id972_at_idx35242
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule398_id972_at_idx35242
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule399_id973_at_idx35308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule399_id973_at_idx35308
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBuv4i16_:%[0-9]+]]:dpr = VQSUBuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule400_id974_at_idx35374
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule400_id974_at_idx35374
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBuv2i32_:%[0-9]+]]:dpr = VQSUBuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule401_id975_at_idx35440
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule401_id975_at_idx35440
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule402_id976_at_idx35506
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule402_id976_at_idx35506
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule403_id977_at_idx35572
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule403_id977_at_idx35572
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBuv8i8_:%[0-9]+]]:dpr = VQSUBuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule404_id978_at_idx35638
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule404_id978_at_idx35638
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule405_id979_at_idx35704
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule405_id979_at_idx35704
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSUBuv1i64_:%[0-9]+]]:dpr = VQSUBuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSUBuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule406_id980_at_idx35770
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule406_id980_at_idx35770
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule407_id981_at_idx35836
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule407_id981_at_idx35836
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule408_id982_at_idx35902
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule408_id982_at_idx35902
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule409_id983_at_idx35968
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule409_id983_at_idx35968
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule410_id1076_at_idx36034
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule410_id1076_at_idx36034
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VACGEfd:%[0-9]+]]:dpr = VACGEfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule411_id1077_at_idx36100
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule411_id1077_at_idx36100
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule412_id1078_at_idx36166
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule412_id1078_at_idx36166
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VACGEhd:%[0-9]+]]:dpr = VACGEhd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGEhd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule413_id1079_at_idx36232
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule413_id1079_at_idx36232
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule414_id1080_at_idx36298
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule414_id1080_at_idx36298
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VACGTfd:%[0-9]+]]:dpr = VACGTfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGTfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule415_id1081_at_idx36364
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule415_id1081_at_idx36364
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule416_id1082_at_idx36430
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule416_id1082_at_idx36430
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VACGThd:%[0-9]+]]:dpr = VACGThd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VACGThd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule417_id1083_at_idx36496
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule417_id1083_at_idx36496
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule418_id1116_at_idx36562
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule418_id1116_at_idx36562
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule419_id1117_at_idx36628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule419_id1117_at_idx36628
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule420_id1118_at_idx36694
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule420_id1118_at_idx36694
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule421_id1119_at_idx36760
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule421_id1119_at_idx36760
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule422_id1120_at_idx36826
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule422_id1120_at_idx36826
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv8i8_:%[0-9]+]]:dpr = VABDsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule423_id1121_at_idx36892
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule423_id1121_at_idx36892
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule424_id1122_at_idx36958
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule424_id1122_at_idx36958
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDuv4i16_:%[0-9]+]]:dpr = VABDuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule425_id1123_at_idx37024
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule425_id1123_at_idx37024
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDuv2i32_:%[0-9]+]]:dpr = VABDuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule426_id1124_at_idx37090
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule426_id1124_at_idx37090
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule427_id1125_at_idx37156
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule427_id1125_at_idx37156
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule428_id1126_at_idx37222
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule428_id1126_at_idx37222
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDuv8i8_:%[0-9]+]]:dpr = VABDuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule429_id1127_at_idx37288
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule429_id1127_at_idx37288
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule430_id1128_at_idx37354
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule430_id1128_at_idx37354
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv2i32_:%[0-9]+]]:dpr = VABDsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule431_id1129_at_idx37420
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule431_id1129_at_idx37420
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule432_id1130_at_idx37486
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule432_id1130_at_idx37486
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VABDsv4i16_:%[0-9]+]]:dpr = VABDsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VABDsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule433_id1131_at_idx37552
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule433_id1131_at_idx37552
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule434_id1196_at_idx37618
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule434_id1196_at_idx37618
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi8_:%[0-9]+]]:dpr = VPADDi8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule435_id1197_at_idx37684
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule435_id1197_at_idx37684
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule436_id1198_at_idx37750
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule436_id1198_at_idx37750
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule437_id1199_at_idx37816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule437_id1199_at_idx37816
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi32_:%[0-9]+]]:dpr = VPADDi32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule438_id1200_at_idx37882
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule438_id1200_at_idx37882
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDi16_:%[0-9]+]]:dpr = VPADDi16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDi16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule439_id1213_at_idx37948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule439_id1213_at_idx37948
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALsv8i8_:%[0-9]+]]:dpr = VPADALsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule440_id1214_at_idx38014
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule440_id1214_at_idx38014
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALsv4i16_:%[0-9]+]]:dpr = VPADALsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule441_id1215_at_idx38080
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule441_id1215_at_idx38080
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALsv2i32_:%[0-9]+]]:dpr = VPADALsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule442_id1216_at_idx38146
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule442_id1216_at_idx38146
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<8 x s16>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule443_id1217_at_idx38212
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule443_id1217_at_idx38212
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<4 x s32>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule444_id1218_at_idx38278
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule444_id1218_at_idx38278
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), [[DEF]](<2 x s64>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule445_id1219_at_idx38344
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule445_id1219_at_idx38344
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALuv8i8_:%[0-9]+]]:dpr = VPADALuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule446_id1220_at_idx38410
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule446_id1220_at_idx38410
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALuv4i16_:%[0-9]+]]:dpr = VPADALuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule447_id1221_at_idx38476
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule447_id1221_at_idx38476
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADALuv2i32_:%[0-9]+]]:dpr = VPADALuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADALuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule448_id1222_at_idx38542
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule448_id1222_at_idx38542
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<8 x s16>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule449_id1223_at_idx38608
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule449_id1223_at_idx38608
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<4 x s32>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule450_id1224_at_idx38674
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule450_id1224_at_idx38674
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), [[DEF]](<2 x s64>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule451_id1225_at_idx38740
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule451_id1225_at_idx38740
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs8_:%[0-9]+]]:dpr = VPMAXs8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule452_id1226_at_idx38806
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule452_id1226_at_idx38806
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule453_id1227_at_idx38872
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule453_id1227_at_idx38872
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule454_id1228_at_idx38938
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule454_id1228_at_idx38938
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXu8_:%[0-9]+]]:dpr = VPMAXu8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule455_id1229_at_idx39004
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule455_id1229_at_idx39004
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXu16_:%[0-9]+]]:dpr = VPMAXu16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule456_id1230_at_idx39070
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule456_id1230_at_idx39070
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXu32_:%[0-9]+]]:dpr = VPMAXu32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXu32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule457_id1231_at_idx39136
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule457_id1231_at_idx39136
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs32_:%[0-9]+]]:dpr = VPMAXs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule458_id1232_at_idx39202
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule458_id1232_at_idx39202
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMAXs16_:%[0-9]+]]:dpr = VPMAXs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMAXs16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule459_id1233_at_idx39268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule459_id1233_at_idx39268
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs8_:%[0-9]+]]:dpr = VPMINs8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule460_id1234_at_idx39334
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule460_id1234_at_idx39334
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule461_id1235_at_idx39400
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule461_id1235_at_idx39400
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule462_id1236_at_idx39466
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule462_id1236_at_idx39466
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINu8_:%[0-9]+]]:dpr = VPMINu8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule463_id1237_at_idx39532
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule463_id1237_at_idx39532
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINu16_:%[0-9]+]]:dpr = VPMINu16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule464_id1238_at_idx39598
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule464_id1238_at_idx39598
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINu32_:%[0-9]+]]:dpr = VPMINu32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINu32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule465_id1239_at_idx39664
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule465_id1239_at_idx39664
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs32_:%[0-9]+]]:dpr = VPMINs32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule466_id1240_at_idx39730
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule466_id1240_at_idx39730
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPMINs16_:%[0-9]+]]:dpr = VPMINs16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPMINs16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule467_id1247_at_idx39796
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule467_id1247_at_idx39796
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPSfd:%[0-9]+]]:dpr = VRECPSfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPSfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule468_id1248_at_idx39862
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule468_id1248_at_idx39862
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule469_id1249_at_idx39928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule469_id1249_at_idx39928
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPShd:%[0-9]+]]:dpr = VRECPShd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPShd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule470_id1250_at_idx39994
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule470_id1250_at_idx39994
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule471_id1257_at_idx40060
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule471_id1257_at_idx40060
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTSfd:%[0-9]+]]:dpr = VRSQRTSfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTSfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule472_id1258_at_idx40126
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule472_id1258_at_idx40126
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule473_id1259_at_idx40192
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule473_id1259_at_idx40192
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTShd:%[0-9]+]]:dpr = VRSQRTShd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTShd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule474_id1260_at_idx40258
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule474_id1260_at_idx40258
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule475_id1261_at_idx40324
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule475_id1261_at_idx40324
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLsv4i16_:%[0-9]+]]:dpr = VSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule476_id1262_at_idx40390
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule476_id1262_at_idx40390
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLsv2i32_:%[0-9]+]]:dpr = VSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule477_id1263_at_idx40456
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule477_id1263_at_idx40456
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule478_id1264_at_idx40522
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule478_id1264_at_idx40522
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule479_id1265_at_idx40588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule479_id1265_at_idx40588
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLsv8i8_:%[0-9]+]]:dpr = VSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule480_id1266_at_idx40654
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule480_id1266_at_idx40654
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule481_id1267_at_idx40720
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule481_id1267_at_idx40720
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLsv1i64_:%[0-9]+]]:dpr = VSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule482_id1268_at_idx40786
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule482_id1268_at_idx40786
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule483_id1269_at_idx40852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule483_id1269_at_idx40852
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLuv4i16_:%[0-9]+]]:dpr = VSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule484_id1270_at_idx40918
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule484_id1270_at_idx40918
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLuv2i32_:%[0-9]+]]:dpr = VSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule485_id1271_at_idx40984
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule485_id1271_at_idx40984
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule486_id1272_at_idx41050
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule486_id1272_at_idx41050
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule487_id1273_at_idx41116
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule487_id1273_at_idx41116
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLuv8i8_:%[0-9]+]]:dpr = VSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule488_id1274_at_idx41182
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule488_id1274_at_idx41182
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule489_id1275_at_idx41248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule489_id1275_at_idx41248
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSHLuv1i64_:%[0-9]+]]:dpr = VSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule490_id1276_at_idx41314
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule490_id1276_at_idx41314
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule491_id1310_at_idx41380
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule491_id1310_at_idx41380
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLsv4i16_:%[0-9]+]]:dpr = VRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule492_id1311_at_idx41446
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule492_id1311_at_idx41446
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLsv2i32_:%[0-9]+]]:dpr = VRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule493_id1312_at_idx41512
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule493_id1312_at_idx41512
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule494_id1313_at_idx41578
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule494_id1313_at_idx41578
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule495_id1314_at_idx41644
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule495_id1314_at_idx41644
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLsv8i8_:%[0-9]+]]:dpr = VRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule496_id1315_at_idx41710
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule496_id1315_at_idx41710
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule497_id1316_at_idx41776
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule497_id1316_at_idx41776
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLsv1i64_:%[0-9]+]]:dpr = VRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule498_id1317_at_idx41842
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule498_id1317_at_idx41842
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule499_id1318_at_idx41908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule499_id1318_at_idx41908
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLuv4i16_:%[0-9]+]]:dpr = VRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule500_id1319_at_idx41974
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule500_id1319_at_idx41974
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLuv2i32_:%[0-9]+]]:dpr = VRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule501_id1320_at_idx42040
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule501_id1320_at_idx42040
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule502_id1321_at_idx42106
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule502_id1321_at_idx42106
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule503_id1322_at_idx42172
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule503_id1322_at_idx42172
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLuv8i8_:%[0-9]+]]:dpr = VRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule504_id1323_at_idx42238
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule504_id1323_at_idx42238
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule505_id1324_at_idx42304
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule505_id1324_at_idx42304
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSHLuv1i64_:%[0-9]+]]:dpr = VRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule506_id1325_at_idx42370
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule506_id1325_at_idx42370
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule507_id1345_at_idx42436
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule507_id1345_at_idx42436
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLsv4i16_:%[0-9]+]]:dpr = VQSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule508_id1346_at_idx42502
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule508_id1346_at_idx42502
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLsv2i32_:%[0-9]+]]:dpr = VQSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule509_id1347_at_idx42568
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule509_id1347_at_idx42568
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule510_id1348_at_idx42634
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule510_id1348_at_idx42634
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule511_id1349_at_idx42700
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule511_id1349_at_idx42700
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLsv8i8_:%[0-9]+]]:dpr = VQSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule512_id1350_at_idx42766
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule512_id1350_at_idx42766
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule513_id1351_at_idx42832
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule513_id1351_at_idx42832
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLsv1i64_:%[0-9]+]]:dpr = VQSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule514_id1352_at_idx42898
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule514_id1352_at_idx42898
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule515_id1353_at_idx42964
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule515_id1353_at_idx42964
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLuv4i16_:%[0-9]+]]:dpr = VQSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule516_id1354_at_idx43030
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule516_id1354_at_idx43030
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLuv2i32_:%[0-9]+]]:dpr = VQSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule517_id1355_at_idx43096
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule517_id1355_at_idx43096
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule518_id1356_at_idx43162
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule518_id1356_at_idx43162
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule519_id1357_at_idx43228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule519_id1357_at_idx43228
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLuv8i8_:%[0-9]+]]:dpr = VQSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule520_id1358_at_idx43294
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule520_id1358_at_idx43294
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule521_id1359_at_idx43360
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule521_id1359_at_idx43360
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQSHLuv1i64_:%[0-9]+]]:dpr = VQSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule522_id1360_at_idx43426
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule522_id1360_at_idx43426
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule523_id1394_at_idx43492
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule523_id1394_at_idx43492
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLsv4i16_:%[0-9]+]]:dpr = VQRSHLsv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule524_id1395_at_idx43558
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule524_id1395_at_idx43558
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLsv2i32_:%[0-9]+]]:dpr = VQRSHLsv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule525_id1396_at_idx43624
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule525_id1396_at_idx43624
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule526_id1397_at_idx43690
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule526_id1397_at_idx43690
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule527_id1398_at_idx43756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule527_id1398_at_idx43756
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLsv8i8_:%[0-9]+]]:dpr = VQRSHLsv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule528_id1399_at_idx43822
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule528_id1399_at_idx43822
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule529_id1400_at_idx43888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule529_id1400_at_idx43888
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLsv1i64_:%[0-9]+]]:dpr = VQRSHLsv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLsv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule530_id1401_at_idx43954
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule530_id1401_at_idx43954
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule531_id1402_at_idx44020
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule531_id1402_at_idx44020
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLuv4i16_:%[0-9]+]]:dpr = VQRSHLuv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule532_id1403_at_idx44086
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule532_id1403_at_idx44086
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLuv2i32_:%[0-9]+]]:dpr = VQRSHLuv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule533_id1404_at_idx44152
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule533_id1404_at_idx44152
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<8 x s16>), [[DEF1]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule534_id1405_at_idx44218
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule534_id1405_at_idx44218
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule535_id1406_at_idx44284
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule535_id1406_at_idx44284
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLuv8i8_:%[0-9]+]]:dpr = VQRSHLuv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule536_id1407_at_idx44350
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule536_id1407_at_idx44350
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule537_id1408_at_idx44416
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule537_id1408_at_idx44416
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQRSHLuv1i64_:%[0-9]+]]:dpr = VQRSHLuv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQRSHLuv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule538_id1409_at_idx44482
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule538_id1409_at_idx44482
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), [[DEF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule539_id1674_at_idx44548
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule539_id1674_at_idx44548
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule540_id1675_at_idx44608
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule540_id1675_at_idx44608
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), [[DEF]](<16 x s8>), [[DEF1]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule541_id1678_at_idx44668
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule541_id1678_at_idx44668
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule542_id1679_at_idx44728
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule542_id1679_at_idx44728
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule564_id3_at_idx46183
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule564_id3_at_idx46183
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SEL:%[0-9]+]]:gpr = SEL [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule565_id123_at_idx46253
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule565_id123_at_idx46253
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SASX:%[0-9]+]]:gprnopc = SASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule566_id124_at_idx46323
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule566_id124_at_idx46323
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD16_:%[0-9]+]]:gprnopc = SADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule567_id125_at_idx46393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule567_id125_at_idx46393
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD8_:%[0-9]+]]:gprnopc = SADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule568_id126_at_idx46463
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule568_id126_at_idx46463
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSAX:%[0-9]+]]:gprnopc = SSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule569_id127_at_idx46533
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule569_id127_at_idx46533
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB16_:%[0-9]+]]:gprnopc = SSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule570_id128_at_idx46603
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule570_id128_at_idx46603
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB8_:%[0-9]+]]:gprnopc = SSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule571_id129_at_idx46673
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule571_id129_at_idx46673
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UASX:%[0-9]+]]:gprnopc = UASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule572_id130_at_idx46743
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule572_id130_at_idx46743
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD16_:%[0-9]+]]:gprnopc = UADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule573_id131_at_idx46813
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule573_id131_at_idx46813
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD8_:%[0-9]+]]:gprnopc = UADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule574_id132_at_idx46883
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule574_id132_at_idx46883
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAX:%[0-9]+]]:gprnopc = USAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule575_id133_at_idx46953
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule575_id133_at_idx46953
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB16_:%[0-9]+]]:gprnopc = USUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule576_id134_at_idx47023
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule576_id134_at_idx47023
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB8_:%[0-9]+]]:gprnopc = USUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule577_id435_at_idx47093
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule577_id435_at_idx47093
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SEL:%[0-9]+]]:gpr = SEL [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule578_id448_at_idx47163
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule578_id448_at_idx47163
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SASX:%[0-9]+]]:gprnopc = SASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule579_id449_at_idx47233
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule579_id449_at_idx47233
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD16_:%[0-9]+]]:gprnopc = SADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule580_id450_at_idx47303
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule580_id450_at_idx47303
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SADD8_:%[0-9]+]]:gprnopc = SADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule581_id451_at_idx47373
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule581_id451_at_idx47373
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSAX:%[0-9]+]]:gprnopc = SSAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule582_id452_at_idx47443
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule582_id452_at_idx47443
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB16_:%[0-9]+]]:gprnopc = SSUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule583_id453_at_idx47513
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule583_id453_at_idx47513
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[SSUB8_:%[0-9]+]]:gprnopc = SSUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule584_id454_at_idx47583
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule584_id454_at_idx47583
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UASX:%[0-9]+]]:gprnopc = UASX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UASX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule585_id455_at_idx47653
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule585_id455_at_idx47653
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD16_:%[0-9]+]]:gprnopc = UADD16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule586_id456_at_idx47723
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule586_id456_at_idx47723
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UADD8_:%[0-9]+]]:gprnopc = UADD8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADD8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule587_id457_at_idx47793
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule587_id457_at_idx47793
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USAX:%[0-9]+]]:gprnopc = USAX [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USAX]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule588_id458_at_idx47863
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule588_id458_at_idx47863
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB16_:%[0-9]+]]:gprnopc = USUB16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB16_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule589_id459_at_idx47933
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule589_id459_at_idx47933
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[USUB8_:%[0-9]+]]:gprnopc = USUB8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUB8_]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule590_id351_at_idx48003
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule590_id351_at_idx48003
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTB]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 255
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule591_id352_at_idx48061
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule591_id352_at_idx48061
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UXTH]]
+    %1:gprb(s32) = COPY $lr
+    %2:gprb(s32) = G_CONSTANT 65535
+    %0:gprb(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule596_id1201_at_idx48335
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule596_id1201_at_idx48335
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv8i8_:%[0-9]+]]:dpr = VPADDLsv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule597_id1202_at_idx48389
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule597_id1202_at_idx48389
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv4i16_:%[0-9]+]]:dpr = VPADDLsv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule598_id1203_at_idx48443
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule598_id1203_at_idx48443
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLsv2i32_:%[0-9]+]]:dpr = VPADDLsv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLsv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule599_id1204_at_idx48497
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule599_id1204_at_idx48497
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule600_id1205_at_idx48551
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule600_id1205_at_idx48551
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule601_id1206_at_idx48605
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule601_id1206_at_idx48605
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule602_id1207_at_idx48659
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule602_id1207_at_idx48659
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv8i8_:%[0-9]+]]:dpr = VPADDLuv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule603_id1208_at_idx48713
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule603_id1208_at_idx48713
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv4i16_:%[0-9]+]]:dpr = VPADDLuv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule604_id1209_at_idx48767
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule604_id1209_at_idx48767
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VPADDLuv2i32_:%[0-9]+]]:dpr = VPADDLuv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VPADDLuv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule605_id1210_at_idx48821
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule605_id1210_at_idx48821
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule606_id1211_at_idx48875
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule606_id1211_at_idx48875
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule607_id1212_at_idx48929
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule607_id1212_at_idx48929
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s64>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule608_id1241_at_idx48983
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule608_id1241_at_idx48983
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule609_id1242_at_idx49037
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule609_id1242_at_idx49037
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule610_id1243_at_idx49091
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule610_id1243_at_idx49091
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEd:%[0-9]+]]:dpr = VRECPEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule611_id1244_at_idx49145
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule611_id1244_at_idx49145
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule612_id1245_at_idx49199
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule612_id1245_at_idx49199
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRECPEhd:%[0-9]+]]:dpr = VRECPEhd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRECPEhd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule613_id1246_at_idx49253
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule613_id1246_at_idx49253
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule614_id1251_at_idx49307
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule614_id1251_at_idx49307
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule615_id1252_at_idx49361
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule615_id1252_at_idx49361
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule616_id1253_at_idx49415
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule616_id1253_at_idx49415
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTEd:%[0-9]+]]:dpr = VRSQRTEd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule617_id1254_at_idx49469
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule617_id1254_at_idx49469
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule618_id1255_at_idx49523
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule618_id1255_at_idx49523
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRSQRTEhd:%[0-9]+]]:dpr = VRSQRTEhd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRSQRTEhd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule619_id1256_at_idx49577
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule619_id1256_at_idx49577
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule620_id1477_at_idx49631
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule620_id1477_at_idx49631
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQABSv8i8_:%[0-9]+]]:dpr = VQABSv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule621_id1478_at_idx49685
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule621_id1478_at_idx49685
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQABSv4i16_:%[0-9]+]]:dpr = VQABSv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule622_id1479_at_idx49739
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule622_id1479_at_idx49739
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQABSv2i32_:%[0-9]+]]:dpr = VQABSv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQABSv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule623_id1480_at_idx49793
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule623_id1480_at_idx49793
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule624_id1481_at_idx49847
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule624_id1481_at_idx49847
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule625_id1482_at_idx49901
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule625_id1482_at_idx49901
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule626_id1493_at_idx49955
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule626_id1493_at_idx49955
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQNEGv8i8_:%[0-9]+]]:dpr = VQNEGv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule627_id1494_at_idx50009
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule627_id1494_at_idx50009
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQNEGv4i16_:%[0-9]+]]:dpr = VQNEGv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule628_id1495_at_idx50063
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule628_id1495_at_idx50063
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VQNEGv2i32_:%[0-9]+]]:dpr = VQNEGv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VQNEGv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule629_id1496_at_idx50117
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule629_id1496_at_idx50117
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule630_id1497_at_idx50171
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule630_id1497_at_idx50171
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule631_id1498_at_idx50225
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule631_id1498_at_idx50225
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule632_id1499_at_idx50279
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule632_id1499_at_idx50279
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCLSv8i8_:%[0-9]+]]:dpr = VCLSv8i8 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv8i8_]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule633_id1500_at_idx50333
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule633_id1500_at_idx50333
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCLSv4i16_:%[0-9]+]]:dpr = VCLSv4i16 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv4i16_]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule634_id1501_at_idx50387
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule634_id1501_at_idx50387
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCLSv2i32_:%[0-9]+]]:dpr = VCLSv2i32 [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCLSv2i32_]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule635_id1502_at_idx50441
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule635_id1502_at_idx50441
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule636_id1503_at_idx50495
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule636_id1503_at_idx50495
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule637_id1504_at_idx50549
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule637_id1504_at_idx50549
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule638_id1548_at_idx50603
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule638_id1548_at_idx50603
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule639_id1549_at_idx50657
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule639_id1549_at_idx50657
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule640_id1550_at_idx50711
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule640_id1550_at_idx50711
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule641_id1551_at_idx50765
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule641_id1551_at_idx50765
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule642_id1552_at_idx50819
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule642_id1552_at_idx50819
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule643_id1553_at_idx50873
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule643_id1553_at_idx50873
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule644_id1554_at_idx50927
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule644_id1554_at_idx50927
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule645_id1555_at_idx50981
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule645_id1555_at_idx50981
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule646_id1556_at_idx51035
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule646_id1556_at_idx51035
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule647_id1579_at_idx51089
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule647_id1579_at_idx51089
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANSDf:%[0-9]+]]:dpr = VCVTANSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule648_id1580_at_idx51137
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule648_id1580_at_idx51137
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule649_id1581_at_idx51185
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule649_id1581_at_idx51185
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANUDf:%[0-9]+]]:dpr = VCVTANUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule650_id1582_at_idx51233
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule650_id1582_at_idx51233
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule651_id1583_at_idx51281
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule651_id1583_at_idx51281
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANSDh:%[0-9]+]]:dpr = VCVTANSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule652_id1584_at_idx51329
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule652_id1584_at_idx51329
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule653_id1585_at_idx51377
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule653_id1585_at_idx51377
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTANUDh:%[0-9]+]]:dpr = VCVTANUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTANUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule654_id1586_at_idx51425
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule654_id1586_at_idx51425
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule655_id1587_at_idx51473
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule655_id1587_at_idx51473
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNSDf:%[0-9]+]]:dpr = VCVTNNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule656_id1588_at_idx51521
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule656_id1588_at_idx51521
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule657_id1589_at_idx51569
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule657_id1589_at_idx51569
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNUDf:%[0-9]+]]:dpr = VCVTNNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule658_id1590_at_idx51617
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule658_id1590_at_idx51617
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule659_id1591_at_idx51665
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule659_id1591_at_idx51665
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNSDh:%[0-9]+]]:dpr = VCVTNNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule660_id1592_at_idx51713
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule660_id1592_at_idx51713
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule661_id1593_at_idx51761
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule661_id1593_at_idx51761
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTNNUDh:%[0-9]+]]:dpr = VCVTNNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTNNUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule662_id1594_at_idx51809
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule662_id1594_at_idx51809
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule663_id1595_at_idx51857
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule663_id1595_at_idx51857
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTPNSDf:%[0-9]+]]:dpr = VCVTPNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule664_id1596_at_idx51905
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule664_id1596_at_idx51905
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule665_id1597_at_idx51953
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule665_id1597_at_idx51953
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTPNUDf:%[0-9]+]]:dpr = VCVTPNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule666_id1598_at_idx52001
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule666_id1598_at_idx52001
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule667_id1599_at_idx52049
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule667_id1599_at_idx52049
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTPNSDh:%[0-9]+]]:dpr = VCVTPNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule668_id1600_at_idx52097
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule668_id1600_at_idx52097
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule669_id1601_at_idx52145
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule669_id1601_at_idx52145
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTPNUDh:%[0-9]+]]:dpr = VCVTPNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTPNUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule670_id1602_at_idx52193
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule670_id1602_at_idx52193
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule671_id1603_at_idx52241
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule671_id1603_at_idx52241
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTMNSDf:%[0-9]+]]:dpr = VCVTMNSDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule672_id1604_at_idx52289
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule672_id1604_at_idx52289
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule673_id1605_at_idx52337
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule673_id1605_at_idx52337
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTMNUDf:%[0-9]+]]:dpr = VCVTMNUDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule674_id1606_at_idx52385
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule674_id1606_at_idx52385
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule675_id1607_at_idx52433
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule675_id1607_at_idx52433
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTMNSDh:%[0-9]+]]:dpr = VCVTMNSDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNSDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule676_id1608_at_idx52481
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule676_id1608_at_idx52481
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule677_id1609_at_idx52529
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule677_id1609_at_idx52529
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTMNUDh:%[0-9]+]]:dpr = VCVTMNUDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTMNUDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule678_id1610_at_idx52577
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule678_id1610_at_idx52577
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule679_id1627_at_idx52625
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule679_id1627_at_idx52625
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule680_id1628_at_idx52679
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule680_id1628_at_idx52679
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), [[COPY]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule681_id1650_at_idx52733
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule681_id1650_at_idx52733
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTNNDf:%[0-9]+]]:dpr = VRINTNNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule682_id1651_at_idx52781
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule682_id1651_at_idx52781
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule683_id1652_at_idx52829
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule683_id1652_at_idx52829
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTNNDh:%[0-9]+]]:dpr = VRINTNNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTNNDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule684_id1653_at_idx52877
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule684_id1653_at_idx52877
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule685_id1654_at_idx52925
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule685_id1654_at_idx52925
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTXNDf:%[0-9]+]]:dpr = VRINTXNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule686_id1655_at_idx52973
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule686_id1655_at_idx52973
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule687_id1656_at_idx53021
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule687_id1656_at_idx53021
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTXNDh:%[0-9]+]]:dpr = VRINTXNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTXNDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule688_id1657_at_idx53069
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule688_id1657_at_idx53069
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule689_id1658_at_idx53117
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule689_id1658_at_idx53117
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTANDf:%[0-9]+]]:dpr = VRINTANDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule690_id1659_at_idx53165
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule690_id1659_at_idx53165
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule691_id1660_at_idx53213
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule691_id1660_at_idx53213
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTANDh:%[0-9]+]]:dpr = VRINTANDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTANDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule692_id1661_at_idx53261
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule692_id1661_at_idx53261
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule693_id1662_at_idx53309
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule693_id1662_at_idx53309
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTZNDf:%[0-9]+]]:dpr = VRINTZNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule694_id1663_at_idx53357
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule694_id1663_at_idx53357
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule695_id1664_at_idx53405
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule695_id1664_at_idx53405
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTZNDh:%[0-9]+]]:dpr = VRINTZNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTZNDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule696_id1665_at_idx53453
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule696_id1665_at_idx53453
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule697_id1666_at_idx53501
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule697_id1666_at_idx53501
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTMNDf:%[0-9]+]]:dpr = VRINTMNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule698_id1667_at_idx53549
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule698_id1667_at_idx53549
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule699_id1668_at_idx53597
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule699_id1668_at_idx53597
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTMNDh:%[0-9]+]]:dpr = VRINTMNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTMNDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule700_id1669_at_idx53645
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule700_id1669_at_idx53645
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule701_id1670_at_idx53693
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule701_id1670_at_idx53693
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTPNDf:%[0-9]+]]:dpr = VRINTPNDf [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDf]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule702_id1671_at_idx53741
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule702_id1671_at_idx53741
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule703_id1672_at_idx53789
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule703_id1672_at_idx53789
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VRINTPNDh:%[0-9]+]]:dpr = VRINTPNDh [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[VRINTPNDh]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule704_id1673_at_idx53837
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule704_id1673_at_idx53837
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule705_id1676_at_idx53885
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule705_id1676_at_idx53885
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule706_id1677_at_idx53933
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule706_id1677_at_idx53933
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[INT]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule712_id715_at_idx54278
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule712_id715_at_idx54278
+    ; SELECTED: [[VMRS:%[0-9]+]]:gprnopc = VMRS 14, $noreg, implicit $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMRS]]
+    %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule713_id716_at_idx54324
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule713_id716_at_idx54324
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: VMSR [[COPY]], 14, $noreg, implicit-def $fpscr
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gprb(s32) = COPY $lr
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule714_id254_at_idx54370
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule714_id254_at_idx54370
+    ; SELECTED: CLREX
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule715_id587_at_idx54398
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule715_id587_at_idx54398
+    ; SELECTED: CLREX
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule716_id74_at_idx54432
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule716_id74_at_idx54432
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule717_id411_at_idx54511
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule717_id411_at_idx54511
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule718_id412_at_idx54590
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule718_id412_at_idx54590
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule724_id98_at_idx55061
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule724_id98_at_idx55061
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SUB %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule725_id431_at_idx55140
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule725_id431_at_idx55140
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 1, 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSBri]]
+    %2:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_CONSTANT 1
+    %1:gprb(s32) = G_SUB %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule731_id2086_at_idx55611
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule731_id2086_at_idx55611
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSD]]
+    %4:fprb(s64) = COPY $d18
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %4
+    %1:fprb(s64) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule732_id2087_at_idx55705
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+  - { reg: '$s4', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule732_id2087_at_idx55705
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSS]]
+    %4:fprb(s32) = COPY $s4
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %4
+    %1:fprb(s32) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule733_id2174_at_idx55799
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule733_id2174_at_idx55799
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMSfd:%[0-9]+]]:dpr = VFMSfd [[COPY1]], [[COPY]], [[COPY2]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSfd]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FNEG %4
+    %1:fprb(<2 x s32>) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule734_id2175_at_idx55893
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule734_id2175_at_idx55893
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:_(<4 x s32>) = G_FNEG [[DEF2]]
+    ; SELECTED: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FNEG]], [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMA]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FNEG %4
+    %1:_(<4 x s32>) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule735_id2088_at_idx55987
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule735_id2088_at_idx55987
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSD]]
+    %4:fprb(s64) = COPY $d18
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %4
+    %1:fprb(s64) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule736_id2089_at_idx56081
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+  - { reg: '$s4', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule736_id2089_at_idx56081
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY1]], [[COPY2]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMSS]]
+    %4:fprb(s32) = COPY $s4
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %4
+    %1:fprb(s32) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule737_id2098_at_idx56175
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule737_id2098_at_idx56175
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSD]]
+    %4:fprb(s64) = COPY $d18
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %4
+    %1:fprb(s64) = G_FMA %2, %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule738_id2099_at_idx56269
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+  - { reg: '$s4', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule738_id2099_at_idx56269
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMSS]]
+    %4:fprb(s32) = COPY $s4
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %4
+    %1:fprb(s32) = G_FMA %2, %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule742_id2569_at_idx56651
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule742_id2569_at_idx56651
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv8i8_:%[0-9]+]]:dpr = VMLAv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_MUL %3, %4
+    %1:fprb(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule743_id2570_at_idx56745
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule743_id2570_at_idx56745
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv4i16_:%[0-9]+]]:dpr = VMLAv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_MUL %3, %4
+    %1:fprb(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule744_id2571_at_idx56839
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule744_id2571_at_idx56839
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv2i32_:%[0-9]+]]:dpr = VMLAv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_MUL %3, %4
+    %1:fprb(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule745_id2572_at_idx56933
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule745_id2572_at_idx56933
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[MUL]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_MUL %3, %4
+    %1:_(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule746_id2573_at_idx57027
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule746_id2573_at_idx57027
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[MUL]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_MUL %3, %4
+    %1:_(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule747_id2574_at_idx57121
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule747_id2574_at_idx57121
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[MUL]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_MUL %3, %4
+    %1:_(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule748_id2545_at_idx57215
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule748_id2545_at_idx57215
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule749_id2546_at_idx57297
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule749_id2546_at_idx57297
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule750_id2547_at_idx57379
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule750_id2547_at_idx57379
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[SEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule751_id2548_at_idx57461
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule751_id2548_at_idx57461
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule752_id2549_at_idx57543
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule752_id2549_at_idx57543
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule753_id2550_at_idx57625
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule753_id2550_at_idx57625
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ZEXT]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule754_id865_at_idx57707
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule754_id865_at_idx57707
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv8i8_:%[0-9]+]]:dpr = VMLAv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_MUL %3, %4
+    %1:fprb(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule755_id866_at_idx57801
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule755_id866_at_idx57801
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv4i16_:%[0-9]+]]:dpr = VMLAv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_MUL %3, %4
+    %1:fprb(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule756_id867_at_idx57895
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule756_id867_at_idx57895
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLAv2i32_:%[0-9]+]]:dpr = VMLAv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLAv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_MUL %3, %4
+    %1:fprb(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule757_id868_at_idx57989
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule757_id868_at_idx57989
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_MUL %3, %4
+    %1:_(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule758_id869_at_idx58083
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule758_id869_at_idx58083
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_MUL %3, %4
+    %1:_(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule759_id870_at_idx58177
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule759_id870_at_idx58177
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_MUL %3, %4
+    %1:_(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule763_id764_at_idx58559
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule763_id764_at_idx58559
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule764_id765_at_idx58641
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule764_id765_at_idx58641
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule765_id766_at_idx58723
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule765_id766_at_idx58723
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule766_id767_at_idx58805
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule766_id767_at_idx58805
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule767_id768_at_idx58887
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule767_id768_at_idx58887
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule768_id769_at_idx58969
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule768_id769_at_idx58969
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule769_id2623_at_idx59051
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule769_id2623_at_idx59051
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMAhd:%[0-9]+]]:dpr = VFMAhd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAhd]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FMUL %3, %4
+    %1:fprb(<4 x s16>) = G_FADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule770_id2624_at_idx59145
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule770_id2624_at_idx59145
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[FMUL]], [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FMUL %3, %4
+    %1:_(<8 x s16>) = G_FADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule771_id923_at_idx59239
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule771_id923_at_idx59239
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMAhd:%[0-9]+]]:dpr = VFMAhd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAhd]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FMUL %3, %4
+    %1:fprb(<4 x s16>) = G_FADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule772_id924_at_idx59333
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule772_id924_at_idx59333
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[DEF]], [[FMUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FMUL %3, %4
+    %1:_(<8 x s16>) = G_FADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule773_id2029_at_idx59427
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule773_id2029_at_idx59427
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULD]]
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %3
+    %1:fprb(s64) = G_FMUL %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule774_id2030_at_idx59509
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule774_id2030_at_idx59509
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULS]]
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %3
+    %1:fprb(s32) = G_FMUL %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule775_id2736_at_idx59591
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule775_id2736_at_idx59591
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULD]]
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %3
+    %1:fprb(s64) = G_FMUL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule776_id2737_at_idx59673
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule776_id2737_at_idx59673
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULS]]
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %3
+    %1:fprb(s32) = G_FMUL %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule777_id901_at_idx59755
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule777_id901_at_idx59755
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLShd:%[0-9]+]]:dpr = VMLShd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLShd]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FMUL %3, %4
+    %1:fprb(<4 x s16>) = G_FSUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule778_id902_at_idx59849
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule778_id902_at_idx59849
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[FMUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FMUL %3, %4
+    %1:_(<8 x s16>) = G_FSUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule779_id927_at_idx59943
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule779_id927_at_idx59943
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLShd:%[0-9]+]]:dpr = VMLShd [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLShd]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FMUL %3, %4
+    %1:fprb(<4 x s16>) = G_FSUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule780_id928_at_idx60037
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule780_id928_at_idx60037
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[FMUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FMUL %3, %4
+    %1:_(<8 x s16>) = G_FSUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule783_id893_at_idx60319
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule783_id893_at_idx60319
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLSv8i8_:%[0-9]+]]:dpr = VMLSv8i8 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv8i8_]]
+    %4:fprb(<8 x s8>) = COPY $d18
+    %3:fprb(<8 x s8>) = COPY $d17
+    %2:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_MUL %3, %4
+    %1:fprb(<8 x s8>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule784_id894_at_idx60413
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule784_id894_at_idx60413
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLSv4i16_:%[0-9]+]]:dpr = VMLSv4i16 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv4i16_]]
+    %4:fprb(<4 x s16>) = COPY $d18
+    %3:fprb(<4 x s16>) = COPY $d17
+    %2:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_MUL %3, %4
+    %1:fprb(<4 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule785_id895_at_idx60507
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule785_id895_at_idx60507
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMLSv2i32_:%[0-9]+]]:dpr = VMLSv2i32 [[COPY2]], [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMLSv2i32_]]
+    %4:fprb(<2 x s32>) = COPY $d18
+    %3:fprb(<2 x s32>) = COPY $d17
+    %2:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_MUL %3, %4
+    %1:fprb(<2 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule786_id896_at_idx60601
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule786_id896_at_idx60601
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<16 x s8>)
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %3:_(<16 x s8>) = IMPLICIT_DEF
+    %4:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_MUL %3, %4
+    %1:_(<16 x s8>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule787_id897_at_idx60695
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule787_id897_at_idx60695
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %3:_(<8 x s16>) = IMPLICIT_DEF
+    %4:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_MUL %3, %4
+    %1:_(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule788_id898_at_idx60789
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule788_id898_at_idx60789
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF1]], [[DEF2]]
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[MUL]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %4:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_MUL %3, %4
+    %1:_(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule789_id947_at_idx60883
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule789_id947_at_idx60883
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule790_id948_at_idx60965
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule790_id948_at_idx60965
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule791_id949_at_idx61047
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule791_id949_at_idx61047
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[SEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule792_id950_at_idx61129
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule792_id950_at_idx61129
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %3:fprb(<8 x s8>) = COPY $d16
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:_(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule793_id951_at_idx61211
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule793_id951_at_idx61211
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %3:fprb(<4 x s16>) = COPY $d16
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:_(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule794_id952_at_idx61293
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule794_id952_at_idx61293
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[ZEXT]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    %3:fprb(<2 x s32>) = COPY $d16
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:_(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule795_id2092_at_idx61375
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+  - { reg: '$d18', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule795_id2092_at_idx61375
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAD]]
+    %4:fprb(s64) = COPY $d18
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FMA %2, %3, %4
+    %1:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule796_id2093_at_idx61469
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+  - { id: 4, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+  - { reg: '$s4', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule796_id2093_at_idx61469
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFNMAS]]
+    %4:fprb(s32) = COPY $s4
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FMA %2, %3, %4
+    %1:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule797_id630_at_idx61563
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%2' }
+  - { reg: '$d17', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule797_id630_at_idx61563
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULD]]
+    %3:fprb(s64) = COPY $d17
+    %2:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FMUL %2, %3
+    %1:fprb(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule798_id631_at_idx61645
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule798_id631_at_idx61645
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNMULS]]
+    %3:fprb(s32) = COPY $s2
+    %2:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FMUL %2, %3
+    %1:fprb(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule804_id2081_at_idx61991
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule804_id2081_at_idx61991
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMAD:%[0-9]+]]:dpr = VFMAD [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAD]]
+    %3:fprb(s64) = COPY $d18
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule805_id2082_at_idx62065
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s2', virtual-reg: '%2' }
+  - { reg: '$s4', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2, $s4
+
+    ; SELECTED-LABEL: name: test_rule805_id2082_at_idx62065
+    ; SELECTED: liveins: $s0, $s2, $s4
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s4
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY2:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VFMAS:%[0-9]+]]:spr = VFMAS [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAS]]
+    %3:fprb(s32) = COPY $s4
+    %2:fprb(s32) = COPY $s2
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule806_id2172_at_idx62139
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+  - { id: 3, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+  - { reg: '$d18', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17, $d18
+
+    ; SELECTED-LABEL: name: test_rule806_id2172_at_idx62139
+    ; SELECTED: liveins: $d16, $d17, $d18
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d18
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY2:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VFMAfd:%[0-9]+]]:dpr = VFMAfd [[COPY]], [[COPY2]], [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VFMAfd]]
+    %3:fprb(<2 x s32>) = COPY $d18
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule807_id2173_at_idx62213
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule807_id2173_at_idx62213
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF2:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[DEF]], [[DEF1]], [[DEF2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMA]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %3:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule808_id75_at_idx62287
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule808_id75_at_idx62287
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule809_id413_at_idx62352
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule809_id413_at_idx62352
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule810_id746_at_idx62417
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule810_id746_at_idx62417
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDv8i8_:%[0-9]+]]:dpr = VADDv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule811_id747_at_idx62479
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule811_id747_at_idx62479
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDv4i16_:%[0-9]+]]:dpr = VADDv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule812_id748_at_idx62541
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule812_id748_at_idx62541
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDv2i32_:%[0-9]+]]:dpr = VADDv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule813_id749_at_idx62603
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule813_id749_at_idx62603
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule814_id750_at_idx62665
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule814_id750_at_idx62665
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule815_id751_at_idx62727
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule815_id751_at_idx62727
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule816_id752_at_idx62789
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule816_id752_at_idx62789
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDv1i64_:%[0-9]+]]:dpr = VADDv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule817_id753_at_idx62851
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule817_id753_at_idx62851
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADD]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule818_id2503_at_idx62913
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule818_id2503_at_idx62913
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDrr]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule821_id1090_at_idx63108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule821_id1090_at_idx63108
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VANDd:%[0-9]+]]:dpr = VANDd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VANDd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule822_id1091_at_idx63170
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule822_id1091_at_idx63170
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AND]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule824_id618_at_idx63297
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule824_id618_at_idx63297
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDD:%[0-9]+]]:dpr = VADDD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDD]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule825_id619_at_idx63359
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s2', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule825_id619_at_idx63359
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VADDS:%[0-9]+]]:spr = VADDS [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDS]]
+    %2:fprb(s32) = COPY $s2
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule827_id754_at_idx63483
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule827_id754_at_idx63483
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDfd:%[0-9]+]]:dpr = VADDfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule828_id755_at_idx63545
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule828_id755_at_idx63545
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule829_id756_at_idx63607
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule829_id756_at_idx63607
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VADDhd:%[0-9]+]]:dpr = VADDhd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VADDhd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule830_id757_at_idx63669
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule830_id757_at_idx63669
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FADD:%[0-9]+]]:_(<8 x s16>) = G_FADD [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADD]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule831_id624_at_idx63731
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule831_id624_at_idx63731
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VDIVD:%[0-9]+]]:dpr = VDIVD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVD]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule832_id625_at_idx63793
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s2', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule832_id625_at_idx63793
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VDIVS:%[0-9]+]]:spr = VDIVS [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VDIVS]]
+    %2:fprb(s32) = COPY $s2
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule834_id627_at_idx63917
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule834_id627_at_idx63917
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULD:%[0-9]+]]:dpr = VMULD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULD]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule835_id628_at_idx63979
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s2', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule835_id628_at_idx63979
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VMULS:%[0-9]+]]:spr = VMULS [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULS]]
+    %2:fprb(s32) = COPY $s2
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule837_id821_at_idx64103
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule837_id821_at_idx64103
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULfd:%[0-9]+]]:dpr = VMULfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule838_id822_at_idx64165
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule838_id822_at_idx64165
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule839_id823_at_idx64227
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule839_id823_at_idx64227
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULhd:%[0-9]+]]:dpr = VMULhd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULhd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule840_id824_at_idx64289
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule840_id824_at_idx64289
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FMUL:%[0-9]+]]:_(<8 x s16>) = G_FMUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMUL]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule841_id621_at_idx64351
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule841_id621_at_idx64351
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBD:%[0-9]+]]:dpr = VSUBD [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBD]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule842_id622_at_idx64413
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s2', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s2
+
+    ; SELECTED-LABEL: name: test_rule842_id622_at_idx64413
+    ; SELECTED: liveins: $s0, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VSUBS:%[0-9]+]]:spr = VSUBS [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBS]]
+    %2:fprb(s32) = COPY $s2
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule844_id937_at_idx64537
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule844_id937_at_idx64537
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBfd:%[0-9]+]]:dpr = VSUBfd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBfd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule845_id938_at_idx64599
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule845_id938_at_idx64599
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule846_id939_at_idx64661
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule846_id939_at_idx64661
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBhd:%[0-9]+]]:dpr = VSUBhd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBhd]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule847_id940_at_idx64723
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule847_id940_at_idx64723
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FSUB:%[0-9]+]]:_(<8 x s16>) = G_FSUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUB]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule849_id171_at_idx64850
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule849_id171_at_idx64850
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule850_id172_at_idx64915
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule850_id172_at_idx64915
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule851_id506_at_idx64980
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule851_id506_at_idx64980
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gprnopc = COPY $lr
+    ; SELECTED: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY1]], [[COPY]], 14, $noreg, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule852_id813_at_idx65042
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule852_id813_at_idx65042
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULv8i8_:%[0-9]+]]:dpr = VMULv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule853_id814_at_idx65104
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule853_id814_at_idx65104
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULv4i16_:%[0-9]+]]:dpr = VMULv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule854_id815_at_idx65166
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule854_id815_at_idx65166
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VMULv2i32_:%[0-9]+]]:dpr = VMULv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMULv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule855_id816_at_idx65228
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule855_id816_at_idx65228
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule856_id817_at_idx65290
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule856_id817_at_idx65290
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule857_id818_at_idx65352
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule857_id818_at_idx65352
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MUL]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule860_id1094_at_idx65544
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule860_id1094_at_idx65544
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VORRd:%[0-9]+]]:dpr = VORRd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VORRd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule861_id1095_at_idx65606
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule861_id1095_at_idx65606
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[OR]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule862_id197_at_idx65668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule862_id197_at_idx65668
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIV]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_SDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule863_id536_at_idx65730
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule863_id536_at_idx65730
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIV]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_SDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule867_id929_at_idx65987
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule867_id929_at_idx65987
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBv8i8_:%[0-9]+]]:dpr = VSUBv8i8 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv8i8_]]
+    %2:fprb(<8 x s8>) = COPY $d17
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule868_id930_at_idx66049
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule868_id930_at_idx66049
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBv4i16_:%[0-9]+]]:dpr = VSUBv4i16 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv4i16_]]
+    %2:fprb(<4 x s16>) = COPY $d17
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule869_id931_at_idx66111
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule869_id931_at_idx66111
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBv2i32_:%[0-9]+]]:dpr = VSUBv2i32 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv2i32_]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule870_id932_at_idx66173
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule870_id932_at_idx66173
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<16 x s8>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %2:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule871_id933_at_idx66235
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule871_id933_at_idx66235
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %2:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule872_id934_at_idx66297
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule872_id934_at_idx66297
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule873_id935_at_idx66359
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule873_id935_at_idx66359
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VSUBv1i64_:%[0-9]+]]:dpr = VSUBv1i64 [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSUBv1i64_]]
+    %2:fprb(s64) = COPY $d17
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule874_id936_at_idx66421
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule874_id936_at_idx66421
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUB]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %2:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule875_id198_at_idx66483
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule875_id198_at_idx66483
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIV]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_UDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule876_id537_at_idx66545
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+  - { reg: '$r0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $lr, $r0
+
+    ; SELECTED-LABEL: name: test_rule876_id537_at_idx66545
+    ; SELECTED: liveins: $lr, $r0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $r0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIV]]
+    %2:gprb(s32) = COPY $r0
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_UDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule879_id1092_at_idx66737
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+  - { id: 2, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+  - { reg: '$d17', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d16, $d17
+
+    ; SELECTED-LABEL: name: test_rule879_id1092_at_idx66737
+    ; SELECTED: liveins: $d16, $d17
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d17
+    ; SELECTED: [[COPY1:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VEORd:%[0-9]+]]:dpr = VEORd [[COPY1]], [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VEORd]]
+    %2:fprb(<2 x s32>) = COPY $d17
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule880_id1093_at_idx66799
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule880_id1093_at_idx66799
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[DEF]], [[DEF1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XOR]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %2:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule881_id2253_at_idx66861
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule881_id2253_at_idx66861
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<8 x s16>)
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule882_id2254_at_idx66909
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule882_id2254_at_idx66909
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<4 x s32>)
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:_(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule883_id2255_at_idx66957
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule883_id2255_at_idx66957
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANYEXT]](<2 x s64>)
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule884_id678_at_idx67005
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule884_id678_at_idx67005
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVRS]]
+    %1:fprb(s32) = COPY $s0
+    %0:gprb(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule885_id679_at_idx67055
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule885_id679_at_idx67055
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VMOVSR]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule886_id2295_at_idx67105
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule886_id2295_at_idx67105
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule887_id2296_at_idx67151
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule887_id2296_at_idx67151
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule888_id2297_at_idx67197
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule888_id2297_at_idx67197
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule889_id2298_at_idx67243
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule889_id2298_at_idx67243
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule891_id2300_at_idx67333
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule891_id2300_at_idx67333
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule892_id2301_at_idx67379
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule892_id2301_at_idx67379
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule893_id2302_at_idx67425
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule893_id2302_at_idx67425
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule895_id2304_at_idx67517
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule895_id2304_at_idx67517
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule896_id2305_at_idx67561
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule896_id2305_at_idx67561
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule897_id2306_at_idx67607
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule897_id2306_at_idx67607
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule898_id2307_at_idx67653
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule898_id2307_at_idx67653
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule901_id2310_at_idx67791
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule901_id2310_at_idx67791
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule902_id2311_at_idx67837
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule902_id2311_at_idx67837
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule903_id2312_at_idx67883
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule903_id2312_at_idx67883
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule916_id2325_at_idx68477
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule916_id2325_at_idx68477
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule917_id2326_at_idx68523
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule917_id2326_at_idx68523
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule918_id2327_at_idx68569
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule918_id2327_at_idx68569
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule919_id2328_at_idx68615
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule919_id2328_at_idx68615
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule921_id2330_at_idx68705
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule921_id2330_at_idx68705
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule922_id2331_at_idx68751
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule922_id2331_at_idx68751
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule923_id2332_at_idx68797
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule923_id2332_at_idx68797
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule925_id2334_at_idx68889
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule925_id2334_at_idx68889
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule926_id2335_at_idx68933
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule926_id2335_at_idx68933
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule927_id2336_at_idx68979
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule927_id2336_at_idx68979
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule928_id2337_at_idx69025
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule928_id2337_at_idx69025
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule931_id2340_at_idx69163
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule931_id2340_at_idx69163
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule932_id2341_at_idx69209
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule932_id2341_at_idx69209
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule933_id2342_at_idx69255
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule933_id2342_at_idx69255
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule946_id2355_at_idx69849
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule946_id2355_at_idx69849
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule947_id2356_at_idx69899
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule947_id2356_at_idx69899
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule948_id2357_at_idx69949
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule948_id2357_at_idx69949
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule950_id2359_at_idx70049
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule950_id2359_at_idx70049
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule951_id2360_at_idx70099
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule951_id2360_at_idx70099
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule952_id2361_at_idx70149
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule952_id2361_at_idx70149
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule954_id2363_at_idx70249
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule954_id2363_at_idx70249
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule955_id2364_at_idx70299
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule955_id2364_at_idx70299
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule956_id2365_at_idx70349
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule956_id2365_at_idx70349
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule959_id2368_at_idx70499
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule959_id2368_at_idx70499
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule960_id2369_at_idx70549
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule960_id2369_at_idx70549
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule961_id2370_at_idx70599
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule961_id2370_at_idx70599
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule972_id2381_at_idx71149
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule972_id2381_at_idx71149
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule973_id2382_at_idx71199
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule973_id2382_at_idx71199
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule974_id2383_at_idx71249
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule974_id2383_at_idx71249
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<2 x s64>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule976_id2385_at_idx71349
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule976_id2385_at_idx71349
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule977_id2386_at_idx71399
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule977_id2386_at_idx71399
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule978_id2387_at_idx71449
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule978_id2387_at_idx71449
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<4 x s32>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule980_id2389_at_idx71549
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule980_id2389_at_idx71549
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule981_id2390_at_idx71599
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule981_id2390_at_idx71599
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule982_id2391_at_idx71649
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule982_id2391_at_idx71649
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[DEF]](<16 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<8 x s16>)
+    %1:_(<16 x s8>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule985_id2394_at_idx71799
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule985_id2394_at_idx71799
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule986_id2395_at_idx71849
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule986_id2395_at_idx71849
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule987_id2396_at_idx71899
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule987_id2396_at_idx71899
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[BITCAST]](<16 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule998_id201_at_idx72449
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule998_id201_at_idx72449
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REV:%[0-9]+]]:gpr = REV [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule999_id334_at_idx72499
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule999_id334_at_idx72499
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REV:%[0-9]+]]:gpr = REV [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1000_id540_at_idx72549
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1000_id540_at_idx72549
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[REV:%[0-9]+]]:gpr = REV [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV]]
+    %1:gprb(s32) = COPY $lr
+    %0:gprb(s32) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1002_id661_at_idx72634
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1002_id661_at_idx72634
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNEGD:%[0-9]+]]:dpr = VNEGD [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGD]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s64) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1003_id662_at_idx72684
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1003_id662_at_idx72684
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VNEGS:%[0-9]+]]:spr = VNEGS [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGS]]
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s32) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1005_id1489_at_idx72784
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1005_id1489_at_idx72784
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNEGfd:%[0-9]+]]:dpr = VNEGfd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGfd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1006_id1490_at_idx72834
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1006_id1490_at_idx72834
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:_(<4 x s32>) = G_FNEG [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1007_id1491_at_idx72884
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1007_id1491_at_idx72884
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VNEGhd:%[0-9]+]]:dpr = VNEGhd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VNEGhd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1008_id1492_at_idx72934
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1008_id1492_at_idx72934
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FNEG:%[0-9]+]]:_(<8 x s16>) = G_FNEG [[DEF]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEG]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1009_id659_at_idx72984
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1009_id659_at_idx72984
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VCVTDS:%[0-9]+]]:dpr = VCVTDS [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTDS]]
+    %1:fprb(s32) = COPY $s0
+    %0:fprb(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1012_id1563_at_idx73166
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1012_id1563_at_idx73166
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2sd:%[0-9]+]]:dpr = VCVTf2sd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2sd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1013_id1567_at_idx73216
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1013_id1567_at_idx73216
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FPTOSI:%[0-9]+]]:_(<4 x s32>) = G_FPTOSI [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOSI]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1014_id1571_at_idx73266
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1014_id1571_at_idx73266
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2sd:%[0-9]+]]:dpr = VCVTh2sd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2sd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FPTOSI %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1015_id1575_at_idx73316
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1015_id1575_at_idx73316
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FPTOSI:%[0-9]+]]:_(<8 x s16>) = G_FPTOSI [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOSI]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1016_id2053_at_idx73366
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1016_id2053_at_idx73366
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTOSIZD:%[0-9]+]]:spr = VTOSIZD [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZD]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s64) = COPY $d16
+    %0:gprb(s32) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1017_id2055_at_idx73434
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1017_id2055_at_idx73434
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s32) = COPY $s0
+    %0:gprb(s32) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1019_id1564_at_idx73570
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1019_id1564_at_idx73570
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTf2ud:%[0-9]+]]:dpr = VCVTf2ud [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTf2ud]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1020_id1568_at_idx73620
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1020_id1568_at_idx73620
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[FPTOUI:%[0-9]+]]:_(<4 x s32>) = G_FPTOUI [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOUI]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1021_id1572_at_idx73670
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1021_id1572_at_idx73670
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTh2ud:%[0-9]+]]:dpr = VCVTh2ud [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTh2ud]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_FPTOUI %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1022_id1576_at_idx73720
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1022_id1576_at_idx73720
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[FPTOUI:%[0-9]+]]:_(<8 x s16>) = G_FPTOUI [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[FPTOUI]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1023_id2058_at_idx73770
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1023_id2058_at_idx73770
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VTOUIZD:%[0-9]+]]:spr = VTOUIZD [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZD]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s64) = COPY $d16
+    %0:gprb(s32) = G_FPTOUI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1024_id2060_at_idx73838
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1024_id2060_at_idx73838
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:spr = COPY $s0
+    ; SELECTED: [[VTOUIZS:%[0-9]+]]:spr = VTOUIZS [[COPY]], 14, $noreg
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZS]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fprb(s32) = COPY $s0
+    %0:gprb(s32) = G_FPTOUI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1026_id660_at_idx73974
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1026_id660_at_idx73974
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTSD:%[0-9]+]]:spr = VCVTSD [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTSD]]
+    %1:fprb(s64) = COPY $d16
+    %0:fprb(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1029_id1557_at_idx74160
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1029_id1557_at_idx74160
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<8 x s16>)
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1030_id1558_at_idx74210
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1030_id1558_at_idx74210
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<4 x s32>)
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:_(<4 x s32>) = G_SEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1031_id1559_at_idx74260
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1031_id1559_at_idx74260
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SEXT]](<2 x s64>)
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1032_id1565_at_idx74310
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1032_id1565_at_idx74310
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTs2fd:%[0-9]+]]:dpr = VCVTs2fd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTs2fd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_SITOFP %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1033_id1569_at_idx74360
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1033_id1569_at_idx74360
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[SITOFP:%[0-9]+]]:_(<4 x s32>) = G_SITOFP [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SITOFP]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1034_id1573_at_idx74410
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1034_id1573_at_idx74410
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTs2hd:%[0-9]+]]:dpr = VCVTs2hd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTs2hd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_SITOFP %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1035_id1577_at_idx74460
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1035_id1577_at_idx74460
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[SITOFP:%[0-9]+]]:_(<8 x s16>) = G_SITOFP [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SITOFP]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1036_id2043_at_idx74510
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1036_id2043_at_idx74510
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VSITOD:%[0-9]+]]:dpr = VSITOD [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSITOD]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s64) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1037_id2045_at_idx74576
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1037_id2045_at_idx74576
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VSITOS:%[0-9]+]]:spr = VSITOS [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VSITOS]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s32) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1039_id1545_at_idx74708
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1039_id1545_at_idx74708
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<8 x s8>) = G_TRUNC [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<8 x s8>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:fprb(<8 x s8>) = G_TRUNC %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1040_id1546_at_idx74758
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1040_id1546_at_idx74758
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<4 x s16>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<4 x s16>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:fprb(<4 x s16>) = G_TRUNC %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1041_id1547_at_idx74808
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1041_id1547_at_idx74808
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; SELECTED: [[TRUNC:%[0-9]+]]:fprb(<2 x s32>) = G_TRUNC [[DEF]](<2 x s64>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[TRUNC]](<2 x s32>)
+    %1:_(<2 x s64>) = IMPLICIT_DEF
+    %0:fprb(<2 x s32>) = G_TRUNC %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1042_id1566_at_idx74858
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1042_id1566_at_idx74858
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTu2fd:%[0-9]+]]:dpr = VCVTu2fd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTu2fd]]
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:fprb(<2 x s32>) = G_UITOFP %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1043_id1570_at_idx74908
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1043_id1570_at_idx74908
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; SELECTED: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[DEF]](<4 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[UITOFP]](<4 x s32>)
+    %1:_(<4 x s32>) = IMPLICIT_DEF
+    %0:_(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1044_id1574_at_idx74958
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1044_id1574_at_idx74958
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:dpr = COPY $d16
+    ; SELECTED: [[VCVTu2hd:%[0-9]+]]:dpr = VCVTu2hd [[COPY]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VCVTu2hd]]
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:fprb(<4 x s16>) = G_UITOFP %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1045_id1578_at_idx75008
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1045_id1578_at_idx75008
+    ; SELECTED: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; SELECTED: [[UITOFP:%[0-9]+]]:_(<8 x s16>) = G_UITOFP [[DEF]](<8 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[UITOFP]](<8 x s16>)
+    %1:_(<8 x s16>) = IMPLICIT_DEF
+    %0:_(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1046_id2048_at_idx75058
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1046_id2048_at_idx75058
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VUITOD:%[0-9]+]]:dpr = VUITOD [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VUITOD]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s64) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1047_id2050_at_idx75124
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: gprb }
+liveins:
+  - { reg: '$lr', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; SELECTED-LABEL: name: test_rule1047_id2050_at_idx75124
+    ; SELECTED: liveins: $lr
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr = COPY $lr
+    ; SELECTED: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
+    ; SELECTED: [[VUITOS:%[0-9]+]]:spr = VUITOS [[COPY1]], 14, $noreg
+    ; SELECTED: $noreg = PATCHABLE_RET [[VUITOS]]
+    %1:gprb(s32) = COPY $lr
+    %0:fprb(s32) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1049_id1560_at_idx75256
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1049_id1560_at_idx75256
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<8 x s8>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<8 x s16>)
+    %1:fprb(<8 x s8>) = COPY $d16
+    %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1050_id1561_at_idx75306
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1050_id1561_at_idx75306
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<4 x s16>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<4 x s32>)
+    %1:fprb(<4 x s16>) = COPY $d16
+    %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1051_id1562_at_idx75356
+alignment:       2
+legalized:       true
+regBankSelected: true
+failedISel:      true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fprb }
+liveins:
+  - { reg: '$d16', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d16
+
+    ; SELECTED-LABEL: name: test_rule1051_id1562_at_idx75356
+    ; SELECTED: liveins: $d16
+    ; SELECTED: [[COPY:%[0-9]+]]:fprb(<2 x s32>) = COPY $d16
+    ; SELECTED: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+    ; SELECTED: $noreg = PATCHABLE_RET [[ZEXT]](<2 x s64>)
+    %1:fprb(<2 x s32>) = COPY $d16
+    %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1052_id34_at_idx75406
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors:
+
+    ; SELECTED-LABEL: name: test_rule1052_id34_at_idx75406
+    ; SELECTED: successors:
+    ; SELECTED: B %bb.0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_BR %bb.0
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1053_id291_at_idx75428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors:
+
+    ; SELECTED-LABEL: name: test_rule1053_id291_at_idx75428
+    ; SELECTED: successors:
+    ; SELECTED: B %bb.0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_BR %bb.0
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1054_id590_at_idx75461
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors:
+
+    ; SELECTED-LABEL: name: test_rule1054_id590_at_idx75461
+    ; SELECTED: successors:
+    ; SELECTED: B %bb.0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_BR %bb.0
+    $noreg = PATCHABLE_RET
+
+...
Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir
@@ -0,0 +1,16403 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+# RUN: llc -mtriple arm-- -run-pass instruction-select-testgen \
+# RUN:     -testgen-exclude-rules=2,3,18,19,20,21,22,23,24,25,26,27,28,29,30,39,40,41,42,47,48,49,50,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,79,80,93,94,95,96,98,99,100,101,102,103,104,105,106,107,108,109,122,123,125,126,127,128,184,185,186,187,190,191,212,219,220,221,222,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,592,593,594,595,707,708,709,710,711,719,720,721,722,723,726,727,728,729,730,739,740,741,760,761,762,781,782,799,800,801,802,803,819,820,823,826,833,836,843,848,858,859,864,865,866,877,878,1001,1004,1010,1011,1018,1025,1027,1028,1038,1048 \
+# RUN:     -testgen-set-all-features -verify-machineinstrs -simplify-mir %s \
+# RUN:     -o - 2>&1 | FileCheck %s --check-prefix=TESTGEND
+#
+# TESTGEND:       ---
+# TESTGEND:       name:            test_return
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule0
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:         - { id: 9, class: gprb }
+# TESTGEND:         - { id: 10, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%9' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %9:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %10:gprb(s32) = G_CONSTANT 24
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %3:gprb(s32) = G_SHL %9, %10
+# TESTGEND:           %2:gprb(s32) = G_ASHR %3, %8
+# TESTGEND:           %1:gprb(s32) = G_LSHR %9, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:         - { id: 7, class: gprb }
+# TESTGEND:         - { id: 8, class: gprb }
+# TESTGEND:         - { id: 9, class: gprb }
+# TESTGEND:         - { id: 10, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%9' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %9:gprb(s32) = COPY $lr
+# TESTGEND:           %8:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %10:gprb(s32) = G_CONSTANT 24
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %7:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %3:gprb(s32) = G_SHL %9, %10
+# TESTGEND:           %2:gprb(s32) = G_ASHR %3, %8
+# TESTGEND:           %1:gprb(s32) = G_LSHR %9, %7
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %5
+# TESTGEND:           %4:gprb(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %4(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule4
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %0:gprb(s32) = G_LSHR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule5
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 8
+# TESTGEND:           %0:gprb(s32) = G_LSHR %3, %4
+# TESTGEND:           %1:gprb(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule6
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule7
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule8
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule9
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule10
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule11
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule12
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule13
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r0
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %3, %4
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule14
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule15
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule16
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule17
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %5:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.cdp2), %0(s32), %1(s32), %2(s32), %3(s32), %4(s32), %5(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule31
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule32
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule33
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule34
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule35
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule36
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16711935
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule37
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule38
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.uxtb16), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule43
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule44
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule45
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule46
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %5:gprb(s32) = COPY $lr
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %3:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcr2), %0(s32), %1(s32), %5(s32), %2(s32), %3(s32), %4(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule51
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
+# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule52
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:         - { id: 5, class: gprb }
+# TESTGEND:         - { id: 6, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %5:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %6:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %4:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %1:gprb(s32) = G_ASHR %5, %6
+# TESTGEND:           %0:gprb(s32) = G_ASHR %3, %4
+# TESTGEND:           %2:gprb(s32) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule69
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule70
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule71
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule72
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:         - { id: 4, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %4:gprb(s32) = COPY $r0
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.mcrr2), %0(s32), %1(s32), %3(s32), %4(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule73
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule74
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule75
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule76
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule77
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule78
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %4:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %0(<2 x s64>), %4(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule81
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule82
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule83
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule84
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule85
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule86
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule87
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule88
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule89
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule90
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule91
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule92
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule97
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule110
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule111
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule112
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule113
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule114
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule115
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule116
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule117
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule118
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule119
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule120
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule121
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %5:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule124
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 249
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule129
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule130
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule131
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule132
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule133
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule134
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule135
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule136
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule137
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.undefined), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule138
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dmb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule139
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dsb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule140
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.isb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule141
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule142
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.dbg), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule143
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule144
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule145
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule146
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule147
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule148
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule149
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule150
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule151
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule152
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule153
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule154
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule155
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule156
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule157
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule158
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule159
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.space), %0(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule160
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule161
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule162
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule163
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule164
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule165
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule166
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule167
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule168
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule169
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule170
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule171
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule172
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule173
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule174
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule175
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule176
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule177
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule178
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule179
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule180
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule181
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule182
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule183
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule188
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule189
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %3:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 16
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %3
+# TESTGEND:           %1:gprb(s32) = G_ASHR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule192
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule193
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule194
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule195
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule196
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule197
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule198
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FNEG %4
+# TESTGEND:           %2:fprb(s64) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule199
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FNEG %4
+# TESTGEND:           %2:fprb(s32) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule200
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule201
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule202
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule203
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule204
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule205
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule206
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:_(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule207
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:_(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule208
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:_(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule209
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %1:_(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:_(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule210
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %1:_(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:_(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule211
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %1:_(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:_(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule213
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FMA %1, %3, %4
+# TESTGEND:           %2:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule214
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FMA %1, %3, %4
+# TESTGEND:           %2:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule215
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %5:fprb(s64) = COPY $d18
+# TESTGEND:           %4:fprb(s64) = COPY $d17
+# TESTGEND:           %3:fprb(s64) = COPY $d16
+# TESTGEND:           %1:fprb(s64) = G_FNEG %5
+# TESTGEND:           %0:fprb(s64) = G_FMA %3, %1, %4
+# TESTGEND:           %2:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule216
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:         - { id: 5, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %5:fprb(s32) = COPY $s4
+# TESTGEND:           %4:fprb(s32) = COPY $s2
+# TESTGEND:           %3:fprb(s32) = COPY $s0
+# TESTGEND:           %1:fprb(s32) = G_FNEG %5
+# TESTGEND:           %0:fprb(s32) = G_FMA %3, %1, %4
+# TESTGEND:           %2:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule217
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule218
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:         - { id: 3, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$r1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0, $r1
+#
+# TESTGEND:           %3:gprb(s32) = COPY $r1
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC intrinsic(@llvm.arm.usada8), %1(s32), %2(s32), %3(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule223
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vtbx1), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule224
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule225
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule226
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule227
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule244
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s8>), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule245
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s16>), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule246
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s32>), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule248
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d18
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(s64), %2(s64), %3(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule249
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule250
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<8 x s16>), %2(<8 x s16>), %3(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule251
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule253
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vbsl), %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule322
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule323
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule324
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule325
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule326
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule327
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule328
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule329
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule330
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule331
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule332
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule333
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule334
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule335
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule336
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule337
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule338
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule339
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule340
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule341
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule342
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule343
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule344
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule345
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrhaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule346
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule347
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule348
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule349
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule350
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule351
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule352
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule353
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqadds), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule354
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule355
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule356
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule357
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule358
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule359
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule360
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule361
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqaddu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule362
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule363
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule364
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vraddhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule365
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule366
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmulp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule367
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule368
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule369
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule370
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule371
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule372
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule373
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule374
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule375
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule376
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vmullp), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule377
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule378
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqdmull), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule379
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule380
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule381
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule382
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule383
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule384
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubs), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule385
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule386
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule387
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule388
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule389
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule390
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vhsubu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule391
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule392
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule393
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule394
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule395
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule396
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule397
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule398
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubs), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule399
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule400
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule401
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule402
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule403
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule404
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule405
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule406
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqsubu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule407
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule408
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule409
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsubhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule410
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule411
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule412
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule413
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacge), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule414
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule415
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule416
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule417
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vacgt), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule418
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule419
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule420
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule421
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule422
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule423
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule424
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule425
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule426
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule427
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule428
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule429
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabdu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule430
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule431
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule432
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule433
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vabds), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule434
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule435
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule436
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule437
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule438
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule439
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s16>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule440
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s32>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule441
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(s64), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule442
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<8 x s16>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule443
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<4 x s32>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule444
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadals), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule445
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s16>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule446
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s32>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule447
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(s64), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule448
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<8 x s16>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule449
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<4 x s32>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule450
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpadalu), %1(<2 x s64>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule451
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule452
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule453
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule454
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule455
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule456
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule457
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule458
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmaxs), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule459
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule460
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule461
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule462
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule463
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule464
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpminu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule465
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule466
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpmins), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule467
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule468
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule469
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule470
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecps), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule471
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule472
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule473
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule474
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule475
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule476
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule477
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule478
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule479
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule480
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule481
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule482
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule483
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule484
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule485
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule486
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule487
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule488
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule489
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule490
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule491
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule492
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule493
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule494
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule495
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule496
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule497
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule498
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule499
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule500
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule501
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule502
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule503
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule504
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule505
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule506
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule507
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule508
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule509
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule510
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule511
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule512
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule513
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule514
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule515
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule516
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule517
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule518
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule519
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule520
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule521
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule522
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule523
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule524
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule525
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule526
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule527
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule528
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule529
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule530
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshifts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule531
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule532
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule533
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule534
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule535
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule536
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule537
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule538
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqrshiftu), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule539
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule540
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aese), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule541
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule542
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule564
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule565
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule566
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule567
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule568
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule569
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule570
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule571
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule572
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule573
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule574
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule575
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule576
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule577
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sel), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule578
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule579
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule580
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.sadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule581
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule582
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule583
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.ssub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule584
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uasx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule585
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule586
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.uadd8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule587
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usax), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule588
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub16), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule589
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.usub8), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule590
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 255
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule591
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %2:gprb(s32) = G_CONSTANT 65535
+# TESTGEND:           %0:gprb(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule596
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule597
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule598
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule599
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule600
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule601
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddls), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule602
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule603
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule604
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule605
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule606
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule607
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vpaddlu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule608
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule609
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule610
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule611
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule612
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule613
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrecpe), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule614
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule615
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule616
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule617
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule618
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule619
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrsqrte), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule620
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule621
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule622
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule623
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule624
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule625
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqabs), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule626
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule627
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule628
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule629
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule630
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule631
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqneg), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule632
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule633
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule634
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule635
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule636
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule637
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcls), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule638
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule639
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule640
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovns), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule641
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule642
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule643
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule644
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule645
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule646
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vqmovnsu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule647
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule648
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule649
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule650
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule651
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule652
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtas), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule653
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule654
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtau), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule655
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule656
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule657
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule658
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule659
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule660
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtns), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule661
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule662
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtnu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule663
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule664
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule665
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule666
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule667
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule668
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtps), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule669
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule670
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtpu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule671
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule672
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule673
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule674
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule675
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule676
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtms), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule677
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule678
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtmu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule679
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvtfp2hf), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule680
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vcvthf2fp), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule681
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule682
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule683
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule684
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintn), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule685
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule686
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule687
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule688
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintx), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule689
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule690
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule691
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule692
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrinta), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule693
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule694
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule695
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule696
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintz), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule697
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule698
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule699
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule700
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintm), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule701
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule702
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule703
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule704
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.arm.neon.vrintp), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule705
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesimc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule706
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.arm.neon.aesmc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule712
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gprb(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.get.fpscr)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule713
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%0' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %0:gprb(s32) = COPY $lr
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.set.fpscr), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule714
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule715
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.arm.clrex)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule716
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule717
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule718
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule724
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule725
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %2:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_CONSTANT 1
+# TESTGEND:           %1:gprb(s32) = G_SUB %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule731
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(s64) = COPY $d18
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %4
+# TESTGEND:           %1:fprb(s64) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule732
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %4:fprb(s32) = COPY $s4
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %4
+# TESTGEND:           %1:fprb(s32) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule733
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fprb(<2 x s32>) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule734
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FNEG %4
+# TESTGEND:           %1:_(<4 x s32>) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule735
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(s64) = COPY $d18
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %4
+# TESTGEND:           %1:fprb(s64) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule736
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %4:fprb(s32) = COPY $s4
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %4
+# TESTGEND:           %1:fprb(s32) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule737
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(s64) = COPY $d18
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %4
+# TESTGEND:           %1:fprb(s64) = G_FMA %2, %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule738
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %4:fprb(s32) = COPY $s4
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %4
+# TESTGEND:           %1:fprb(s32) = G_FMA %2, %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule742
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule743
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule744
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule745
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule746
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule747
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule748
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule749
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule750
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule751
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule752
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule753
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule754
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule755
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule756
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule757
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule758
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule759
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule763
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule764
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule765
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule766
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule767
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule768
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule769
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_FADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule770
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_FADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule771
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_FADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule772
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_FADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule773
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %3
+# TESTGEND:           %1:fprb(s64) = G_FMUL %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule774
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %3
+# TESTGEND:           %1:fprb(s32) = G_FMUL %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule775
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %3
+# TESTGEND:           %1:fprb(s64) = G_FMUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule776
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %3
+# TESTGEND:           %1:fprb(s32) = G_FMUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule777
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_FSUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule778
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_FSUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule779
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_FSUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule780
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_FSUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule783
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<8 x s8>) = COPY $d18
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<8 x s8>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule784
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<4 x s16>) = COPY $d18
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<4 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule785
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fprb(<2 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule786
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<16 x s8>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule787
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule788
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:         - { id: 4, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %4:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule789
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule790
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule791
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule792
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:_(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule793
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:_(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule794
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:_(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule795
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %4:fprb(s64) = COPY $d18
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FMA %2, %3, %4
+# TESTGEND:           %1:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule796
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:         - { id: 4, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %4:fprb(s32) = COPY $s4
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FMA %2, %3, %4
+# TESTGEND:           %1:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule797
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d17
+# TESTGEND:           %2:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FMUL %2, %3
+# TESTGEND:           %1:fprb(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule798
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %3:fprb(s32) = COPY $s2
+# TESTGEND:           %2:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FMUL %2, %3
+# TESTGEND:           %1:fprb(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule804
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(s64) = COPY $d18
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule805
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s4', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2, $s4
+#
+# TESTGEND:           %3:fprb(s32) = COPY $s4
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule806
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:         - { id: 3, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d18', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17, $d18
+#
+# TESTGEND:           %3:fprb(<2 x s32>) = COPY $d18
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule807
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:         - { id: 3, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %3:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule808
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule809
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule810
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule811
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule812
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule813
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule814
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule815
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule816
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule817
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule818
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule821
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule822
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule824
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule825
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule827
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule828
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule829
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule830
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule831
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule832
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule834
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule835
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule837
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule838
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule839
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule840
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule841
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule842
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s2
+#
+# TESTGEND:           %2:fprb(s32) = COPY $s2
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule844
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule845
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule846
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule847
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule849
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule850
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule851
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule852
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule853
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule854
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule855
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule856
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule857
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule860
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule861
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule862
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_SDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule863
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_SDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule867
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<8 x s8>) = COPY $d17
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule868
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<4 x s16>) = COPY $d17
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule869
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule870
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule871
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule872
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule873
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(s64) = COPY $d17
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule874
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule875
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_UDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule876
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:         - { id: 2, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$r0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr, $r0
+#
+# TESTGEND:           %2:gprb(s32) = COPY $r0
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_UDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule879
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:         - { id: 2, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d17', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16, $d17
+#
+# TESTGEND:           %2:fprb(<2 x s32>) = COPY $d17
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule880
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:         - { id: 2, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %2:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule881
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule882
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:_(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule883
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule884
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:gprb(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule885
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule886
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule887
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule888
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule889
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule891
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule892
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule893
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule895
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule896
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule897
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule898
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule901
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule902
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule903
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule916
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule917
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule918
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule919
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule921
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule922
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule923
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule925
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule926
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule927
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule928
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule931
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule932
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule933
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule946
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule947
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule948
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule950
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule951
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule952
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule954
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule955
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule956
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule959
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule960
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule961
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule972
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule973
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule974
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule976
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule977
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule978
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule980
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule981
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule982
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<16 x s8>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule985
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule986
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule987
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule998
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule999
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1000
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:gprb(s32) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1002
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s64) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1003
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s32) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1005
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1006
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1007
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1008
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1009
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:fprb(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1012
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1013
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1014
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FPTOSI %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1015
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1016
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:gprb(s32) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1017
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:gprb(s32) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1019
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1020
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1021
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_FPTOUI %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1022
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1023
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:gprb(s32) = G_FPTOUI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1024
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fprb(s32) = COPY $s0
+# TESTGEND:           %0:gprb(s32) = G_FPTOUI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1026
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(s64) = COPY $d16
+# TESTGEND:           %0:fprb(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1029
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1030
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:_(<4 x s32>) = G_SEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1031
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1032
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_SITOFP %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1033
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1034
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_SITOFP %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1035
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1036
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s64) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1037
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s32) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1039
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<8 x s8>) = G_TRUNC %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1040
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<4 x s16>) = G_TRUNC %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1041
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<2 x s64>) = IMPLICIT_DEF
+# TESTGEND:           %0:fprb(<2 x s32>) = G_TRUNC %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1042
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:fprb(<2 x s32>) = G_UITOFP %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1043
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<4 x s32>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1044
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:fprb(<4 x s16>) = G_UITOFP %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1045
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: _ }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %1:_(<8 x s16>) = IMPLICIT_DEF
+# TESTGEND:           %0:_(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1046
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s64) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1047
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fprb }
+# TESTGEND:         - { id: 1, class: gprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$lr', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $lr
+#
+# TESTGEND:           %1:gprb(s32) = COPY $lr
+# TESTGEND:           %0:fprb(s32) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1049
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<8 x s8>) = COPY $d16
+# TESTGEND:           %0:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1050
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<4 x s16>) = COPY $d16
+# TESTGEND:           %0:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1051
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       failedISel:      true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: _ }
+# TESTGEND:         - { id: 1, class: fprb }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d16', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d16
+#
+# TESTGEND:           %1:fprb(<2 x s32>) = COPY $d16
+# TESTGEND:           %0:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1052
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           successors:
+#
+# TESTGEND:           G_BR %bb.0
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1053
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           successors:
+#
+# TESTGEND:           G_BR %bb.0
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1054
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           successors:
+#
+# TESTGEND:           G_BR %bb.0
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...