Index: test/CodeGen/AArch64/GlobalISel/arm64-instruction-select-testgen-selected.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/GlobalISel/arm64-instruction-select-testgen-selected.mir
@@ -0,0 +1,48678 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+#
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-- -run-pass instruction-select \
+# RUN:     -testgen-set-all-features -disable-gisel-legality-check \
+# RUN:     -verify-machineinstrs -simplify-mir %s -o - 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=SELECTED
+#
+# Test if this file is in sync with the current state of the selector:
+# RUN: cat %s | FileCheck --check-prefix=TESTGEND \
+# RUN:     %S/arm64-instruction-select-testgen-testgend.mir
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+
+  define void @test_return() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule0_id191_at_idx0() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1_id192_at_idx75() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule2_id193_at_idx150() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule3_id194_at_idx225() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule4_id195_at_idx300() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule5_id189_at_idx375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule6_id190_at_idx450() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule7_id1996_at_idx525() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule8_id1997_at_idx661() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule9_id182_at_idx797() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule10_id183_at_idx851() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule11_id185_at_idx905() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule12_id186_at_idx959() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule13_id187_at_idx1013() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule14_id188_at_idx1067() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule15_id228_at_idx1121() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule16_id229_at_idx1176() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule17_id231_at_idx1231() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule18_id232_at_idx1285() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule19_id233_at_idx1339() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule20_id2236_at_idx1393() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule21_id2237_at_idx1449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule22_id2238_at_idx1505() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule27_id2243_at_idx1781() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule28_id2244_at_idx1837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule29_id2245_at_idx1893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule30_id2246_at_idx1949() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule34_id2250_at_idx2173() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule35_id1991_at_idx2227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule36_id1992_at_idx2352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule37_id3729_at_idx2477() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule38_id3730_at_idx2531() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule39_id1999_at_idx2585() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule40_id2000_at_idx2722() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule41_id24_at_idx2859() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule42_id25_at_idx2913() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule43_id4111_at_idx2967() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule44_id4112_at_idx3104() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule45_id2002_at_idx3241() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule46_id2003_at_idx3378() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule47_id3741_at_idx3515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule48_id3742_at_idx3641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule49_id56_at_idx3767() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule50_id58_at_idx3893() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule51_id2017_at_idx4019() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule52_id2018_at_idx4090() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule53_id57_at_idx4161() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule54_id59_at_idx4287() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule55_id206_at_idx4413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule56_id207_at_idx4488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule57_id208_at_idx4563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule58_id209_at_idx4638() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule59_id210_at_idx4713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule60_id204_at_idx4788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule61_id205_at_idx4863() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule62_id2651_at_idx4938() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule63_id2652_at_idx5048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule64_id2653_at_idx5158() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule65_id2654_at_idx5268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule66_id1154_at_idx5378() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule67_id1155_at_idx5474() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule68_id1156_at_idx5570() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule69_id1157_at_idx5666() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule70_id1158_at_idx5762() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule71_id1159_at_idx5858() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule72_id1160_at_idx5954() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule73_id1161_at_idx6050() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule74_id1296_at_idx6146() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule75_id1298_at_idx6242() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule76_id1300_at_idx6338() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule77_id1302_at_idx6434() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule78_id2458_at_idx6530() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule79_id2459_at_idx6626() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule80_id2460_at_idx6722() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule81_id2461_at_idx6816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule82_id3039_at_idx6910() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule83_id3040_at_idx7010() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule84_id1987_at_idx7110() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule85_id1988_at_idx7195() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule86_id4109_at_idx7280() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule87_id4110_at_idx7365() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule88_id1985_at_idx7450() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule89_id1986_at_idx7535() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule90_id2148_at_idx7620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule91_id2149_at_idx7695() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule92_id2150_at_idx7770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule93_id2170_at_idx7845() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule94_id2171_at_idx7920() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule95_id2172_at_idx7995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule96_id2146_at_idx8070() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule98_id2178_at_idx8220() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule99_id2179_at_idx8295() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule100_id1993_at_idx8370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule101_id1994_at_idx8478() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule102_id3863_at_idx8586() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule103_id3865_at_idx8698() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule104_id3867_at_idx8810() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule105_id3881_at_idx8922() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule106_id3883_at_idx9034() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule107_id3885_at_idx9146() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule108_id1254_at_idx9258() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule109_id1256_at_idx9370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule110_id1258_at_idx9482() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule111_id1320_at_idx9594() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule112_id1322_at_idx9706() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule113_id1324_at_idx9818() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule114_id1989_at_idx9930() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule115_id1990_at_idx10027() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule116_id197_at_idx10124() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule117_id198_at_idx10178() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule118_id200_at_idx10232() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule119_id201_at_idx10286() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule120_id202_at_idx10340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule121_id203_at_idx10394() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule122_id236_at_idx10448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule123_id237_at_idx10502() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule124_id239_at_idx10556() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule125_id240_at_idx10610() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule126_id241_at_idx10664() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule127_id242_at_idx10718() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule128_id2129_at_idx10772() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule129_id2130_at_idx10828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule130_id2131_at_idx10884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule135_id2136_at_idx11160() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule136_id2137_at_idx11216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule137_id2138_at_idx11272() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule138_id2139_at_idx11328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule143_id2156_at_idx11606() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule145_id2158_at_idx11718() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule146_id2159_at_idx11774() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule150_id2163_at_idx11994() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule152_id2165_at_idx12106() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule154_id2167_at_idx12218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule155_id2168_at_idx12274() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule157_id2254_at_idx12386() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule158_id2255_at_idx12442() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule159_id2256_at_idx12498() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule164_id2261_at_idx12774() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule165_id2262_at_idx12830() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule166_id2263_at_idx12886() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule167_id2264_at_idx12942() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule172_id1606_at_idx13222() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule173_id1607_at_idx13308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule174_id1608_at_idx13394() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule175_id1609_at_idx13480() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule176_id1610_at_idx13566() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule177_id1611_at_idx13652() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule178_id1612_at_idx13738() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule179_id1639_at_idx13824() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule180_id1640_at_idx13910() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule181_id1641_at_idx13996() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule182_id1642_at_idx14082() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule183_id1643_at_idx14168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule184_id1644_at_idx14254() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule185_id1645_at_idx14340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule186_id2915_at_idx14426() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule187_id2916_at_idx14510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule188_id1558_at_idx14594() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule189_id1559_at_idx14668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule190_id1564_at_idx14742() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule191_id1565_at_idx14816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule192_id1570_at_idx14890() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule193_id1573_at_idx14964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule194_id1593_at_idx15038() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule195_id1594_at_idx15112() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule196_id1595_at_idx15186() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule197_id1613_at_idx15260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule198_id1614_at_idx15334() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule199_id1615_at_idx15408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule200_id1616_at_idx15482() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule201_id1617_at_idx15556() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule202_id1618_at_idx15630() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule203_id1633_at_idx15704() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule204_id1634_at_idx15778() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule205_id1635_at_idx15852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule206_id1636_at_idx15926() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule207_id1637_at_idx16000() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule208_id1638_at_idx16074() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule209_id1685_at_idx16148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule210_id1686_at_idx16222() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule211_id1687_at_idx16296() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule212_id1695_at_idx16370() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule213_id1696_at_idx16444() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule214_id1697_at_idx16518() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule215_id2903_at_idx16592() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule216_id2904_at_idx16664() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule217_id2905_at_idx16736() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule218_id2906_at_idx16808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule221_id2909_at_idx17024() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule222_id2910_at_idx17096() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule223_id2911_at_idx17168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule224_id2912_at_idx17240() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule227_id1963_at_idx17456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule228_id1964_at_idx17510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule229_id9_at_idx17564() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule230_id10_at_idx17617() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule231_id11_at_idx17670() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule232_id12_at_idx17723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule233_id1578_at_idx17776() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule234_id1579_at_idx17847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule235_id1580_at_idx17918() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule236_id1581_at_idx17989() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule237_id1582_at_idx18060() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule238_id1583_at_idx18131() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule239_id1584_at_idx18202() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule240_id1585_at_idx18273() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule241_id1586_at_idx18344() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule242_id1587_at_idx18415() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule243_id1588_at_idx18486() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule244_id1589_at_idx18557() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule245_id1590_at_idx18628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule246_id1591_at_idx18699() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule247_id1592_at_idx18770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule248_id1680_at_idx18841() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule249_id1681_at_idx18912() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule250_id1682_at_idx18983() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule251_id1683_at_idx19054() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule252_id1684_at_idx19125() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule253_id3809_at_idx19196() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule254_id3810_at_idx19288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule255_id3811_at_idx19380() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule256_id3812_at_idx19472() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule257_id3813_at_idx19564() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule258_id3814_at_idx19656() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule259_id3815_at_idx19748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule260_id3816_at_idx19840() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule261_id3817_at_idx19932() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule262_id3818_at_idx20024() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule263_id3819_at_idx20116() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule264_id3820_at_idx20208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule265_id3875_at_idx20300() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule266_id3877_at_idx20392() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule267_id3879_at_idx20484() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule268_id3893_at_idx20576() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule269_id3895_at_idx20668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule270_id3897_at_idx20760() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule271_id3791_at_idx20852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule272_id3792_at_idx20932() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule273_id3793_at_idx21012() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule274_id3794_at_idx21092() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule275_id3795_at_idx21172() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule276_id3796_at_idx21252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule277_id3797_at_idx21332() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule278_id3798_at_idx21412() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule279_id3799_at_idx21492() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule280_id3800_at_idx21572() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule281_id3801_at_idx21652() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule282_id3802_at_idx21732() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule283_id947_at_idx21812() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule284_id948_at_idx21904() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule285_id949_at_idx21996() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule286_id950_at_idx22088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule287_id951_at_idx22180() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule288_id952_at_idx22272() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule289_id1058_at_idx22364() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule290_id1059_at_idx22456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule291_id1060_at_idx22548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule292_id1061_at_idx22640() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule293_id1062_at_idx22732() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule294_id1063_at_idx22824() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule295_id1278_at_idx22916() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule296_id1280_at_idx23008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule297_id1282_at_idx23100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule298_id1338_at_idx23192() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule299_id1340_at_idx23284() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule300_id1342_at_idx23376() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule301_id673_at_idx23468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule302_id674_at_idx23548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule303_id675_at_idx23628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule304_id676_at_idx23708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule305_id677_at_idx23788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule306_id678_at_idx23868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule307_id717_at_idx23948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule308_id718_at_idx24028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule309_id719_at_idx24108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule310_id720_at_idx24188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule311_id721_at_idx24268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule312_id722_at_idx24348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule313_id3751_at_idx24428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule314_id3752_at_idx24510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule315_id90_at_idx24592() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule316_id91_at_idx24674() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule317_id3771_at_idx24756() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule318_id3772_at_idx24838() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule319_id102_at_idx24920() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule320_id103_at_idx25002() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule321_id1284_at_idx25084() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule322_id1286_at_idx25176() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule323_id1288_at_idx25268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule324_id1344_at_idx25360() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule325_id1346_at_idx25452() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule326_id1348_at_idx25544() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule327_id3755_at_idx25636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule328_id3757_at_idx25718() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule329_id94_at_idx25800() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule330_id95_at_idx25882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule331_id3756_at_idx25964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule332_id3758_at_idx26046() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule333_id452_at_idx26128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule334_id454_at_idx26208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule335_id456_at_idx26288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule336_id1260_at_idx26368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule337_id1262_at_idx26448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule338_id1264_at_idx26528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule339_id2369_at_idx26608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule340_id2370_at_idx26714() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule341_id2371_at_idx26820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule342_id2372_at_idx26926() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule343_id1266_at_idx27032() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule344_id1268_at_idx27128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule345_id1270_at_idx27224() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule346_id1326_at_idx27320() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule347_id1328_at_idx27416() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule348_id1330_at_idx27512() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule349_id1308_at_idx27608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule350_id1310_at_idx27704() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule351_id1312_at_idx27800() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule352_id1356_at_idx27896() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule353_id1358_at_idx27992() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule354_id1360_at_idx28088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule355_id1736_at_idx28184() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule356_id1737_at_idx28256() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule357_id1738_at_idx28328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule358_id1739_at_idx28400() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule359_id1740_at_idx28472() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule360_id1741_at_idx28544() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule361_id1742_at_idx28616() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule362_id2575_at_idx28688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule363_id2576_at_idx28758() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule364_id62_at_idx28828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule365_id63_at_idx28888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule366_id64_at_idx28948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule367_id65_at_idx29008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule368_id66_at_idx29068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule369_id67_at_idx29128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule370_id68_at_idx29188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule371_id69_at_idx29248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule372_id710_at_idx29308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule373_id711_at_idx29368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule374_id712_at_idx29428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule375_id713_at_idx29488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule376_id714_at_idx29548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule377_id715_at_idx29608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule378_id716_at_idx29668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule379_id741_at_idx29728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule380_id742_at_idx29788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule381_id743_at_idx29848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule382_id744_at_idx29908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule383_id745_at_idx29968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule384_id746_at_idx30028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule385_id747_at_idx30088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule386_id758_at_idx30148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule387_id759_at_idx30208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule388_id760_at_idx30268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule389_id761_at_idx30328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule390_id762_at_idx30388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule391_id763_at_idx30448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule392_id764_at_idx30508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule393_id807_at_idx30568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule394_id808_at_idx30628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule395_id809_at_idx30688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule396_id810_at_idx30748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule397_id811_at_idx30808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule398_id812_at_idx30868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule399_id813_at_idx30928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule400_id814_at_idx30988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule401_id815_at_idx31048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule402_id816_at_idx31108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule403_id817_at_idx31168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule404_id818_at_idx31228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule405_id819_at_idx31288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule406_id820_at_idx31348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule407_id821_at_idx31408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule408_id822_at_idx31468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule409_id823_at_idx31528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule410_id824_at_idx31588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule411_id825_at_idx31648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule412_id826_at_idx31708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule413_id852_at_idx31768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule414_id853_at_idx31828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule415_id854_at_idx31888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule416_id855_at_idx31948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule417_id856_at_idx32008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule418_id862_at_idx32068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule419_id863_at_idx32128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule420_id864_at_idx32188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule421_id865_at_idx32248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule422_id866_at_idx32308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule423_id872_at_idx32368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule424_id873_at_idx32428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule425_id874_at_idx32488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule426_id875_at_idx32548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule427_id876_at_idx32608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule428_id882_at_idx32668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule429_id883_at_idx32728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule430_id884_at_idx32788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule431_id885_at_idx32848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule432_id886_at_idx32908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule433_id902_at_idx32968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule434_id903_at_idx33028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule435_id904_at_idx33088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule436_id905_at_idx33148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule437_id906_at_idx33208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule438_id912_at_idx33268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule439_id913_at_idx33328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule440_id914_at_idx33388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule441_id915_at_idx33448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule442_id916_at_idx33508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule443_id917_at_idx33568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule444_id918_at_idx33628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule445_id919_at_idx33688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule446_id920_at_idx33748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule447_id921_at_idx33808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule448_id945_at_idx33868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule449_id946_at_idx33928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule450_id953_at_idx33988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule451_id954_at_idx34048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule452_id955_at_idx34108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule453_id956_at_idx34168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule454_id957_at_idx34228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule455_id958_at_idx34288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule456_id959_at_idx34348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule457_id960_at_idx34408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule458_id961_at_idx34468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule459_id962_at_idx34528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule460_id963_at_idx34588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule461_id964_at_idx34648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule462_id965_at_idx34708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule463_id966_at_idx34768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule464_id967_at_idx34828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule465_id968_at_idx34888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule466_id969_at_idx34948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule467_id970_at_idx35008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule468_id971_at_idx35068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule469_id972_at_idx35128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule470_id973_at_idx35188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule471_id974_at_idx35248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule472_id975_at_idx35308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule473_id976_at_idx35368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule474_id983_at_idx35428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule475_id984_at_idx35488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule476_id985_at_idx35548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule477_id986_at_idx35608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule478_id987_at_idx35668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule479_id988_at_idx35728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule480_id995_at_idx35788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule481_id996_at_idx35848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule482_id997_at_idx35908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule483_id998_at_idx35968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule484_id999_at_idx36028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule485_id1000_at_idx36088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule486_id1001_at_idx36148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule487_id1002_at_idx36208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule488_id1003_at_idx36268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule489_id1004_at_idx36328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule490_id1005_at_idx36388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule491_id1006_at_idx36448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule492_id1007_at_idx36508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule493_id1008_at_idx36568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule494_id1009_at_idx36628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule495_id1010_at_idx36688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule496_id1011_at_idx36748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule497_id1012_at_idx36808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule498_id1013_at_idx36868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule499_id1014_at_idx36928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule500_id1015_at_idx36988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule501_id1016_at_idx37048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule502_id1017_at_idx37108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule503_id1018_at_idx37168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule504_id1019_at_idx37228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule505_id1020_at_idx37288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule506_id1021_at_idx37348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule507_id1022_at_idx37408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule508_id1023_at_idx37468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule509_id1024_at_idx37528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule510_id1025_at_idx37588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule511_id1026_at_idx37648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule512_id1027_at_idx37708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule513_id1028_at_idx37768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule514_id1029_at_idx37828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule515_id1030_at_idx37888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule516_id1031_at_idx37948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule517_id1032_at_idx38008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule518_id1033_at_idx38068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule519_id1034_at_idx38128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule520_id1035_at_idx38188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule521_id1036_at_idx38248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule522_id1037_at_idx38308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule523_id1038_at_idx38368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule524_id1039_at_idx38428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule525_id1040_at_idx38488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule526_id1041_at_idx38548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule527_id1042_at_idx38608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule528_id1043_at_idx38668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule529_id1044_at_idx38728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule530_id1045_at_idx38788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule531_id1046_at_idx38848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule532_id1047_at_idx38908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule533_id1048_at_idx38968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule534_id1049_at_idx39028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule535_id1050_at_idx39088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule536_id1064_at_idx39148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule537_id1065_at_idx39208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule538_id1066_at_idx39268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule539_id1067_at_idx39328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule540_id1068_at_idx39388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule541_id1069_at_idx39448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule542_id1070_at_idx39508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule543_id1071_at_idx39568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule544_id1072_at_idx39628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule545_id1073_at_idx39688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule546_id1074_at_idx39748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule547_id1075_at_idx39808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule548_id1076_at_idx39868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule549_id1077_at_idx39928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule550_id1078_at_idx39988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule551_id1079_at_idx40048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule552_id1080_at_idx40108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule553_id1081_at_idx40168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule554_id1082_at_idx40228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule555_id1083_at_idx40288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule556_id1084_at_idx40348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule557_id1085_at_idx40408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule558_id1086_at_idx40468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule559_id1087_at_idx40528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule560_id1094_at_idx40588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule561_id1095_at_idx40648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule562_id1096_at_idx40708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule563_id1097_at_idx40768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule564_id1098_at_idx40828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule565_id1099_at_idx40888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule566_id1106_at_idx40948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule567_id1107_at_idx41008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule568_id1108_at_idx41068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule569_id1109_at_idx41128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule570_id1110_at_idx41188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule571_id1111_at_idx41248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule572_id1112_at_idx41308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule573_id1113_at_idx41368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule574_id1114_at_idx41428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule575_id1115_at_idx41488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule576_id1116_at_idx41548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule577_id1117_at_idx41608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule578_id1118_at_idx41668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule579_id1119_at_idx41728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule580_id1120_at_idx41788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule581_id1121_at_idx41848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule582_id1122_at_idx41908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule583_id1123_at_idx41968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule584_id1124_at_idx42028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule585_id1125_at_idx42088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule586_id1126_at_idx42148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule587_id1127_at_idx42208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule588_id1128_at_idx42268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule589_id1129_at_idx42328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule590_id1130_at_idx42388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule591_id1131_at_idx42448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule592_id1132_at_idx42508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule593_id1133_at_idx42568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule594_id1134_at_idx42628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule595_id1135_at_idx42688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule596_id1136_at_idx42748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule597_id1137_at_idx42808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule598_id1138_at_idx42868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule599_id1139_at_idx42928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule600_id1140_at_idx42988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule601_id1141_at_idx43048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule602_id1142_at_idx43108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule603_id1143_at_idx43168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule604_id1144_at_idx43228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule605_id1145_at_idx43288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule606_id1146_at_idx43348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule607_id1147_at_idx43408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule608_id1148_at_idx43468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule609_id1149_at_idx43528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule610_id1150_at_idx43588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule611_id1151_at_idx43648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule612_id1152_at_idx43708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule613_id1153_at_idx43768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule614_id1183_at_idx43828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule615_id1184_at_idx43888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule616_id1185_at_idx43948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule617_id1186_at_idx44008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule618_id1187_at_idx44068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule619_id1188_at_idx44128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule620_id1189_at_idx44188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule621_id1196_at_idx44248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule622_id1197_at_idx44308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule623_id1198_at_idx44368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule624_id1199_at_idx44428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule625_id1200_at_idx44488() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule626_id1201_at_idx44548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule627_id1202_at_idx44608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule628_id1203_at_idx44668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule629_id1204_at_idx44728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule630_id1205_at_idx44788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule631_id1206_at_idx44848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule632_id1207_at_idx44908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule633_id1208_at_idx44968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule634_id1209_at_idx45028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule635_id1210_at_idx45088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule636_id1211_at_idx45148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule637_id1212_at_idx45208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule638_id1214_at_idx45268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule639_id1215_at_idx45328() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule640_id1216_at_idx45388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule641_id1217_at_idx45448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule642_id1218_at_idx45508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule643_id1219_at_idx45568() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule644_id1220_at_idx45628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule645_id1233_at_idx45688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule646_id1234_at_idx45748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule647_id1239_at_idx45808() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule648_id1240_at_idx45868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule649_id1241_at_idx45928() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule650_id1242_at_idx45988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule651_id1243_at_idx46048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule652_id1244_at_idx46108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule653_id1245_at_idx46168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule654_id1246_at_idx46228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule655_id1247_at_idx46288() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule656_id1248_at_idx46348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule657_id1249_at_idx46408() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule658_id1250_at_idx46468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule659_id1251_at_idx46528() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule660_id1252_at_idx46588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule661_id1253_at_idx46648() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule662_id1290_at_idx46708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule663_id1292_at_idx46768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule664_id1294_at_idx46828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule665_id1304_at_idx46888() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule666_id1306_at_idx46948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule667_id1350_at_idx47008() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule668_id1352_at_idx47068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule669_id1354_at_idx47128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule670_id1732_at_idx47188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule671_id1733_at_idx47248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule672_id1744_at_idx47308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule673_id1745_at_idx47368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule681_id1852_at_idx47848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule683_id1861_at_idx47968() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule685_id1870_at_idx48088() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule687_id1879_at_idx48208() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule690_id1907_at_idx48388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule692_id1909_at_idx48508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule694_id1914_at_idx48628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule696_id1920_at_idx48748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule698_id1979_at_idx48868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule699_id1980_at_idx48926() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule700_id1981_at_idx48984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule701_id1982_at_idx49042() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule702_id2457_at_idx49100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule703_id2542_at_idx49158() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule704_id2573_at_idx49216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule705_id2574_at_idx49274() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule706_id3395_at_idx49332() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule707_id3396_at_idx49390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule708_id3397_at_idx49448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule709_id3398_at_idx49506() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule710_id263_at_idx49564() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule711_id264_at_idx49612() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule712_id265_at_idx49660() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule713_id266_at_idx49708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule714_id267_at_idx49756() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule715_id268_at_idx49804() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule716_id269_at_idx49852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule717_id270_at_idx49900() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule718_id271_at_idx49948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule719_id272_at_idx49996() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule720_id273_at_idx50044() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule721_id274_at_idx50092() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule722_id275_at_idx50140() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule723_id276_at_idx50188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule724_id277_at_idx50236() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule725_id278_at_idx50284() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule726_id279_at_idx50332() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule727_id280_at_idx50380() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule728_id281_at_idx50428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule729_id282_at_idx50476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule730_id283_at_idx50524() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule731_id284_at_idx50572() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule732_id285_at_idx50620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule733_id286_at_idx50668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule734_id287_at_idx50716() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule735_id288_at_idx50764() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule736_id289_at_idx50812() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule737_id290_at_idx50860() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule738_id291_at_idx50908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule739_id292_at_idx50956() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule740_id293_at_idx51004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule741_id294_at_idx51052() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule742_id295_at_idx51100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule743_id296_at_idx51148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule744_id297_at_idx51196() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule745_id298_at_idx51244() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule746_id299_at_idx51292() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule747_id300_at_idx51340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule748_id301_at_idx51388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule749_id302_at_idx51436() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule750_id303_at_idx51484() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule751_id304_at_idx51532() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule752_id305_at_idx51580() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule753_id306_at_idx51628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule754_id307_at_idx51676() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule755_id308_at_idx51724() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule756_id309_at_idx51772() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule757_id310_at_idx51820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule758_id383_at_idx51868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule759_id384_at_idx51916() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule760_id385_at_idx51964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule761_id465_at_idx52012() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule762_id466_at_idx52060() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule763_id467_at_idx52108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule764_id468_at_idx52156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule765_id469_at_idx52204() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule766_id470_at_idx52252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule767_id544_at_idx52300() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule768_id545_at_idx52348() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule769_id546_at_idx52396() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule770_id547_at_idx52444() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule771_id548_at_idx52492() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule772_id549_at_idx52540() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule773_id550_at_idx52588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule774_id551_at_idx52636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule775_id552_at_idx52684() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule776_id553_at_idx52732() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule777_id554_at_idx52780() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule778_id555_at_idx52828() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule779_id556_at_idx52876() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule780_id557_at_idx52924() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule781_id558_at_idx52972() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule782_id559_at_idx53020() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule783_id560_at_idx53068() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule784_id561_at_idx53116() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule785_id562_at_idx53164() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule786_id563_at_idx53212() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule787_id564_at_idx53260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule788_id565_at_idx53308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule789_id566_at_idx53356() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule790_id567_at_idx53404() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule791_id568_at_idx53452() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule792_id569_at_idx53500() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule793_id570_at_idx53548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule794_id571_at_idx53596() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule795_id572_at_idx53644() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule796_id573_at_idx53692() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule797_id574_at_idx53740() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule798_id575_at_idx53788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule799_id576_at_idx53836() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule800_id577_at_idx53884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule801_id578_at_idx53932() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule802_id579_at_idx53980() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule803_id580_at_idx54028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule804_id581_at_idx54076() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule805_id582_at_idx54124() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule806_id583_at_idx54172() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule807_id584_at_idx54220() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule808_id600_at_idx54268() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule809_id601_at_idx54316() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule810_id602_at_idx54364() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule811_id603_at_idx54412() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule812_id604_at_idx54460() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule813_id620_at_idx54508() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule814_id621_at_idx54556() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule815_id622_at_idx54604() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule816_id623_at_idx54652() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule817_id624_at_idx54700() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule818_id640_at_idx54748() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule819_id641_at_idx54796() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule820_id642_at_idx54844() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule821_id643_at_idx54892() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule822_id644_at_idx54940() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule823_id659_at_idx54988() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule824_id660_at_idx55036() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule825_id679_at_idx55084() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule826_id680_at_idx55132() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule827_id681_at_idx55180() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule828_id682_at_idx55228() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule829_id683_at_idx55276() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule830_id684_at_idx55324() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule831_id690_at_idx55372() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule832_id691_at_idx55420() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule833_id692_at_idx55468() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule834_id693_at_idx55516() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule835_id694_at_idx55564() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule836_id695_at_idx55612() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule837_id696_at_idx55660() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule838_id697_at_idx55708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule839_id698_at_idx55756() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule840_id699_at_idx55804() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule841_id700_at_idx55852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule842_id701_at_idx55900() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule843_id702_at_idx55948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule844_id703_at_idx55996() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule845_id704_at_idx56044() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule846_id705_at_idx56092() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule847_id706_at_idx56140() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule848_id707_at_idx56188() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule849_id708_at_idx56236() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule850_id709_at_idx56284() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule851_id723_at_idx56332() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule852_id724_at_idx56380() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule853_id725_at_idx56428() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule854_id726_at_idx56476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule855_id727_at_idx56524() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule856_id728_at_idx56572() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule857_id734_at_idx56620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule858_id735_at_idx56668() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule859_id736_at_idx56716() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule860_id737_at_idx56764() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule861_id738_at_idx56812() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule862_id739_at_idx56860() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule863_id740_at_idx56908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule864_id1222_at_idx56956() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule865_id1227_at_idx57004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule866_id1228_at_idx57052() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule867_id1229_at_idx57100() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule868_id1230_at_idx57148() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule869_id1231_at_idx57196() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule870_id1232_at_idx57244() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule871_id1238_at_idx57292() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule872_id1438_at_idx57340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule873_id1439_at_idx57388() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule874_id1440_at_idx57436() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule875_id1441_at_idx57484() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule876_id1442_at_idx57532() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule877_id1443_at_idx57580() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule878_id1444_at_idx57628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule879_id1445_at_idx57676() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule880_id1446_at_idx57724() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule881_id1447_at_idx57772() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule882_id1448_at_idx57820() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule883_id1449_at_idx57868() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule884_id1734_at_idx57916() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule885_id1735_at_idx57964() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule886_id1743_at_idx58012() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule889_id2362_at_idx58156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule890_id2381_at_idx58202() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule891_id2387_at_idx58248() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule892_id2463_at_idx58294() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule893_id2464_at_idx58340() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule894_id2465_at_idx58386() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule895_id2466_at_idx58432() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule896_id2467_at_idx58478() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule897_id2468_at_idx58524() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule898_id2469_at_idx58570() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule899_id2470_at_idx58616() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule900_id2471_at_idx58662() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule901_id2472_at_idx58708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule902_id2473_at_idx58754() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule904_id2486_at_idx58846() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule905_id2487_at_idx58892() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule906_id2488_at_idx58938() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule907_id2489_at_idx58984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule908_id2490_at_idx59030() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule909_id2491_at_idx59076() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule911_id2579_at_idx59168() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule912_id2581_at_idx59214() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule913_id2582_at_idx59260() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule914_id2583_at_idx59306() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule915_id2584_at_idx59352() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule916_id2585_at_idx59398() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule917_id2586_at_idx59444() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule918_id2587_at_idx59490() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule919_id2588_at_idx59536() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule920_id2589_at_idx59582() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule921_id1983_at_idx59628() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule922_id1984_at_idx59685() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule923_id2005_at_idx59742() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule924_id2006_at_idx59795() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule925_id3488_at_idx59848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule926_id2019_at_idx59877() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule927_id2020_at_idx59948() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule928_id2367_at_idx60019() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule929_id2368_at_idx60105() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule930_id2446_at_idx60191() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule931_id2447_at_idx60277() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule932_id2448_at_idx60363() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule933_id428_at_idx60449() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule934_id429_at_idx60537() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule935_id430_at_idx60625() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule936_id897_at_idx60713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule937_id898_at_idx60801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule938_id899_at_idx60889() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule939_id900_at_idx60977() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule940_id901_at_idx61065() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule941_id434_at_idx61153() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule942_id435_at_idx61241() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule943_id436_at_idx61329() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule944_id3803_at_idx61417() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule945_id3804_at_idx61505() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule946_id3805_at_idx61593() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule947_id3806_at_idx61681() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule948_id3807_at_idx61769() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule949_id3808_at_idx61857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule950_id3869_at_idx61945() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule951_id3871_at_idx62021() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule952_id3873_at_idx62097() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule953_id3887_at_idx62173() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule954_id3889_at_idx62249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule955_id3891_at_idx62325() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule956_id927_at_idx62401() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule957_id928_at_idx62489() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule958_id929_at_idx62577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule959_id930_at_idx62665() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule960_id931_at_idx62753() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule961_id932_at_idx62841() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule962_id1272_at_idx62929() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule963_id1274_at_idx63005() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule964_id1276_at_idx63081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule965_id1332_at_idx63157() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule966_id1334_at_idx63233() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule967_id1336_at_idx63309() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule968_id1759_at_idx63385() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule969_id1760_at_idx63459() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule970_id1758_at_idx63533() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule971_id1818_at_idx63607() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule972_id1819_at_idx63681() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule973_id1817_at_idx63755() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule974_id1814_at_idx63829() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule975_id1815_at_idx63903() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule976_id1813_at_idx63977() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule977_id933_at_idx64051() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule978_id934_at_idx64139() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule979_id935_at_idx64227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule980_id936_at_idx64315() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule981_id937_at_idx64403() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule982_id938_at_idx64491() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule983_id1314_at_idx64579() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule984_id1316_at_idx64655() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule985_id1318_at_idx64731() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule986_id1362_at_idx64807() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule987_id1364_at_idx64883() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule988_id1366_at_idx64959() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule989_id431_at_idx65035() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule990_id432_at_idx65123() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule991_id433_at_idx65211() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule992_id419_at_idx65299() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule993_id420_at_idx65375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule994_id421_at_idx65451() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule995_id3669_at_idx65527() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule996_id3670_at_idx65606() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule997_id3671_at_idx65685() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule998_id3672_at_idx65764() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule999_id3673_at_idx65843() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1000_id3674_at_idx65922() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1001_id3675_at_idx66001() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1002_id3676_at_idx66080() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1003_id3677_at_idx66159() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1004_id3678_at_idx66238() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1005_id3679_at_idx66317() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1006_id3680_at_idx66396() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1007_id3681_at_idx66475() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1008_id3682_at_idx66554() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1009_id3683_at_idx66633() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1010_id3684_at_idx66712() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1011_id3685_at_idx66791() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1012_id3686_at_idx66870() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1013_id3687_at_idx66949() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1014_id3688_at_idx67028() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1015_id3489_at_idx67107() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1016_id3490_at_idx67174() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1017_id3491_at_idx67241() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1018_id3492_at_idx67308() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1019_id3493_at_idx67375() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1020_id3494_at_idx67442() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1021_id3495_at_idx67509() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1022_id3496_at_idx67576() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1023_id3497_at_idx67643() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1024_id3498_at_idx67710() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1025_id3499_at_idx67777() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1026_id3500_at_idx67844() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1027_id3501_at_idx67911() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1028_id3502_at_idx67978() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1029_id3503_at_idx68045() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1030_id3504_at_idx68112() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1031_id3505_at_idx68179() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1032_id3506_at_idx68246() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1033_id3507_at_idx68313() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1034_id3508_at_idx68380() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1035_id3709_at_idx68447() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1036_id3710_at_idx68533() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1037_id3711_at_idx68619() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1038_id3712_at_idx68705() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1039_id3713_at_idx68791() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1040_id3714_at_idx68877() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1041_id3715_at_idx68963() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1042_id3716_at_idx69049() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1043_id3717_at_idx69135() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1044_id3718_at_idx69221() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1045_id3719_at_idx69307() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1046_id3720_at_idx69393() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1047_id3721_at_idx69479() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1048_id3722_at_idx69565() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1049_id3723_at_idx69651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1050_id3724_at_idx69737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1051_id3725_at_idx69823() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1052_id3726_at_idx69909() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1053_id3727_at_idx69995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1054_id3728_at_idx70081() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1055_id3569_at_idx70167() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1056_id3570_at_idx70234() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1057_id3571_at_idx70301() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1058_id3572_at_idx70368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1059_id3573_at_idx70435() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1060_id3574_at_idx70502() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1061_id3575_at_idx70569() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1062_id3576_at_idx70636() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1063_id3577_at_idx70703() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1064_id3578_at_idx70770() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1065_id3579_at_idx70837() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1066_id3580_at_idx70904() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1067_id3581_at_idx70971() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1068_id3582_at_idx71038() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1069_id3583_at_idx71105() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1070_id3584_at_idx71172() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1071_id3585_at_idx71239() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1072_id3586_at_idx71306() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1073_id3587_at_idx71373() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1074_id3588_at_idx71440() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1075_id3589_at_idx71507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1076_id3590_at_idx71574() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1077_id3591_at_idx71641() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1078_id3592_at_idx71708() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1079_id3593_at_idx71775() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1080_id3594_at_idx71842() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1081_id3595_at_idx71909() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1082_id3596_at_idx71976() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1083_id3597_at_idx72043() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1084_id3598_at_idx72110() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1085_id3599_at_idx72177() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1086_id3600_at_idx72244() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1087_id3601_at_idx72311() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1088_id3602_at_idx72378() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1089_id3603_at_idx72445() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1090_id3604_at_idx72512() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1091_id3605_at_idx72579() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1092_id3606_at_idx72646() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1093_id3607_at_idx72713() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1094_id3608_at_idx72780() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1095_id3509_at_idx72847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1096_id3510_at_idx72914() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1097_id3511_at_idx72981() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1098_id3512_at_idx73048() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1099_id3513_at_idx73115() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1100_id3514_at_idx73182() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1101_id3515_at_idx73249() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1102_id3516_at_idx73316() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1103_id3517_at_idx73383() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1104_id3518_at_idx73450() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1105_id3519_at_idx73517() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1106_id3520_at_idx73584() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1107_id3521_at_idx73651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1108_id3522_at_idx73718() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1109_id3523_at_idx73785() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1110_id3524_at_idx73852() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1111_id3525_at_idx73919() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1112_id3526_at_idx73986() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1113_id3527_at_idx74053() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1114_id3528_at_idx74120() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1115_id3689_at_idx74187() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1116_id3690_at_idx74273() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1117_id3691_at_idx74359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1118_id3692_at_idx74445() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1119_id3693_at_idx74531() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1120_id3694_at_idx74617() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1121_id3695_at_idx74703() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1122_id3696_at_idx74789() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1123_id3697_at_idx74875() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1124_id3698_at_idx74961() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1125_id3699_at_idx75047() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1126_id3700_at_idx75133() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1127_id3701_at_idx75219() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1128_id3702_at_idx75305() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1129_id3703_at_idx75391() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1130_id3704_at_idx75477() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1131_id3705_at_idx75563() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1132_id3706_at_idx75649() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1133_id3707_at_idx75735() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1134_id3708_at_idx75821() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1135_id3609_at_idx75907() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1136_id3610_at_idx75974() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1137_id3611_at_idx76041() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1138_id3612_at_idx76108() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1139_id3613_at_idx76175() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1140_id3614_at_idx76242() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1141_id3615_at_idx76309() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1142_id3616_at_idx76376() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1143_id3617_at_idx76443() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1144_id3618_at_idx76510() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1145_id3619_at_idx76577() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1146_id3620_at_idx76644() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1147_id3621_at_idx76711() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1148_id3622_at_idx76778() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1149_id3623_at_idx76845() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1150_id3624_at_idx76912() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1151_id3625_at_idx76979() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1152_id3626_at_idx77046() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1153_id3627_at_idx77113() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1154_id3628_at_idx77180() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1155_id3629_at_idx77247() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1156_id3630_at_idx77314() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1157_id3631_at_idx77381() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1158_id3632_at_idx77448() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1159_id3633_at_idx77515() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1160_id3634_at_idx77582() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1161_id3635_at_idx77649() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1162_id3636_at_idx77716() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1163_id3637_at_idx77783() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1164_id3638_at_idx77850() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1165_id3639_at_idx77917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1166_id3640_at_idx77984() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1167_id3641_at_idx78051() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1168_id3642_at_idx78118() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1169_id3643_at_idx78185() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1170_id3644_at_idx78252() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1171_id3645_at_idx78319() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1172_id3646_at_idx78386() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1173_id3647_at_idx78453() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1174_id3648_at_idx78520() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1175_id3649_at_idx78587() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1176_id3650_at_idx78654() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1177_id3651_at_idx78721() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1178_id3652_at_idx78788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1179_id3653_at_idx78855() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1180_id3654_at_idx78922() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1181_id3655_at_idx78989() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1182_id3656_at_idx79056() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1183_id3657_at_idx79123() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1184_id3658_at_idx79190() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1185_id3659_at_idx79257() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1186_id3660_at_idx79324() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1187_id3661_at_idx79391() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1188_id3662_at_idx79458() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1189_id3663_at_idx79525() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1190_id3664_at_idx79592() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1191_id3665_at_idx79659() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1192_id3666_at_idx79726() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1193_id3667_at_idx79793() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1194_id3668_at_idx79860() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1195_id3529_at_idx79927() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1196_id3530_at_idx79994() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1197_id3531_at_idx80061() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1198_id3532_at_idx80128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1199_id3533_at_idx80195() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1200_id3534_at_idx80262() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1201_id3535_at_idx80329() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1202_id3536_at_idx80396() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1203_id3537_at_idx80463() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1204_id3538_at_idx80530() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1205_id3539_at_idx80597() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1206_id3540_at_idx80664() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1207_id3541_at_idx80731() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1208_id3542_at_idx80798() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1209_id3543_at_idx80865() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1210_id3544_at_idx80932() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1211_id3545_at_idx80999() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1212_id3546_at_idx81066() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1213_id3547_at_idx81133() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1214_id3548_at_idx81200() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1215_id359_at_idx81267() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1216_id360_at_idx81302() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1217_id361_at_idx81335() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1218_id2957_at_idx81368() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1219_id2958_at_idx81404() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1220_id2959_at_idx81440() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1221_id2960_at_idx81476() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1222_id2961_at_idx81512() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1223_id2962_at_idx81548() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1224_id2963_at_idx81584() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1225_id2964_at_idx81620() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1226_id2965_at_idx81656() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1227_id2966_at_idx81688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1228_id2967_at_idx81720() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1229_id2968_at_idx81752() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1230_id2969_at_idx81784() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1231_id2970_at_idx81816() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1232_id2971_at_idx81848() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1233_id2972_at_idx81880() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1234_id425_at_idx81912() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1235_id426_at_idx81963() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1236_id427_at_idx82014() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1237_id892_at_idx82065() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1238_id893_at_idx82133() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1239_id894_at_idx82201() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1240_id895_at_idx82269() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1241_id896_at_idx82337() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1242_id26_at_idx82405() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1243_id27_at_idx82446() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1244_id751_at_idx82487() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1245_id752_at_idx82530() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1246_id753_at_idx82573() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1247_id754_at_idx82616() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1248_id755_at_idx82659() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1249_id756_at_idx82702() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1250_id757_at_idx82745() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1251_id1176_at_idx82788() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1252_id86_at_idx82831() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1253_id87_at_idx82872() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1254_id1162_at_idx82913() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1255_id1163_at_idx82956() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1256_id1751_at_idx82999() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1257_id1752_at_idx83042() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1258_id1753_at_idx83085() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1259_id1754_at_idx83128() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1260_id1755_at_idx83171() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1261_id1756_at_idx83214() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1262_id52_at_idx83257() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1263_id398_at_idx83298() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1264_id399_at_idx83341() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1265_id400_at_idx83384() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1266_id827_at_idx83427() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1267_id828_at_idx83470() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1268_id829_at_idx83513() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1269_id830_at_idx83556() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1270_id831_at_idx83599() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1271_id401_at_idx83642() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1272_id402_at_idx83685() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1273_id403_at_idx83728() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1274_id847_at_idx83771() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1275_id848_at_idx83814() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1276_id849_at_idx83857() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1277_id850_at_idx83900() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1278_id851_at_idx83943() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1279_id416_at_idx83986() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1280_id417_at_idx84029() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1281_id418_at_idx84072() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1282_id907_at_idx84115() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1283_id908_at_idx84158() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1284_id909_at_idx84201() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1285_id910_at_idx84244() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1286_id911_at_idx84287() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1287_id422_at_idx84330() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1288_id423_at_idx84373() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1289_id424_at_idx84416() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1290_id922_at_idx84459() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1291_id923_at_idx84502() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1292_id924_at_idx84545() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1293_id925_at_idx84588() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1294_id926_at_idx84631() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1295_id54_at_idx84674() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1296_id939_at_idx84715() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1297_id940_at_idx84758() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1298_id941_at_idx84801() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1299_id942_at_idx84844() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1300_id943_at_idx84887() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1301_id944_at_idx84930() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1302_id106_at_idx84973() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1303_id107_at_idx85014() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1304_id1174_at_idx85055() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1305_id1175_at_idx85098() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1306_id1827_at_idx85141() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1307_id1828_at_idx85184() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1308_id1829_at_idx85227() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1309_id1830_at_idx85270() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1310_id1831_at_idx85313() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1311_id1832_at_idx85356() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1312_id50_at_idx85399() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1313_id51_at_idx85440() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1314_id53_at_idx85481() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1315_id1051_at_idx85522() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1316_id1052_at_idx85565() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1317_id1053_at_idx85608() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1318_id1054_at_idx85651() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1319_id1055_at_idx85694() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1320_id1056_at_idx85737() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1321_id1057_at_idx85780() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1322_id1213_at_idx85823() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1323_id1965_at_idx85866() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1324_id1966_at_idx85910() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1325_id48_at_idx85954() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1326_id49_at_idx85995() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1327_id98_at_idx86036() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1328_id99_at_idx86077() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1329_id1170_at_idx86118() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1330_id1171_at_idx86161() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1331_id1791_at_idx86204() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1332_id1792_at_idx86247() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1333_id1793_at_idx86290() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1334_id1794_at_idx86333() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1335_id1795_at_idx86376() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1336_id1796_at_idx86419() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1337_id2925_at_idx86462() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1338_id2928_at_idx86507() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1339_id2931_at_idx86552() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1340_id3134_at_idx86597() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1341_id3135_at_idx86634() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1342_id3136_at_idx86671() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1345_id3139_at_idx86782() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1346_id3140_at_idx86819() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1347_id3141_at_idx86856() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1350_id3144_at_idx86967() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1351_id3145_at_idx87004() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1352_id3146_at_idx87064() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1353_id3147_at_idx87124() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1356_id3150_at_idx87304() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1357_id3151_at_idx87364() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1358_id3152_at_idx87424() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1361_id3155_at_idx87604() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1363_id3157_at_idx87674() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1364_id3161_at_idx87709() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1365_id3162_at_idx87744() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1369_id3166_at_idx87884() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1370_id3167_at_idx87930() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1371_id3168_at_idx87976() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1374_id3171_at_idx88114() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1375_id3172_at_idx88149() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1376_id3173_at_idx88184() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1379_id3176_at_idx88289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1381_id3178_at_idx88377() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1382_id3179_at_idx88423() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1383_id3180_at_idx88469() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1387_id3184_at_idx88653() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1388_id3185_at_idx88688() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1389_id3186_at_idx88723() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1393_id3190_at_idx88863() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1394_id3191_at_idx88907() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1395_id3192_at_idx88953() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1396_id3193_at_idx88999() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1400_id3197_at_idx89183() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1401_id3198_at_idx89218() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1402_id3199_at_idx89253() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1406_id3203_at_idx89393() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1420_id3217_at_idx89967() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1421_id3218_at_idx90013() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1422_id3219_at_idx90059() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1427_id3224_at_idx90289() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1428_id3225_at_idx90324() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1429_id3226_at_idx90359() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1471_id3268_at_idx92050() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1472_id3269_at_idx92096() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1473_id3270_at_idx92142() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1477_id3274_at_idx92326() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1478_id3275_at_idx92372() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1479_id3276_at_idx92423() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1480_id3277_at_idx92506() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1484_id3281_at_idx92806() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1485_id3282_at_idx92889() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1486_id3283_at_idx92935() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1487_id3284_at_idx92981() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1489_id3286_at_idx93073() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1491_id3288_at_idx93165() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1492_id3289_at_idx93216() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1493_id3290_at_idx93251() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1495_id3292_at_idx93321() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1497_id3294_at_idx93391() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1498_id3295_at_idx93435() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1499_id3296_at_idx93481() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1501_id3298_at_idx93573() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1502_id3299_at_idx93619() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1504_id3301_at_idx93711() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1505_id3302_at_idx93794() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1507_id3304_at_idx93864() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1508_id3305_at_idx93899() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1510_id3307_at_idx93969() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1537_id3334_at_idx95137() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1538_id3335_at_idx95183() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1539_id3336_at_idx95229() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1540_id3337_at_idx95275() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1543_id3340_at_idx95413() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1544_id3341_at_idx95496() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1545_id3342_at_idx95531() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1546_id3343_at_idx95566() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1549_id3346_at_idx95671() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1563_id3360_at_idx96293() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1564_id3361_at_idx96339() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1565_id3362_at_idx96385() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1566_id3363_at_idx96431() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1570_id3367_at_idx96615() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1571_id3368_at_idx96698() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1572_id3369_at_idx96733() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1573_id3370_at_idx96768() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1577_id115_at_idx96908() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1578_id116_at_idx96941() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1579_id14_at_idx96974() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1580_id15_at_idx97007() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1581_id371_at_idx97040() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1582_id372_at_idx97075() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1583_id373_at_idx97110() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1584_id595_at_idx97145() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1585_id596_at_idx97180() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1586_id597_at_idx97215() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1587_id598_at_idx97250() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1588_id599_at_idx97285() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1589_id364_at_idx97320() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1590_id365_at_idx97355() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1591_id366_at_idx97390() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1592_id2383_at_idx97425() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1593_id2385_at_idx97458() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1594_id311_at_idx97491() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1595_id312_at_idx97526() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1596_id313_at_idx97561() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1597_id314_at_idx97596() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1598_id315_at_idx97631() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1599_id316_at_idx97666() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1600_id585_at_idx97701() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1601_id586_at_idx97736() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1602_id587_at_idx97771() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1603_id588_at_idx97806() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1604_id589_at_idx97841() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1605_id317_at_idx97876() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1606_id318_at_idx97911() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1607_id319_at_idx97946() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1608_id320_at_idx97981() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1609_id321_at_idx98016() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1610_id322_at_idx98051() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1611_id590_at_idx98086() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1612_id591_at_idx98121() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1613_id592_at_idx98156() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1614_id593_at_idx98191() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1615_id594_at_idx98226() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1616_id362_at_idx98261() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1617_id363_at_idx98296() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1618_id367_at_idx98331() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1619_id2389_at_idx98366() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1620_id2390_at_idx98399() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1621_id2923_at_idx98432() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1622_id2926_at_idx98477() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1623_id2929_at_idx98522() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1624_id335_at_idx98567() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1625_id336_at_idx98602() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1626_id337_at_idx98637() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1627_id338_at_idx98672() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1628_id339_at_idx98707() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1629_id340_at_idx98742() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1630_id685_at_idx98777() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1631_id686_at_idx98812() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1632_id687_at_idx98847() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1633_id688_at_idx98882() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1634_id689_at_idx98917() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1635_id748_at_idx98952() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1636_id749_at_idx98987() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1637_id750_at_idx99022() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1638_id3062_at_idx99057() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1639_id347_at_idx99106() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1640_id348_at_idx99141() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1641_id349_at_idx99176() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1642_id350_at_idx99211() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1643_id351_at_idx99246() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1644_id352_at_idx99281() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1645_id729_at_idx99316() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1646_id730_at_idx99351() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1647_id731_at_idx99386() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1648_id732_at_idx99421() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1649_id733_at_idx99456() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1650_id2924_at_idx99491() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1651_id2927_at_idx99536() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1652_id2930_at_idx99581() {
+  entry:
+    unreachable
+  }
+
+  define void @test_rule1653_id150_at_idx99626() {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            test_return
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_return
+    ; SELECTED: $noreg = PATCHABLE_RET
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule0_id191_at_idx0
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule0_id191_at_idx0
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSHWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_SEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule1_id192_at_idx75
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1_id192_at_idx75
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSHXui:%[0-9]+]]:gpr64 = LDRSHXui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSHXui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s64) = G_SEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule2_id193_at_idx150
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule2_id193_at_idx150
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSBWui:%[0-9]+]]:gpr32 = LDRSBWui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSBWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_SEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule3_id194_at_idx225
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule3_id194_at_idx225
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSBXui:%[0-9]+]]:gpr64 = LDRSBXui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSBXui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s64) = G_SEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule4_id195_at_idx300
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule4_id195_at_idx300
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSWui:%[0-9]+]]:gpr64 = LDRSWui [[COPY]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:gpr(s32) = G_LOAD %2(p0) :: (load 4)
+    %1:gpr(s64) = G_SEXT %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule5_id189_at_idx375
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule5_id189_at_idx375
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHHui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_ZEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule6_id190_at_idx450
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule6_id190_at_idx450
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ZEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule7_id1996_at_idx525
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule7_id1996_at_idx525
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[SMSUBLrrr:%[0-9]+]]:gpr64 = SMSUBLrrr [[COPY]], [[MOVi32imm]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMSUBLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = G_CONSTANT 0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule8_id1997_at_idx661
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule8_id1997_at_idx661
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[UMSUBLrrr:%[0-9]+]]:gpr64 = UMSUBLrrr [[COPY]], [[MOVi32imm]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMSUBLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = G_CONSTANT 0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule9_id182_at_idx797
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule9_id182_at_idx797
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRXui]]
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s64) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule10_id183_at_idx851
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule10_id183_at_idx851
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRWui]]
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s32) = G_LOAD %1(p0) :: (load 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule11_id185_at_idx905
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule11_id185_at_idx905
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY1]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s16) = G_LOAD %1(p0) :: (load 2)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule12_id186_at_idx959
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule12_id186_at_idx959
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s32) = G_LOAD %1(p0) :: (load 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule13_id187_at_idx1013
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule13_id187_at_idx1013
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule14_id188_at_idx1067
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule14_id188_at_idx1067
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule15_id228_at_idx1121
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule15_id228_at_idx1121
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: STRXui [[COPY1]], [[COPY]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(s64) = COPY $x0
+    G_STORE %0(s64), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule16_id229_at_idx1176
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule16_id229_at_idx1176
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: STRWui [[COPY1]], [[COPY]], 0 :: (store 4)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s32) = COPY $w0
+    G_STORE %0(s32), %1(p0) :: (store 4)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule17_id231_at_idx1231
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $d0
+
+    ; SELECTED-LABEL: name: test_rule17_id231_at_idx1231
+    ; SELECTED: liveins: $h0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRHui [[COPY1]], [[COPY2]], 0 :: (store 2)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s16) = COPY $h0
+    G_STORE %0(s16), %1(p0) :: (store 2)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule18_id232_at_idx1285
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $d0
+
+    ; SELECTED-LABEL: name: test_rule18_id232_at_idx1285
+    ; SELECTED: liveins: $s0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRSui [[COPY1]], [[COPY2]], 0 :: (store 4)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s32) = COPY $s0
+    G_STORE %0(s32), %1(p0) :: (store 4)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule19_id233_at_idx1339
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule19_id233_at_idx1339
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(s64) = COPY $d0
+    G_STORE %0(s64), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule20_id2236_at_idx1393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule20_id2236_at_idx1393
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<2 x s32>) = COPY $d0
+    G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule21_id2237_at_idx1449
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule21_id2237_at_idx1449
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<8 x s8>) = COPY $d0
+    G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule22_id2238_at_idx1505
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule22_id2238_at_idx1505
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<4 x s16>) = COPY $d0
+    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule27_id2243_at_idx1781
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule27_id2243_at_idx1781
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = COPY $q0
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule28_id2244_at_idx1837
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule28_id2244_at_idx1837
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s64>) = COPY $q0
+    G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule29_id2245_at_idx1893
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule29_id2245_at_idx1893
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<16 x s8>) = COPY $q0
+    G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule30_id2246_at_idx1949
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule30_id2246_at_idx1949
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s16>) = COPY $q0
+    G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule34_id2250_at_idx2173
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule34_id2250_at_idx2173
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s128) = COPY $q0
+    G_STORE %0(s128), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule35_id1991_at_idx2227
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule35_id1991_at_idx2227
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SMSUBLrrr:%[0-9]+]]:gpr64 = SMSUBLrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMSUBLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = G_CONSTANT 0
+    %2:gpr(s64) = G_SEXT %6(s32)
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule36_id1992_at_idx2352
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule36_id1992_at_idx2352
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UMSUBLrrr:%[0-9]+]]:gpr64 = UMSUBLrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMSUBLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = G_CONSTANT 0
+    %2:gpr(s64) = G_ZEXT %6(s32)
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule37_id3729_at_idx2477
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule37_id3729_at_idx2477
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule38_id3730_at_idx2531
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule38_id3730_at_idx2531
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule39_id1999_at_idx2585
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule39_id1999_at_idx2585
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule40_id2000_at_idx2722
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule40_id2000_at_idx2722
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule41_id24_at_idx2859
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule41_id24_at_idx2859
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule42_id25_at_idx2913
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule42_id25_at_idx2913
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule43_id4111_at_idx2967
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule43_id4111_at_idx2967
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule44_id4112_at_idx3104
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule44_id4112_at_idx3104
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule45_id2002_at_idx3241
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule45_id2002_at_idx3241
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[SMSUBLrrr:%[0-9]+]]:gpr64 = SMSUBLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMSUBLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule46_id2003_at_idx3378
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule46_id2003_at_idx3378
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[UMSUBLrrr:%[0-9]+]]:gpr64 = UMSUBLrrr [[COPY]], [[MOVi32imm]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMSUBLrrr]]
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule47_id3741_at_idx3515
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule47_id3741_at_idx3515
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_SEXT %6(s32)
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule48_id3742_at_idx3641
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule48_id3742_at_idx3641
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_ZEXT %6(s32)
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %0, %4
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule49_id56_at_idx3767
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule49_id56_at_idx3767
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_SEXT %6(s32)
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule50_id58_at_idx3893
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule50_id58_at_idx3893
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_ZEXT %6(s32)
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_ADD %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule51_id2017_at_idx4019
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule51_id2017_at_idx4019
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 1, 63
+    ; SELECTED: $noreg = PATCHABLE_RET [[SBFMXri]]
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule52_id2018_at_idx4090
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule52_id2018_at_idx4090
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 1, 63
+    ; SELECTED: $noreg = PATCHABLE_RET [[SBFMXri]]
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule53_id57_at_idx4161
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule53_id57_at_idx4161
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SMSUBLrrr:%[0-9]+]]:gpr64 = SMSUBLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMSUBLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_SEXT %6(s32)
+    %1:gpr(s64) = G_SEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule54_id59_at_idx4287
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%4' }
+  - { reg: '$w0', virtual-reg: '%5' }
+  - { reg: '$w1', virtual-reg: '%6' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule54_id59_at_idx4287
+    ; SELECTED: liveins: $x0, $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UMSUBLrrr:%[0-9]+]]:gpr64 = UMSUBLrrr [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMSUBLrrr]]
+    %6:gpr(s32) = COPY $w1
+    %5:gpr(s32) = COPY $w0
+    %4:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_ZEXT %6(s32)
+    %1:gpr(s64) = G_ZEXT %5(s32)
+    %0:gpr(s64) = G_MUL %1, %2
+    %3:gpr(s64) = G_SUB %4, %0
+    $noreg = PATCHABLE_RET %3(s64)
+
+...
+---
+name:            test_rule55_id206_at_idx4413
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule55_id206_at_idx4413
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSHWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_SEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule56_id207_at_idx4488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule56_id207_at_idx4488
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSHXui:%[0-9]+]]:gpr64 = LDRSHXui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSHXui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s64) = G_SEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule57_id208_at_idx4563
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule57_id208_at_idx4563
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSBWui:%[0-9]+]]:gpr32 = LDRSBWui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSBWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_SEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule58_id209_at_idx4638
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule58_id209_at_idx4638
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSBXui:%[0-9]+]]:gpr64 = LDRSBXui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSBXui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s64) = G_SEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule59_id210_at_idx4713
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule59_id210_at_idx4713
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRSWui:%[0-9]+]]:gpr64 = LDRSWui [[COPY]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSWui]]
+    %2:gpr(p0) = COPY $x0
+    %0:gpr(s32) = G_LOAD %2(p0) :: (load 4)
+    %1:gpr(s64) = G_SEXT %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule60_id204_at_idx4788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule60_id204_at_idx4788
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHHui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_ZEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule61_id205_at_idx4863
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule61_id205_at_idx4863
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ZEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule62_id2651_at_idx4938
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$q1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule62_id2651_at_idx4938
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[INSvi8lane:%[0-9]+]]:fpr128 = INSvi8lane [[COPY1]], 1, [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[INSvi8lane]]
+    %4:fpr(<16 x s8>) = COPY $q1
+    %3:fpr(<16 x s8>) = COPY $q0
+    %1:fpr(s64) = G_CONSTANT 1
+    %0:fpr(s64) = G_CONSTANT 1
+    %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<16 x s8>), %0(s64), %4(<16 x s8>), %1(s64)
+    $noreg = PATCHABLE_RET %2(<16 x s8>)
+
+...
+---
+name:            test_rule63_id2652_at_idx5048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$q1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule63_id2652_at_idx5048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[INSvi16lane]]
+    %4:fpr(<8 x s16>) = COPY $q1
+    %3:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(s64) = G_CONSTANT 1
+    %0:fpr(s64) = G_CONSTANT 1
+    %2:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<8 x s16>), %0(s64), %4(<8 x s16>), %1(s64)
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule64_id2653_at_idx5158
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$q1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule64_id2653_at_idx5158
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[INSvi32lane]]
+    %4:fpr(<4 x s32>) = COPY $q1
+    %3:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(s64) = G_CONSTANT 1
+    %0:fpr(s64) = G_CONSTANT 1
+    %2:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<4 x s32>), %0(s64), %4(<4 x s32>), %1(s64)
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule65_id2654_at_idx5268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$q1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule65_id2654_at_idx5268
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[INSvi64lane]]
+    %4:fpr(<2 x s64>) = COPY $q1
+    %3:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(s64) = G_CONSTANT 1
+    %0:fpr(s64) = G_CONSTANT 1
+    %2:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<2 x s64>), %0(s64), %4(<2 x s64>), %1(s64)
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule66_id1154_at_idx5378
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule66_id1154_at_idx5378
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMLAHv4i16_:%[0-9]+]]:fpr64 = SQRDMLAHv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLAHv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule67_id1155_at_idx5474
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule67_id1155_at_idx5474
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMLAHv8i16_:%[0-9]+]]:fpr128 = SQRDMLAHv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLAHv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule68_id1156_at_idx5570
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule68_id1156_at_idx5570
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMLAHv2i32_:%[0-9]+]]:fpr64 = SQRDMLAHv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLAHv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule69_id1157_at_idx5666
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule69_id1157_at_idx5666
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMLAHv4i32_:%[0-9]+]]:fpr128 = SQRDMLAHv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLAHv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule70_id1158_at_idx5762
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule70_id1158_at_idx5762
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMLSHv4i16_:%[0-9]+]]:fpr64 = SQRDMLSHv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLSHv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s16>), %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule71_id1159_at_idx5858
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule71_id1159_at_idx5858
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMLSHv8i16_:%[0-9]+]]:fpr128 = SQRDMLSHv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLSHv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<8 x s16>), %0(<8 x s16>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule72_id1160_at_idx5954
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule72_id1160_at_idx5954
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMLSHv2i32_:%[0-9]+]]:fpr64 = SQRDMLSHv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLSHv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<2 x s32>), %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule73_id1161_at_idx6050
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule73_id1161_at_idx6050
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMLSHv4i32_:%[0-9]+]]:fpr128 = SQRDMLSHv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLSHv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule74_id1296_at_idx6146
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule74_id1296_at_idx6146
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMLALv4i16_v4i32_:%[0-9]+]]:fpr128 = SQDMLALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLALv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule75_id1298_at_idx6242
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule75_id1298_at_idx6242
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMLALv2i32_v2i64_:%[0-9]+]]:fpr128 = SQDMLALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLALv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule76_id1300_at_idx6338
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule76_id1300_at_idx6338
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMLSLv4i16_v4i32_:%[0-9]+]]:fpr128 = SQDMLSLv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLSLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s32>), %0(<4 x s32>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule77_id1302_at_idx6434
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule77_id1302_at_idx6434
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMLSLv2i32_v2i64_:%[0-9]+]]:fpr128 = SQDMLSLv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLSLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<2 x s64>), %0(<2 x s64>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule78_id2458_at_idx6530
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule78_id2458_at_idx6530
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQRDMLAHv1i32_:%[0-9]+]]:fpr32 = SQRDMLAHv1i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLAHv1i32_]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(s32), %4(s32)
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule79_id2459_at_idx6626
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule79_id2459_at_idx6626
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQRDMLSHv1i32_:%[0-9]+]]:fpr32 = SQRDMLSHv1i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMLSHv1i32_]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(s32), %4(s32)
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule80_id2460_at_idx6722
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule80_id2460_at_idx6722
+    ; SELECTED: liveins: $d0, $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMLALi32_:%[0-9]+]]:fpr64 = SQDMLALi32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLALi32_]]
+    %4:fpr(s32) = COPY $s1
+    %3:fpr(s32) = COPY $s0
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %3(s32), %4(s32)
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(s64), %0(s64)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule81_id2461_at_idx6816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule81_id2461_at_idx6816
+    ; SELECTED: liveins: $d0, $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMLSLi32_:%[0-9]+]]:fpr64 = SQDMLSLi32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMLSLi32_]]
+    %4:fpr(s32) = COPY $s1
+    %3:fpr(s32) = COPY $s0
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %3(s32), %4(s32)
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(s64), %0(s64)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule82_id3039_at_idx6910
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule82_id3039_at_idx6910
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESErr:%[0-9]+]]:fpr128 = AESErr [[COPY1]], [[COPY]]
+    ; SELECTED: [[AESMCrrTied:%[0-9]+]]:fpr128 = AESMCrrTied [[AESErr]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESMCrrTied]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %2(<16 x s8>), %3(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %0(<16 x s8>)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule83_id3040_at_idx7010
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule83_id3040_at_idx7010
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESDrr:%[0-9]+]]:fpr128 = AESDrr [[COPY1]], [[COPY]]
+    ; SELECTED: [[AESIMCrrTied:%[0-9]+]]:fpr128 = AESIMCrrTied [[AESDrr]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESIMCrrTied]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesd), %2(<16 x s8>), %3(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesimc), %0(<16 x s8>)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule84_id1987_at_idx7110
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule84_id1987_at_idx7110
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MSUBWrrr:%[0-9]+]]:gpr32 = MSUBWrrr [[COPY]], [[COPY1]], $wzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBWrrr]]
+    %4:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %3:gpr(s32) = G_CONSTANT 0
+    %0:gpr(s32) = G_SUB %3, %4
+    %1:gpr(s32) = G_MUL %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule85_id1988_at_idx7195
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule85_id1988_at_idx7195
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[COPY]], [[COPY1]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBXrrr]]
+    %4:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %3:gpr(s64) = G_CONSTANT 0
+    %0:gpr(s64) = G_SUB %3, %4
+    %1:gpr(s64) = G_MUL %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule86_id4109_at_idx7280
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule86_id4109_at_idx7280
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MSUBWrrr:%[0-9]+]]:gpr32 = MSUBWrrr [[COPY]], [[COPY1]], $wzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBWrrr]]
+    %4:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %3:gpr(s32) = G_CONSTANT 0
+    %0:gpr(s32) = G_SUB %3, %4
+    %1:gpr(s32) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule87_id4110_at_idx7365
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule87_id4110_at_idx7365
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[COPY]], [[COPY1]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBXrrr]]
+    %4:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %3:gpr(s64) = G_CONSTANT 0
+    %0:gpr(s64) = G_SUB %3, %4
+    %1:gpr(s64) = G_MUL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule88_id1985_at_idx7450
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule88_id1985_at_idx7450
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MSUBWrrr:%[0-9]+]]:gpr32 = MSUBWrrr [[COPY1]], [[COPY]], $wzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBWrrr]]
+    %4:gpr(s32) = COPY $w1
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s32) = G_CONSTANT 0
+    %0:gpr(s32) = G_MUL %3, %4
+    %1:gpr(s32) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule89_id1986_at_idx7535
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%3' }
+  - { reg: '$x1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule89_id1986_at_idx7535
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MSUBXrrr]]
+    %4:gpr(s64) = COPY $x1
+    %3:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT 0
+    %0:gpr(s64) = G_MUL %3, %4
+    %1:gpr(s64) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule90_id2148_at_idx7620
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule90_id2148_at_idx7620
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHHui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_ANYEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule91_id2149_at_idx7695
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule91_id2149_at_idx7695
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ANYEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule92_id2150_at_idx7770
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule92_id2150_at_idx7770
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ANYEXT %0(s1)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule93_id2170_at_idx7845
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule93_id2170_at_idx7845
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHHui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+    %1:gpr(s32) = G_ANYEXT %0(s16)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule94_id2171_at_idx7920
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule94_id2171_at_idx7920
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ANYEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule95_id2172_at_idx7995
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule95_id2172_at_idx7995
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ANYEXT %0(s1)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule96_id2146_at_idx8070
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule96_id2146_at_idx8070
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ZEXT %0(s1)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule98_id2178_at_idx8220
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule98_id2178_at_idx8220
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ZEXT %0(s8)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule99_id2179_at_idx8295
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule99_id2179_at_idx8295
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRBBui]]
+    %2:gpr(p0) = COPY $x0
+    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+    %1:gpr(s32) = G_ZEXT %0(s1)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule100_id1993_at_idx8370
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule100_id1993_at_idx8370
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %3:gpr(s32) = COPY $w0
+    %1:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_SEXT %3(s32)
+    %2:gpr(s64) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule101_id1994_at_idx8478
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule101_id1994_at_idx8478
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %3:gpr(s32) = COPY $w0
+    %1:gpr(s64) = G_CONSTANT 1
+    %0:gpr(s64) = G_ZEXT %3(s32)
+    %2:gpr(s64) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule102_id3863_at_idx8586
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule102_id3863_at_idx8586
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv8i8_v8i16_:%[0-9]+]]:fpr128 = SABALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv8i8_v8i16_]]
+    %5:fpr(<8 x s8>) = COPY $d1
+    %4:fpr(<8 x s8>) = COPY $d0
+    %3:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule103_id3865_at_idx8698
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule103_id3865_at_idx8698
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv4i16_v4i32_:%[0-9]+]]:fpr128 = SABALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv4i16_v4i32_]]
+    %5:fpr(<4 x s16>) = COPY $d1
+    %4:fpr(<4 x s16>) = COPY $d0
+    %3:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule104_id3867_at_idx8810
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule104_id3867_at_idx8810
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv2i32_v2i64_:%[0-9]+]]:fpr128 = SABALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv2i32_v2i64_]]
+    %5:fpr(<2 x s32>) = COPY $d1
+    %4:fpr(<2 x s32>) = COPY $d0
+    %3:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule105_id3881_at_idx8922
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule105_id3881_at_idx8922
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv8i8_v8i16_:%[0-9]+]]:fpr128 = UABALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv8i8_v8i16_]]
+    %5:fpr(<8 x s8>) = COPY $d1
+    %4:fpr(<8 x s8>) = COPY $d0
+    %3:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule106_id3883_at_idx9034
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule106_id3883_at_idx9034
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv4i16_v4i32_:%[0-9]+]]:fpr128 = UABALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv4i16_v4i32_]]
+    %5:fpr(<4 x s16>) = COPY $d1
+    %4:fpr(<4 x s16>) = COPY $d0
+    %3:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule107_id3885_at_idx9146
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule107_id3885_at_idx9146
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv2i32_v2i64_:%[0-9]+]]:fpr128 = UABALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv2i32_v2i64_]]
+    %5:fpr(<2 x s32>) = COPY $d1
+    %4:fpr(<2 x s32>) = COPY $d0
+    %3:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %0, %3
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule108_id1254_at_idx9258
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule108_id1254_at_idx9258
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv8i8_v8i16_:%[0-9]+]]:fpr128 = SABALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv8i8_v8i16_]]
+    %5:fpr(<8 x s8>) = COPY $d1
+    %4:fpr(<8 x s8>) = COPY $d0
+    %3:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule109_id1256_at_idx9370
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule109_id1256_at_idx9370
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv4i16_v4i32_:%[0-9]+]]:fpr128 = SABALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv4i16_v4i32_]]
+    %5:fpr(<4 x s16>) = COPY $d1
+    %4:fpr(<4 x s16>) = COPY $d0
+    %3:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule110_id1258_at_idx9482
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule110_id1258_at_idx9482
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABALv2i32_v2i64_:%[0-9]+]]:fpr128 = SABALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABALv2i32_v2i64_]]
+    %5:fpr(<2 x s32>) = COPY $d1
+    %4:fpr(<2 x s32>) = COPY $d0
+    %3:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule111_id1320_at_idx9594
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule111_id1320_at_idx9594
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv8i8_v8i16_:%[0-9]+]]:fpr128 = UABALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv8i8_v8i16_]]
+    %5:fpr(<8 x s8>) = COPY $d1
+    %4:fpr(<8 x s8>) = COPY $d0
+    %3:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<8 x s8>), %5(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule112_id1322_at_idx9706
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule112_id1322_at_idx9706
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv4i16_v4i32_:%[0-9]+]]:fpr128 = UABALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv4i16_v4i32_]]
+    %5:fpr(<4 x s16>) = COPY $d1
+    %4:fpr(<4 x s16>) = COPY $d0
+    %3:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<4 x s16>), %5(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule113_id1324_at_idx9818
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%3' }
+  - { reg: '$d0', virtual-reg: '%4' }
+  - { reg: '$d1', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule113_id1324_at_idx9818
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABALv2i32_v2i64_:%[0-9]+]]:fpr128 = UABALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABALv2i32_v2i64_]]
+    %5:fpr(<2 x s32>) = COPY $d1
+    %4:fpr(<2 x s32>) = COPY $d0
+    %3:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<2 x s32>), %5(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %3, %0
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule114_id1989_at_idx9930
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule114_id1989_at_idx9930
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMADDLrrr]]
+    %4:gpr(s32) = COPY $w1
+    %3:gpr(s32) = COPY $w0
+    %1:gpr(s64) = G_SEXT %4(s32)
+    %0:gpr(s64) = G_SEXT %3(s32)
+    %2:gpr(s64) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule115_id1990_at_idx10027
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule115_id1990_at_idx10027
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UMADDLrrr:%[0-9]+]]:gpr64 = UMADDLrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMADDLrrr]]
+    %4:gpr(s32) = COPY $w1
+    %3:gpr(s32) = COPY $w0
+    %1:gpr(s64) = G_ZEXT %4(s32)
+    %0:gpr(s64) = G_ZEXT %3(s32)
+    %2:gpr(s64) = G_MUL %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule116_id197_at_idx10124
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule116_id197_at_idx10124
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRXui]]
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s64) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule117_id198_at_idx10178
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule117_id198_at_idx10178
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRWui]]
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s32) = G_LOAD %1(p0) :: (load 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule118_id200_at_idx10232
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule118_id200_at_idx10232
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY1]], 0 :: (load 2)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRHui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s16) = G_LOAD %1(p0) :: (load 2)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule119_id201_at_idx10286
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule119_id201_at_idx10286
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRSui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s32) = G_LOAD %1(p0) :: (load 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule120_id202_at_idx10340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule120_id202_at_idx10340
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule121_id203_at_idx10394
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule121_id203_at_idx10394
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule122_id236_at_idx10448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule122_id236_at_idx10448
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: STRXui [[COPY1]], [[COPY]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(s64) = COPY $x0
+    G_STORE %0(s64), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule123_id237_at_idx10502
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule123_id237_at_idx10502
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: STRWui [[COPY1]], [[COPY]], 0 :: (store 4)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:gpr(s32) = COPY $w0
+    G_STORE %0(s32), %1(p0) :: (store 4)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule124_id239_at_idx10556
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $d0
+
+    ; SELECTED-LABEL: name: test_rule124_id239_at_idx10556
+    ; SELECTED: liveins: $h0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRHui [[COPY1]], [[COPY2]], 0 :: (store 2)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s16) = COPY $h0
+    G_STORE %0(s16), %1(p0) :: (store 2)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule125_id240_at_idx10610
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $d0
+
+    ; SELECTED-LABEL: name: test_rule125_id240_at_idx10610
+    ; SELECTED: liveins: $s0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRSui [[COPY1]], [[COPY2]], 0 :: (store 4)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s32) = COPY $s0
+    G_STORE %0(s32), %1(p0) :: (store 4)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule126_id241_at_idx10664
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule126_id241_at_idx10664
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(s64) = COPY $d0
+    G_STORE %0(s64), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule127_id242_at_idx10718
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule127_id242_at_idx10718
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(s128) = COPY $q0
+    G_STORE %0(s128), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule128_id2129_at_idx10772
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule128_id2129_at_idx10772
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule129_id2130_at_idx10828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule129_id2130_at_idx10828
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule130_id2131_at_idx10884
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule130_id2131_at_idx10884
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule135_id2136_at_idx11160
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule135_id2136_at_idx11160
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule136_id2137_at_idx11216
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule136_id2137_at_idx11216
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule137_id2138_at_idx11272
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule137_id2138_at_idx11272
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule138_id2139_at_idx11328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule138_id2139_at_idx11328
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule143_id2156_at_idx11606
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule143_id2156_at_idx11606
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule145_id2158_at_idx11718
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule145_id2158_at_idx11718
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule146_id2159_at_idx11774
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule146_id2159_at_idx11774
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule150_id2163_at_idx11994
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule150_id2163_at_idx11994
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule152_id2165_at_idx12106
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule152_id2165_at_idx12106
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule154_id2167_at_idx12218
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule154_id2167_at_idx12218
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule155_id2168_at_idx12274
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule155_id2168_at_idx12274
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule157_id2254_at_idx12386
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule157_id2254_at_idx12386
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<2 x s32>) = COPY $d0
+    G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule158_id2255_at_idx12442
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule158_id2255_at_idx12442
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<8 x s8>) = COPY $d0
+    G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule159_id2256_at_idx12498
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%0' }
+  - { reg: '$d1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule159_id2256_at_idx12498
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d1
+    %0:fpr(<4 x s16>) = COPY $d0
+    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule164_id2261_at_idx12774
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule164_id2261_at_idx12774
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = COPY $q0
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule165_id2262_at_idx12830
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule165_id2262_at_idx12830
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<2 x s64>) = COPY $q0
+    G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule166_id2263_at_idx12886
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule166_id2263_at_idx12886
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<16 x s8>) = COPY $q0
+    G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule167_id2264_at_idx12942
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule167_id2264_at_idx12942
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
+    ; SELECTED: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<8 x s16>) = COPY $q0
+    G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule172_id1606_at_idx13222
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule172_id1606_at_idx13222
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SLIv8i8_shift:%[0-9]+]]:fpr64 = SLIv8i8_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv8i8_shift]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<8 x s8>), %3(<8 x s8>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule173_id1607_at_idx13308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule173_id1607_at_idx13308
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SLIv16i8_shift:%[0-9]+]]:fpr128 = SLIv16i8_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv16i8_shift]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<16 x s8>), %3(<16 x s8>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule174_id1608_at_idx13394
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule174_id1608_at_idx13394
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SLIv4i16_shift:%[0-9]+]]:fpr64 = SLIv4i16_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv4i16_shift]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<4 x s16>), %3(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule175_id1609_at_idx13480
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule175_id1609_at_idx13480
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SLIv8i16_shift:%[0-9]+]]:fpr128 = SLIv8i16_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv8i16_shift]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<8 x s16>), %3(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule176_id1610_at_idx13566
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule176_id1610_at_idx13566
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SLIv2i32_shift:%[0-9]+]]:fpr64 = SLIv2i32_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv2i32_shift]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<2 x s32>), %3(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule177_id1611_at_idx13652
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule177_id1611_at_idx13652
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SLIv4i32_shift:%[0-9]+]]:fpr128 = SLIv4i32_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv4i32_shift]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<4 x s32>), %3(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule178_id1612_at_idx13738
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule178_id1612_at_idx13738
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SLIv2i64_shift:%[0-9]+]]:fpr128 = SLIv2i64_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLIv2i64_shift]]
+    %3:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<2 x s64>), %3(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule179_id1639_at_idx13824
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule179_id1639_at_idx13824
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRIv8i8_shift:%[0-9]+]]:fpr64 = SRIv8i8_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv8i8_shift]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<8 x s8>), %3(<8 x s8>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule180_id1640_at_idx13910
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule180_id1640_at_idx13910
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRIv16i8_shift:%[0-9]+]]:fpr128 = SRIv16i8_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv16i8_shift]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<16 x s8>), %3(<16 x s8>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule181_id1641_at_idx13996
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule181_id1641_at_idx13996
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRIv4i16_shift:%[0-9]+]]:fpr64 = SRIv4i16_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv4i16_shift]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<4 x s16>), %3(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule182_id1642_at_idx14082
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule182_id1642_at_idx14082
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRIv8i16_shift:%[0-9]+]]:fpr128 = SRIv8i16_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv8i16_shift]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<8 x s16>), %3(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule183_id1643_at_idx14168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule183_id1643_at_idx14168
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRIv2i32_shift:%[0-9]+]]:fpr64 = SRIv2i32_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv2i32_shift]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<2 x s32>), %3(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule184_id1644_at_idx14254
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule184_id1644_at_idx14254
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRIv4i32_shift:%[0-9]+]]:fpr128 = SRIv4i32_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv4i32_shift]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<4 x s32>), %3(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule185_id1645_at_idx14340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule185_id1645_at_idx14340
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRIv2i64_shift:%[0-9]+]]:fpr128 = SRIv2i64_shift [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRIv2i64_shift]]
+    %3:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<2 x s64>), %3(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule186_id2915_at_idx14426
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule186_id2915_at_idx14426
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SLId:%[0-9]+]]:fpr64 = SLId [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SLId]]
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(s64), %3(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule187_id2916_at_idx14510
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule187_id2916_at_idx14510
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRId:%[0-9]+]]:fpr64 = SRId [[COPY1]], [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRId]]
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(s64), %3(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule188_id1558_at_idx14594
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule188_id1558_at_idx14594
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHRNs:%[0-9]+]]:fpr32 = SQRSHRNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule189_id1559_at_idx14668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule189_id1559_at_idx14668
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHRUNs:%[0-9]+]]:fpr32 = SQRSHRUNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRUNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule190_id1564_at_idx14742
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule190_id1564_at_idx14742
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHRNs:%[0-9]+]]:fpr32 = SQSHRNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule191_id1565_at_idx14816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule191_id1565_at_idx14816
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHRUNs:%[0-9]+]]:fpr32 = SQSHRUNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRUNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule192_id1570_at_idx14890
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule192_id1570_at_idx14890
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQRSHRNs:%[0-9]+]]:fpr32 = UQRSHRNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHRNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule193_id1573_at_idx14964
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule193_id1573_at_idx14964
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSHRNs:%[0-9]+]]:fpr32 = UQSHRNs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHRNs]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule194_id1593_at_idx15038
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule194_id1593_at_idx15038
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSHRNv8i8_shift:%[0-9]+]]:fpr64 = RSHRNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSHRNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule195_id1594_at_idx15112
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule195_id1594_at_idx15112
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSHRNv4i16_shift:%[0-9]+]]:fpr64 = RSHRNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSHRNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule196_id1595_at_idx15186
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule196_id1595_at_idx15186
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSHRNv2i32_shift:%[0-9]+]]:fpr64 = RSHRNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSHRNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule197_id1613_at_idx15260
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule197_id1613_at_idx15260
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRNv8i8_shift:%[0-9]+]]:fpr64 = SQRSHRNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule198_id1614_at_idx15334
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule198_id1614_at_idx15334
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRNv4i16_shift:%[0-9]+]]:fpr64 = SQRSHRNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule199_id1615_at_idx15408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule199_id1615_at_idx15408
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRNv2i32_shift:%[0-9]+]]:fpr64 = SQRSHRNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule200_id1616_at_idx15482
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule200_id1616_at_idx15482
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRUNv8i8_shift:%[0-9]+]]:fpr64 = SQRSHRUNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRUNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule201_id1617_at_idx15556
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule201_id1617_at_idx15556
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRUNv4i16_shift:%[0-9]+]]:fpr64 = SQRSHRUNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRUNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule202_id1618_at_idx15630
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule202_id1618_at_idx15630
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHRUNv2i32_shift:%[0-9]+]]:fpr64 = SQRSHRUNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHRUNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule203_id1633_at_idx15704
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule203_id1633_at_idx15704
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRNv8i8_shift:%[0-9]+]]:fpr64 = SQSHRNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule204_id1634_at_idx15778
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule204_id1634_at_idx15778
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRNv4i16_shift:%[0-9]+]]:fpr64 = SQSHRNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule205_id1635_at_idx15852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule205_id1635_at_idx15852
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRNv2i32_shift:%[0-9]+]]:fpr64 = SQSHRNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule206_id1636_at_idx15926
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule206_id1636_at_idx15926
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRUNv8i8_shift:%[0-9]+]]:fpr64 = SQSHRUNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRUNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule207_id1637_at_idx16000
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule207_id1637_at_idx16000
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRUNv4i16_shift:%[0-9]+]]:fpr64 = SQSHRUNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRUNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule208_id1638_at_idx16074
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule208_id1638_at_idx16074
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHRUNv2i32_shift:%[0-9]+]]:fpr64 = SQSHRUNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHRUNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule209_id1685_at_idx16148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule209_id1685_at_idx16148
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHRNv8i8_shift:%[0-9]+]]:fpr64 = UQRSHRNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHRNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule210_id1686_at_idx16222
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule210_id1686_at_idx16222
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHRNv4i16_shift:%[0-9]+]]:fpr64 = UQRSHRNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHRNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule211_id1687_at_idx16296
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule211_id1687_at_idx16296
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHRNv2i32_shift:%[0-9]+]]:fpr64 = UQRSHRNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHRNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule212_id1695_at_idx16370
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule212_id1695_at_idx16370
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHRNv8i8_shift:%[0-9]+]]:fpr64 = UQSHRNv8i8_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHRNv8i8_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule213_id1696_at_idx16444
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule213_id1696_at_idx16444
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHRNv4i16_shift:%[0-9]+]]:fpr64 = UQSHRNv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHRNv4i16_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule214_id1697_at_idx16518
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule214_id1697_at_idx16518
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHRNv2i32_shift:%[0-9]+]]:fpr64 = UQSHRNv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHRNv2i32_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule215_id2903_at_idx16592
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule215_id2903_at_idx16592
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZSs:%[0-9]+]]:fpr32 = FCVTZSs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSs]]
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule216_id2904_at_idx16664
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule216_id2904_at_idx16664
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZUs:%[0-9]+]]:fpr32 = FCVTZUs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUs]]
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule217_id2905_at_idx16736
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule217_id2905_at_idx16736
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSd:%[0-9]+]]:fpr64 = FCVTZSd [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSd]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule218_id2906_at_idx16808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule218_id2906_at_idx16808
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUd:%[0-9]+]]:fpr64 = FCVTZUd [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUd]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule221_id2909_at_idx17024
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule221_id2909_at_idx17024
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SCVTFs:%[0-9]+]]:fpr32 = SCVTFs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFs]]
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule222_id2910_at_idx17096
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule222_id2910_at_idx17096
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[UCVTFs:%[0-9]+]]:fpr32 = UCVTFs [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFs]]
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(s32), %0(s32)
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule223_id2911_at_idx17168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule223_id2911_at_idx17168
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SCVTFd:%[0-9]+]]:fpr64 = SCVTFd [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFd]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule224_id2912_at_idx17240
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule224_id2912_at_idx17240
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFd]]
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(s64), %0(s32)
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule227_id1963_at_idx17456
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule227_id1963_at_idx17456
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBSWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule228_id1964_at_idx17510
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule228_id1964_at_idx17510
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBSXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule229_id9_at_idx17564
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule229_id9_at_idx17564
+    ; SELECTED: HINT 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.hint), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule230_id10_at_idx17617
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule230_id10_at_idx17617
+    ; SELECTED: DMB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.dmb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule231_id11_at_idx17670
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule231_id11_at_idx17670
+    ; SELECTED: DSB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.dsb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule232_id12_at_idx17723
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule232_id12_at_idx17723
+    ; SELECTED: ISB 1
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %0:gpr(s32) = G_CONSTANT 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.isb), %0(s32)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule233_id1578_at_idx17776
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule233_id1578_at_idx17776
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSv4i16_shift:%[0-9]+]]:fpr64 = FCVTZSv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv4i16_shift]]
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule234_id1579_at_idx17847
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule234_id1579_at_idx17847
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv8i16_shift:%[0-9]+]]:fpr128 = FCVTZSv8i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv8i16_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule235_id1580_at_idx17918
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule235_id1580_at_idx17918
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSv2i32_shift:%[0-9]+]]:fpr64 = FCVTZSv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv2i32_shift]]
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule236_id1581_at_idx17989
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule236_id1581_at_idx17989
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv4i32_shift:%[0-9]+]]:fpr128 = FCVTZSv4i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv4i32_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule237_id1582_at_idx18060
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule237_id1582_at_idx18060
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv2i64_shift:%[0-9]+]]:fpr128 = FCVTZSv2i64_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv2i64_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule238_id1583_at_idx18131
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule238_id1583_at_idx18131
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUv4i16_shift:%[0-9]+]]:fpr64 = FCVTZUv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv4i16_shift]]
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule239_id1584_at_idx18202
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule239_id1584_at_idx18202
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv8i16_shift:%[0-9]+]]:fpr128 = FCVTZUv8i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv8i16_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule240_id1585_at_idx18273
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule240_id1585_at_idx18273
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUv2i32_shift:%[0-9]+]]:fpr64 = FCVTZUv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv2i32_shift]]
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule241_id1586_at_idx18344
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule241_id1586_at_idx18344
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv4i32_shift:%[0-9]+]]:fpr128 = FCVTZUv4i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv4i32_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule242_id1587_at_idx18415
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule242_id1587_at_idx18415
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv2i64_shift:%[0-9]+]]:fpr128 = FCVTZUv2i64_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv2i64_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule243_id1588_at_idx18486
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule243_id1588_at_idx18486
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SCVTFv4i16_shift:%[0-9]+]]:fpr64 = SCVTFv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv4i16_shift]]
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule244_id1589_at_idx18557
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule244_id1589_at_idx18557
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv8i16_shift:%[0-9]+]]:fpr128 = SCVTFv8i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv8i16_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule245_id1590_at_idx18628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule245_id1590_at_idx18628
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SCVTFv2i32_shift:%[0-9]+]]:fpr64 = SCVTFv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv2i32_shift]]
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule246_id1591_at_idx18699
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule246_id1591_at_idx18699
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv4i32_shift:%[0-9]+]]:fpr128 = SCVTFv4i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv4i32_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule247_id1592_at_idx18770
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule247_id1592_at_idx18770
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv2i64_shift:%[0-9]+]]:fpr128 = SCVTFv2i64_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv2i64_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule248_id1680_at_idx18841
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule248_id1680_at_idx18841
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UCVTFv4i16_shift:%[0-9]+]]:fpr64 = UCVTFv4i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv4i16_shift]]
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule249_id1681_at_idx18912
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule249_id1681_at_idx18912
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv8i16_shift:%[0-9]+]]:fpr128 = UCVTFv8i16_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv8i16_shift]]
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule250_id1682_at_idx18983
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule250_id1682_at_idx18983
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UCVTFv2i32_shift:%[0-9]+]]:fpr64 = UCVTFv2i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv2i32_shift]]
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule251_id1683_at_idx19054
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule251_id1683_at_idx19054
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv4i32_shift:%[0-9]+]]:fpr128 = UCVTFv4i32_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv4i32_shift]]
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule252_id1684_at_idx19125
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule252_id1684_at_idx19125
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv2i64_shift:%[0-9]+]]:fpr128 = UCVTFv2i64_shift [[COPY]], 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv2i64_shift]]
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s32) = G_CONSTANT 1
+    %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<2 x s64>), %0(s32)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule253_id3809_at_idx19196
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule253_id3809_at_idx19196
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv8i8_:%[0-9]+]]:fpr64 = SABAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule254_id3810_at_idx19288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule254_id3810_at_idx19288
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv16i8_:%[0-9]+]]:fpr128 = SABAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule255_id3811_at_idx19380
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule255_id3811_at_idx19380
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv4i16_:%[0-9]+]]:fpr64 = SABAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule256_id3812_at_idx19472
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule256_id3812_at_idx19472
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv8i16_:%[0-9]+]]:fpr128 = SABAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule257_id3813_at_idx19564
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule257_id3813_at_idx19564
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv2i32_:%[0-9]+]]:fpr64 = SABAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule258_id3814_at_idx19656
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule258_id3814_at_idx19656
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv4i32_:%[0-9]+]]:fpr128 = SABAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule259_id3815_at_idx19748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule259_id3815_at_idx19748
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv8i8_:%[0-9]+]]:fpr64 = UABAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule260_id3816_at_idx19840
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule260_id3816_at_idx19840
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv16i8_:%[0-9]+]]:fpr128 = UABAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule261_id3817_at_idx19932
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule261_id3817_at_idx19932
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv4i16_:%[0-9]+]]:fpr64 = UABAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule262_id3818_at_idx20024
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule262_id3818_at_idx20024
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv8i16_:%[0-9]+]]:fpr128 = UABAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule263_id3819_at_idx20116
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule263_id3819_at_idx20116
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv2i32_:%[0-9]+]]:fpr64 = UABAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule264_id3820_at_idx20208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule264_id3820_at_idx20208
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv4i32_:%[0-9]+]]:fpr128 = UABAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule265_id3875_at_idx20300
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule265_id3875_at_idx20300
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv8i8_v8i16_:%[0-9]+]]:fpr128 = SMLALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule266_id3877_at_idx20392
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule266_id3877_at_idx20392
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv4i16_v4i32_:%[0-9]+]]:fpr128 = SMLALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule267_id3879_at_idx20484
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule267_id3879_at_idx20484
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv2i32_v2i64_:%[0-9]+]]:fpr128 = SMLALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule268_id3893_at_idx20576
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule268_id3893_at_idx20576
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv8i8_v8i16_:%[0-9]+]]:fpr128 = UMLALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule269_id3895_at_idx20668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule269_id3895_at_idx20668
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv4i16_v4i32_:%[0-9]+]]:fpr128 = UMLALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule270_id3897_at_idx20760
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule270_id3897_at_idx20760
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv2i32_v2i64_:%[0-9]+]]:fpr128 = UMLALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule271_id3791_at_idx20852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule271_id3791_at_idx20852
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv8i8_v4i16_:%[0-9]+]]:fpr64 = SADALPv8i8_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv8i8_v4i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s8>)
+    %1:fpr(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule272_id3792_at_idx20932
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule272_id3792_at_idx20932
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv16i8_v8i16_:%[0-9]+]]:fpr128 = SADALPv16i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv16i8_v8i16_]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<16 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule273_id3793_at_idx21012
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule273_id3793_at_idx21012
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv4i16_v2i32_:%[0-9]+]]:fpr64 = SADALPv4i16_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv4i16_v2i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s16>)
+    %1:fpr(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule274_id3794_at_idx21092
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule274_id3794_at_idx21092
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv8i16_v4i32_:%[0-9]+]]:fpr128 = SADALPv8i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv8i16_v4i32_]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule275_id3795_at_idx21172
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule275_id3795_at_idx21172
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv2i32_v1i64_:%[0-9]+]]:fpr64 = SADALPv2i32_v1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv2i32_v1i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<2 x s32>)
+    %1:fpr(s64) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule276_id3796_at_idx21252
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule276_id3796_at_idx21252
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv4i32_v2i64_:%[0-9]+]]:fpr128 = SADALPv4i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv4i32_v2i64_]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule277_id3797_at_idx21332
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule277_id3797_at_idx21332
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv8i8_v4i16_:%[0-9]+]]:fpr64 = UADALPv8i8_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv8i8_v4i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s8>)
+    %1:fpr(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule278_id3798_at_idx21412
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule278_id3798_at_idx21412
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv16i8_v8i16_:%[0-9]+]]:fpr128 = UADALPv16i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv16i8_v8i16_]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<16 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule279_id3799_at_idx21492
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule279_id3799_at_idx21492
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv4i16_v2i32_:%[0-9]+]]:fpr64 = UADALPv4i16_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv4i16_v2i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s16>)
+    %1:fpr(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule280_id3800_at_idx21572
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule280_id3800_at_idx21572
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv8i16_v4i32_:%[0-9]+]]:fpr128 = UADALPv8i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv8i16_v4i32_]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule281_id3801_at_idx21652
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule281_id3801_at_idx21652
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv2i32_v1i64_:%[0-9]+]]:fpr64 = UADALPv2i32_v1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv2i32_v1i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<2 x s32>)
+    %1:fpr(s64) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule282_id3802_at_idx21732
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule282_id3802_at_idx21732
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv4i32_v2i64_:%[0-9]+]]:fpr128 = UADALPv4i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv4i32_v2i64_]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule283_id947_at_idx21812
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule283_id947_at_idx21812
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv8i8_:%[0-9]+]]:fpr64 = SABAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule284_id948_at_idx21904
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule284_id948_at_idx21904
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv16i8_:%[0-9]+]]:fpr128 = SABAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule285_id949_at_idx21996
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule285_id949_at_idx21996
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv4i16_:%[0-9]+]]:fpr64 = SABAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule286_id950_at_idx22088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule286_id950_at_idx22088
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv8i16_:%[0-9]+]]:fpr128 = SABAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule287_id951_at_idx22180
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule287_id951_at_idx22180
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABAv2i32_:%[0-9]+]]:fpr64 = SABAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule288_id952_at_idx22272
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule288_id952_at_idx22272
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABAv4i32_:%[0-9]+]]:fpr128 = SABAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule289_id1058_at_idx22364
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule289_id1058_at_idx22364
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv8i8_:%[0-9]+]]:fpr64 = UABAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule290_id1059_at_idx22456
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule290_id1059_at_idx22456
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv16i8_:%[0-9]+]]:fpr128 = UABAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<16 x s8>), %4(<16 x s8>)
+    %1:fpr(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule291_id1060_at_idx22548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule291_id1060_at_idx22548
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv4i16_:%[0-9]+]]:fpr64 = UABAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule292_id1061_at_idx22640
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule292_id1061_at_idx22640
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv8i16_:%[0-9]+]]:fpr128 = UABAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s16>), %4(<8 x s16>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule293_id1062_at_idx22732
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule293_id1062_at_idx22732
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABAv2i32_:%[0-9]+]]:fpr64 = UABAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule294_id1063_at_idx22824
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule294_id1063_at_idx22824
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABAv4i32_:%[0-9]+]]:fpr128 = UABAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s32>), %4(<4 x s32>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule295_id1278_at_idx22916
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule295_id1278_at_idx22916
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv8i8_v8i16_:%[0-9]+]]:fpr128 = SMLALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule296_id1280_at_idx23008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule296_id1280_at_idx23008
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv4i16_v4i32_:%[0-9]+]]:fpr128 = SMLALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule297_id1282_at_idx23100
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule297_id1282_at_idx23100
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLALv2i32_v2i64_:%[0-9]+]]:fpr128 = SMLALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLALv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule298_id1338_at_idx23192
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule298_id1338_at_idx23192
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv8i8_v8i16_:%[0-9]+]]:fpr128 = UMLALv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule299_id1340_at_idx23284
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule299_id1340_at_idx23284
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv4i16_v4i32_:%[0-9]+]]:fpr128 = UMLALv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule300_id1342_at_idx23376
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule300_id1342_at_idx23376
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLALv2i32_v2i64_:%[0-9]+]]:fpr128 = UMLALv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLALv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule301_id673_at_idx23468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule301_id673_at_idx23468
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv8i8_v4i16_:%[0-9]+]]:fpr64 = SADALPv8i8_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv8i8_v4i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s8>)
+    %1:fpr(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule302_id674_at_idx23548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule302_id674_at_idx23548
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv16i8_v8i16_:%[0-9]+]]:fpr128 = SADALPv16i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv16i8_v8i16_]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<16 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule303_id675_at_idx23628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule303_id675_at_idx23628
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv4i16_v2i32_:%[0-9]+]]:fpr64 = SADALPv4i16_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv4i16_v2i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s16>)
+    %1:fpr(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule304_id676_at_idx23708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule304_id676_at_idx23708
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv8i16_v4i32_:%[0-9]+]]:fpr128 = SADALPv8i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv8i16_v4i32_]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule305_id677_at_idx23788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule305_id677_at_idx23788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADALPv2i32_v1i64_:%[0-9]+]]:fpr64 = SADALPv2i32_v1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv2i32_v1i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<2 x s32>)
+    %1:fpr(s64) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule306_id678_at_idx23868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule306_id678_at_idx23868
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADALPv4i32_v2i64_:%[0-9]+]]:fpr128 = SADALPv4i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADALPv4i32_v2i64_]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule307_id717_at_idx23948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule307_id717_at_idx23948
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv8i8_v4i16_:%[0-9]+]]:fpr64 = UADALPv8i8_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv8i8_v4i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s8>)
+    %1:fpr(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule308_id718_at_idx24028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule308_id718_at_idx24028
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv16i8_v8i16_:%[0-9]+]]:fpr128 = UADALPv16i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv16i8_v8i16_]]
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<16 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule309_id719_at_idx24108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule309_id719_at_idx24108
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv4i16_v2i32_:%[0-9]+]]:fpr64 = UADALPv4i16_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv4i16_v2i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s16>)
+    %1:fpr(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule310_id720_at_idx24188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule310_id720_at_idx24188
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv8i16_v4i32_:%[0-9]+]]:fpr128 = UADALPv8i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv8i16_v4i32_]]
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule311_id721_at_idx24268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule311_id721_at_idx24268
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADALPv2i32_v1i64_:%[0-9]+]]:fpr64 = UADALPv2i32_v1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv2i32_v1i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<2 x s32>)
+    %1:fpr(s64) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule312_id722_at_idx24348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule312_id722_at_idx24348
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADALPv4i32_v2i64_:%[0-9]+]]:fpr128 = UADALPv4i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADALPv4i32_v2i64_]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule313_id3751_at_idx24428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule313_id3751_at_idx24428
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[BICWrr:%[0-9]+]]:gpr32 = BICWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule314_id3752_at_idx24510
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule314_id3752_at_idx24510
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[BICXrr:%[0-9]+]]:gpr64 = BICXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_AND %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule315_id90_at_idx24592
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule315_id90_at_idx24592
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[BICWrr:%[0-9]+]]:gpr32 = BICWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule316_id91_at_idx24674
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule316_id91_at_idx24674
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[BICXrr:%[0-9]+]]:gpr64 = BICXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[BICXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_AND %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule317_id3771_at_idx24756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule317_id3771_at_idx24756
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule318_id3772_at_idx24838
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule318_id3772_at_idx24838
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_OR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule319_id102_at_idx24920
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule319_id102_at_idx24920
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule320_id103_at_idx25002
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule320_id103_at_idx25002
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_OR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule321_id1284_at_idx25084
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule321_id1284_at_idx25084
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLSLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMLSLv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLSLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule322_id1286_at_idx25176
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule322_id1286_at_idx25176
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLSLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMLSLv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLSLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule323_id1288_at_idx25268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule323_id1288_at_idx25268
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMLSLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMLSLv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMLSLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule324_id1344_at_idx25360
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule324_id1344_at_idx25360
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLSLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMLSLv8i8_v8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLSLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule325_id1346_at_idx25452
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule325_id1346_at_idx25452
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLSLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMLSLv4i16_v4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLSLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule326_id1348_at_idx25544
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule326_id1348_at_idx25544
+    ; SELECTED: liveins: $q0, $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMLSLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMLSLv2i32_v2i64 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMLSLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule327_id3755_at_idx25636
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule327_id3755_at_idx25636
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule328_id3757_at_idx25718
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule328_id3757_at_idx25718
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[EONXrr:%[0-9]+]]:gpr64 = EONXrr [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule329_id94_at_idx25800
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%3' }
+  - { reg: '$w1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule329_id94_at_idx25800
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONWrr]]
+    %4:gpr(s32) = COPY $w1
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule330_id95_at_idx25882
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%3' }
+  - { reg: '$x1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule330_id95_at_idx25882
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[EONXrr:%[0-9]+]]:gpr64 = EONXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONXrr]]
+    %4:gpr(s64) = COPY $x1
+    %3:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_XOR %0, %2
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule331_id3756_at_idx25964
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%2' }
+  - { reg: '$w1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule331_id3756_at_idx25964
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONWrr]]
+    %3:gpr(s32) = COPY $w1
+    %2:gpr(s32) = COPY $w0
+    %4:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %3, %4
+    %1:gpr(s32) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule332_id3758_at_idx26046
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$x1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule332_id3758_at_idx26046
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[EONXrr:%[0-9]+]]:gpr64 = EONXrr [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EONXrr]]
+    %3:gpr(s64) = COPY $x1
+    %2:gpr(s64) = COPY $x0
+    %4:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %3, %4
+    %1:gpr(s64) = G_XOR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule333_id452_at_idx26128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule333_id452_at_idx26128
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UABDLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDLv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<8 x s8>), %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule334_id454_at_idx26208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule334_id454_at_idx26208
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UABDLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDLv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule335_id456_at_idx26288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule335_id456_at_idx26288
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UABDLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDLv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule336_id1260_at_idx26368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule336_id1260_at_idx26368
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SABDLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDLv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<8 x s8>), %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule337_id1262_at_idx26448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule337_id1262_at_idx26448
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SABDLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDLv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<4 x s16>), %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule338_id1264_at_idx26528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule338_id1264_at_idx26528
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SABDLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDLv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<2 x s32>), %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule339_id2369_at_idx26608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s1', virtual-reg: '%4' }
+  - { reg: '$s2', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule339_id2369_at_idx26608
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
+    %5:fpr(s32) = COPY $s2
+    %4:fpr(s32) = COPY $s1
+    %3:fpr(s32) = COPY $s0
+    %1:fpr(s32) = G_FNEG %5
+    %0:fpr(s32) = G_FNEG %4
+    %2:fpr(s32) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule340_id2370_at_idx26714
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+  - { reg: '$d2', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule340_id2370_at_idx26714
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
+    %5:fpr(s64) = COPY $d2
+    %4:fpr(s64) = COPY $d1
+    %3:fpr(s64) = COPY $d0
+    %1:fpr(s64) = G_FNEG %5
+    %0:fpr(s64) = G_FNEG %4
+    %2:fpr(s64) = G_FMA %0, %3, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule341_id2371_at_idx26820
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%3' }
+  - { reg: '$s1', virtual-reg: '%4' }
+  - { reg: '$s2', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule341_id2371_at_idx26820
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
+    %5:fpr(s32) = COPY $s2
+    %4:fpr(s32) = COPY $s1
+    %3:fpr(s32) = COPY $s0
+    %1:fpr(s32) = G_FNEG %5
+    %0:fpr(s32) = G_FNEG %4
+    %2:fpr(s32) = G_FMA %3, %0, %1
+    $noreg = PATCHABLE_RET %2(s32)
+
+...
+---
+name:            test_rule342_id2372_at_idx26926
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+  - { id: 5, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+  - { reg: '$d2', virtual-reg: '%5' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule342_id2372_at_idx26926
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
+    %5:fpr(s64) = COPY $d2
+    %4:fpr(s64) = COPY $d1
+    %3:fpr(s64) = COPY $d0
+    %1:fpr(s64) = G_FNEG %5
+    %0:fpr(s64) = G_FNEG %4
+    %2:fpr(s64) = G_FMA %3, %0, %1
+    $noreg = PATCHABLE_RET %2(s64)
+
+...
+---
+name:            test_rule343_id1266_at_idx27032
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule343_id1266_at_idx27032
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule344_id1268_at_idx27128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule344_id1268_at_idx27128
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule345_id1270_at_idx27224
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule345_id1270_at_idx27224
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule346_id1326_at_idx27320
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule346_id1326_at_idx27320
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule347_id1328_at_idx27416
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule347_id1328_at_idx27416
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule348_id1330_at_idx27512
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule348_id1330_at_idx27512
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_ADD %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule349_id1308_at_idx27608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule349_id1308_at_idx27608
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule350_id1310_at_idx27704
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule350_id1310_at_idx27704
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule351_id1312_at_idx27800
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule351_id1312_at_idx27800
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule352_id1356_at_idx27896
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule352_id1356_at_idx27896
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]
+    %4:fpr(<8 x s8>) = COPY $d1
+    %3:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %2:fpr(<8 x s16>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<8 x s16>)
+
+...
+---
+name:            test_rule353_id1358_at_idx27992
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule353_id1358_at_idx27992
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]
+    %4:fpr(<4 x s16>) = COPY $d1
+    %3:fpr(<4 x s16>) = COPY $d0
+    %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %2:fpr(<4 x s32>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<4 x s32>)
+
+...
+---
+name:            test_rule354_id1360_at_idx28088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%3' }
+  - { reg: '$d1', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule354_id1360_at_idx28088
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]
+    %4:fpr(<2 x s32>) = COPY $d1
+    %3:fpr(<2 x s32>) = COPY $d0
+    %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %2:fpr(<2 x s64>) = G_SUB %0, %1
+    $noreg = PATCHABLE_RET %2(<2 x s64>)
+
+...
+---
+name:            test_rule355_id1736_at_idx28184
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $s0, $q1
+
+    ; SELECTED-LABEL: name: test_rule355_id1736_at_idx28184
+    ; SELECTED: liveins: $q0, $s0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA1Crrr:%[0-9]+]]:fpr128 = SHA1Crrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1Crrr]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(s32) = COPY $s0
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1c), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule356_id1737_at_idx28256
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $s0, $q1
+
+    ; SELECTED-LABEL: name: test_rule356_id1737_at_idx28256
+    ; SELECTED: liveins: $q0, $s0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA1Prrr:%[0-9]+]]:fpr128 = SHA1Prrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1Prrr]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(s32) = COPY $s0
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1p), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule357_id1738_at_idx28328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $s0, $q1
+
+    ; SELECTED-LABEL: name: test_rule357_id1738_at_idx28328
+    ; SELECTED: liveins: $q0, $s0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA1Mrrr:%[0-9]+]]:fpr128 = SHA1Mrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1Mrrr]]
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(s32) = COPY $s0
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1m), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule358_id1739_at_idx28400
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule358_id1739_at_idx28400
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA1SU0rrr:%[0-9]+]]:fpr128 = SHA1SU0rrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1SU0rrr]]
+    %3:fpr(<4 x s32>) = COPY $q2
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule359_id1740_at_idx28472
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule359_id1740_at_idx28472
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA256Hrrr:%[0-9]+]]:fpr128 = SHA256Hrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256Hrrr]]
+    %3:fpr(<4 x s32>) = COPY $q2
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule360_id1741_at_idx28544
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule360_id1741_at_idx28544
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA256H2rrr:%[0-9]+]]:fpr128 = SHA256H2rrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256H2rrr]]
+    %3:fpr(<4 x s32>) = COPY $q2
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule361_id1742_at_idx28616
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule361_id1742_at_idx28616
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA256SU1rrr:%[0-9]+]]:fpr128 = SHA256SU1rrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256SU1rrr]]
+    %3:fpr(<4 x s32>) = COPY $q2
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule362_id2575_at_idx28688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $q0, $d1
+
+    ; SELECTED-LABEL: name: test_rule362_id2575_at_idx28688
+    ; SELECTED: liveins: $d0, $q0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[TBXv8i8One:%[0-9]+]]:fpr64 = TBXv8i8One [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[TBXv8i8One]]
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbx1), %1(<8 x s8>), %2(<16 x s8>), %3(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule363_id2576_at_idx28758
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule363_id2576_at_idx28758
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[TBXv16i8One:%[0-9]+]]:fpr128 = TBXv16i8One [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[TBXv16i8One]]
+    %3:fpr(<16 x s8>) = COPY $q2
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbx1), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule364_id62_at_idx28828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule364_id62_at_idx28828
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32Brr:%[0-9]+]]:gpr32 = CRC32Brr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32Brr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32b), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule365_id63_at_idx28888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule365_id63_at_idx28888
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32Hrr:%[0-9]+]]:gpr32 = CRC32Hrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32Hrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32h), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule366_id64_at_idx28948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule366_id64_at_idx28948
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32Wrr:%[0-9]+]]:gpr32 = CRC32Wrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32Wrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32w), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule367_id65_at_idx29008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule367_id65_at_idx29008
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32Xrr:%[0-9]+]]:gpr32 = CRC32Xrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32Xrr]]
+    %2:gpr(s64) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32x), %1(s32), %2(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule368_id66_at_idx29068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule368_id66_at_idx29068
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32CBrr:%[0-9]+]]:gpr32 = CRC32CBrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CBrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cb), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule369_id67_at_idx29128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule369_id67_at_idx29128
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32CHrr:%[0-9]+]]:gpr32 = CRC32CHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CHrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32ch), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule370_id68_at_idx29188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule370_id68_at_idx29188
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32CWrr:%[0-9]+]]:gpr32 = CRC32CWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cw), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule371_id69_at_idx29248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule371_id69_at_idx29248
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CRC32CXrr:%[0-9]+]]:gpr32 = CRC32CXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CRC32CXrr]]
+    %2:gpr(s64) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cx), %1(s32), %2(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule372_id710_at_idx29308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule372_id710_at_idx29308
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUQADDv8i8_:%[0-9]+]]:fpr64 = SUQADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule373_id711_at_idx29368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule373_id711_at_idx29368
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUQADDv16i8_:%[0-9]+]]:fpr128 = SUQADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule374_id712_at_idx29428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule374_id712_at_idx29428
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUQADDv4i16_:%[0-9]+]]:fpr64 = SUQADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule375_id713_at_idx29488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule375_id713_at_idx29488
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUQADDv8i16_:%[0-9]+]]:fpr128 = SUQADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule376_id714_at_idx29548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule376_id714_at_idx29548
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUQADDv2i32_:%[0-9]+]]:fpr64 = SUQADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule377_id715_at_idx29608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule377_id715_at_idx29608
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUQADDv4i32_:%[0-9]+]]:fpr128 = SUQADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule378_id716_at_idx29668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule378_id716_at_idx29668
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUQADDv2i64_:%[0-9]+]]:fpr128 = SUQADDv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule379_id741_at_idx29728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule379_id741_at_idx29728
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USQADDv8i8_:%[0-9]+]]:fpr64 = USQADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule380_id742_at_idx29788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule380_id742_at_idx29788
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USQADDv16i8_:%[0-9]+]]:fpr128 = USQADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule381_id743_at_idx29848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule381_id743_at_idx29848
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USQADDv4i16_:%[0-9]+]]:fpr64 = USQADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule382_id744_at_idx29908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule382_id744_at_idx29908
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USQADDv8i16_:%[0-9]+]]:fpr128 = USQADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule383_id745_at_idx29968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule383_id745_at_idx29968
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USQADDv2i32_:%[0-9]+]]:fpr64 = USQADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule384_id746_at_idx30028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule384_id746_at_idx30028
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USQADDv4i32_:%[0-9]+]]:fpr128 = USQADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule385_id747_at_idx30088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule385_id747_at_idx30088
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USQADDv2i64_:%[0-9]+]]:fpr128 = USQADDv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule386_id758_at_idx30148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule386_id758_at_idx30148
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDPv8i8_:%[0-9]+]]:fpr64 = ADDPv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule387_id759_at_idx30208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule387_id759_at_idx30208
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv16i8_:%[0-9]+]]:fpr128 = ADDPv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule388_id760_at_idx30268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule388_id760_at_idx30268
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDPv4i16_:%[0-9]+]]:fpr64 = ADDPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule389_id761_at_idx30328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule389_id761_at_idx30328
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv8i16_:%[0-9]+]]:fpr128 = ADDPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule390_id762_at_idx30388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule390_id762_at_idx30388
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule391_id763_at_idx30448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule391_id763_at_idx30448
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv4i32_:%[0-9]+]]:fpr128 = ADDPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule392_id764_at_idx30508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule392_id764_at_idx30508
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv2i64_:%[0-9]+]]:fpr128 = ADDPv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule393_id807_at_idx30568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule393_id807_at_idx30568
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FABDv4f16_:%[0-9]+]]:fpr64 = FABDv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABDv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule394_id808_at_idx30628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule394_id808_at_idx30628
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FABDv8f16_:%[0-9]+]]:fpr128 = FABDv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABDv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule395_id809_at_idx30688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule395_id809_at_idx30688
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FABDv2f32_:%[0-9]+]]:fpr64 = FABDv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABDv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule396_id810_at_idx30748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule396_id810_at_idx30748
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FABDv4f32_:%[0-9]+]]:fpr128 = FABDv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABDv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule397_id811_at_idx30808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule397_id811_at_idx30808
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FABDv2f64_:%[0-9]+]]:fpr128 = FABDv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABDv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule398_id812_at_idx30868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule398_id812_at_idx30868
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGEv4f16_:%[0-9]+]]:fpr64 = FACGEv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGEv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule399_id813_at_idx30928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule399_id813_at_idx30928
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGEv8f16_:%[0-9]+]]:fpr128 = FACGEv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGEv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule400_id814_at_idx30988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule400_id814_at_idx30988
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGEv2f32_:%[0-9]+]]:fpr64 = FACGEv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGEv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule401_id815_at_idx31048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule401_id815_at_idx31048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGEv4f32_:%[0-9]+]]:fpr128 = FACGEv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGEv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule402_id816_at_idx31108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule402_id816_at_idx31108
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGEv2f64_:%[0-9]+]]:fpr128 = FACGEv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGEv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule403_id817_at_idx31168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule403_id817_at_idx31168
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGTv4f16_:%[0-9]+]]:fpr64 = FACGTv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGTv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule404_id818_at_idx31228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule404_id818_at_idx31228
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGTv8f16_:%[0-9]+]]:fpr128 = FACGTv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGTv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule405_id819_at_idx31288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule405_id819_at_idx31288
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGTv2f32_:%[0-9]+]]:fpr64 = FACGTv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGTv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule406_id820_at_idx31348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule406_id820_at_idx31348
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGTv4f32_:%[0-9]+]]:fpr128 = FACGTv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGTv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule407_id821_at_idx31408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule407_id821_at_idx31408
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FACGTv2f64_:%[0-9]+]]:fpr128 = FACGTv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGTv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule408_id822_at_idx31468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule408_id822_at_idx31468
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDPv4i16_:%[0-9]+]]:fpr64 = ADDPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule409_id823_at_idx31528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule409_id823_at_idx31528
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv8i16_:%[0-9]+]]:fpr128 = ADDPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule410_id824_at_idx31588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule410_id824_at_idx31588
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule411_id825_at_idx31648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule411_id825_at_idx31648
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv4i32_:%[0-9]+]]:fpr128 = ADDPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule412_id826_at_idx31708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule412_id826_at_idx31708
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDPv2i64_:%[0-9]+]]:fpr128 = ADDPv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDPv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule413_id852_at_idx31768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule413_id852_at_idx31768
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXNMPv4f16_:%[0-9]+]]:fpr64 = FMAXNMPv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule414_id853_at_idx31828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule414_id853_at_idx31828
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMPv8f16_:%[0-9]+]]:fpr128 = FMAXNMPv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule415_id854_at_idx31888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule415_id854_at_idx31888
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXNMPv2f32_:%[0-9]+]]:fpr64 = FMAXNMPv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule416_id855_at_idx31948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule416_id855_at_idx31948
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMPv4f32_:%[0-9]+]]:fpr128 = FMAXNMPv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule417_id856_at_idx32008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule417_id856_at_idx32008
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMPv2f64_:%[0-9]+]]:fpr128 = FMAXNMPv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule418_id862_at_idx32068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule418_id862_at_idx32068
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXPv4f16_:%[0-9]+]]:fpr64 = FMAXPv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule419_id863_at_idx32128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule419_id863_at_idx32128
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXPv8f16_:%[0-9]+]]:fpr128 = FMAXPv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule420_id864_at_idx32188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule420_id864_at_idx32188
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXPv2f32_:%[0-9]+]]:fpr64 = FMAXPv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule421_id865_at_idx32248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule421_id865_at_idx32248
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXPv4f32_:%[0-9]+]]:fpr128 = FMAXPv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule422_id866_at_idx32308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule422_id866_at_idx32308
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXPv2f64_:%[0-9]+]]:fpr128 = FMAXPv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule423_id872_at_idx32368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule423_id872_at_idx32368
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINNMPv4f16_:%[0-9]+]]:fpr64 = FMINNMPv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule424_id873_at_idx32428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule424_id873_at_idx32428
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMPv8f16_:%[0-9]+]]:fpr128 = FMINNMPv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule425_id874_at_idx32488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule425_id874_at_idx32488
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINNMPv2f32_:%[0-9]+]]:fpr64 = FMINNMPv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule426_id875_at_idx32548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule426_id875_at_idx32548
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMPv4f32_:%[0-9]+]]:fpr128 = FMINNMPv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule427_id876_at_idx32608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule427_id876_at_idx32608
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMPv2f64_:%[0-9]+]]:fpr128 = FMINNMPv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule428_id882_at_idx32668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule428_id882_at_idx32668
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINPv4f16_:%[0-9]+]]:fpr64 = FMINPv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule429_id883_at_idx32728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule429_id883_at_idx32728
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINPv8f16_:%[0-9]+]]:fpr128 = FMINPv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule430_id884_at_idx32788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule430_id884_at_idx32788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINPv2f32_:%[0-9]+]]:fpr64 = FMINPv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule431_id885_at_idx32848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule431_id885_at_idx32848
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINPv4f32_:%[0-9]+]]:fpr128 = FMINPv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule432_id886_at_idx32908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule432_id886_at_idx32908
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINPv2f64_:%[0-9]+]]:fpr128 = FMINPv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule433_id902_at_idx32968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule433_id902_at_idx32968
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULXv4f16_:%[0-9]+]]:fpr64 = FMULXv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULXv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule434_id903_at_idx33028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule434_id903_at_idx33028
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULXv8f16_:%[0-9]+]]:fpr128 = FMULXv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULXv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule435_id904_at_idx33088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule435_id904_at_idx33088
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULXv2f32_:%[0-9]+]]:fpr64 = FMULXv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULXv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule436_id905_at_idx33148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule436_id905_at_idx33148
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULXv4f32_:%[0-9]+]]:fpr128 = FMULXv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULXv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule437_id906_at_idx33208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule437_id906_at_idx33208
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULXv2f64_:%[0-9]+]]:fpr128 = FMULXv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULXv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule438_id912_at_idx33268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule438_id912_at_idx33268
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPSv4f16_:%[0-9]+]]:fpr64 = FRECPSv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPSv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule439_id913_at_idx33328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule439_id913_at_idx33328
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPSv8f16_:%[0-9]+]]:fpr128 = FRECPSv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPSv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule440_id914_at_idx33388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule440_id914_at_idx33388
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPSv2f32_:%[0-9]+]]:fpr64 = FRECPSv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPSv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule441_id915_at_idx33448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule441_id915_at_idx33448
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPSv4f32_:%[0-9]+]]:fpr128 = FRECPSv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPSv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule442_id916_at_idx33508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule442_id916_at_idx33508
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPSv2f64_:%[0-9]+]]:fpr128 = FRECPSv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPSv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule443_id917_at_idx33568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule443_id917_at_idx33568
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTSv4f16_:%[0-9]+]]:fpr64 = FRSQRTSv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTSv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule444_id918_at_idx33628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule444_id918_at_idx33628
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTSv8f16_:%[0-9]+]]:fpr128 = FRSQRTSv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTSv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule445_id919_at_idx33688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule445_id919_at_idx33688
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTSv2f32_:%[0-9]+]]:fpr64 = FRSQRTSv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTSv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule446_id920_at_idx33748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule446_id920_at_idx33748
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTSv4f32_:%[0-9]+]]:fpr128 = FRSQRTSv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTSv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule447_id921_at_idx33808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule447_id921_at_idx33808
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTSv2f64_:%[0-9]+]]:fpr128 = FRSQRTSv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTSv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule448_id945_at_idx33868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule448_id945_at_idx33868
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[PMULv8i8_:%[0-9]+]]:fpr64 = PMULv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PMULv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmul), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule449_id946_at_idx33928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule449_id946_at_idx33928
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[PMULv16i8_:%[0-9]+]]:fpr128 = PMULv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PMULv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmul), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule450_id953_at_idx33988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule450_id953_at_idx33988
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDv8i8_:%[0-9]+]]:fpr64 = SABDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule451_id954_at_idx34048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule451_id954_at_idx34048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABDv16i8_:%[0-9]+]]:fpr128 = SABDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule452_id955_at_idx34108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule452_id955_at_idx34108
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDv4i16_:%[0-9]+]]:fpr64 = SABDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule453_id956_at_idx34168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule453_id956_at_idx34168
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABDv8i16_:%[0-9]+]]:fpr128 = SABDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule454_id957_at_idx34228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule454_id957_at_idx34228
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SABDv2i32_:%[0-9]+]]:fpr64 = SABDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule455_id958_at_idx34288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule455_id958_at_idx34288
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SABDv4i32_:%[0-9]+]]:fpr128 = SABDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SABDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule456_id959_at_idx34348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule456_id959_at_idx34348
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHADDv8i8_:%[0-9]+]]:fpr64 = SHADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule457_id960_at_idx34408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule457_id960_at_idx34408
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHADDv16i8_:%[0-9]+]]:fpr128 = SHADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule458_id961_at_idx34468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule458_id961_at_idx34468
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHADDv4i16_:%[0-9]+]]:fpr64 = SHADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule459_id962_at_idx34528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule459_id962_at_idx34528
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHADDv8i16_:%[0-9]+]]:fpr128 = SHADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule460_id963_at_idx34588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule460_id963_at_idx34588
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHADDv2i32_:%[0-9]+]]:fpr64 = SHADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule461_id964_at_idx34648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule461_id964_at_idx34648
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHADDv4i32_:%[0-9]+]]:fpr128 = SHADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule462_id965_at_idx34708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule462_id965_at_idx34708
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHSUBv8i8_:%[0-9]+]]:fpr64 = SHSUBv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule463_id966_at_idx34768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule463_id966_at_idx34768
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHSUBv16i8_:%[0-9]+]]:fpr128 = SHSUBv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule464_id967_at_idx34828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule464_id967_at_idx34828
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHSUBv4i16_:%[0-9]+]]:fpr64 = SHSUBv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule465_id968_at_idx34888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule465_id968_at_idx34888
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHSUBv8i16_:%[0-9]+]]:fpr128 = SHSUBv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule466_id969_at_idx34948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule466_id969_at_idx34948
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SHSUBv2i32_:%[0-9]+]]:fpr64 = SHSUBv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule467_id970_at_idx35008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule467_id970_at_idx35008
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHSUBv4i32_:%[0-9]+]]:fpr128 = SHSUBv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHSUBv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule468_id971_at_idx35068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule468_id971_at_idx35068
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMAXPv8i8_:%[0-9]+]]:fpr64 = SMAXPv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule469_id972_at_idx35128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule469_id972_at_idx35128
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMAXPv16i8_:%[0-9]+]]:fpr128 = SMAXPv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule470_id973_at_idx35188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule470_id973_at_idx35188
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMAXPv4i16_:%[0-9]+]]:fpr64 = SMAXPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule471_id974_at_idx35248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule471_id974_at_idx35248
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMAXPv8i16_:%[0-9]+]]:fpr128 = SMAXPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule472_id975_at_idx35308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule472_id975_at_idx35308
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMAXPv2i32_:%[0-9]+]]:fpr64 = SMAXPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule473_id976_at_idx35368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule473_id976_at_idx35368
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMAXPv4i32_:%[0-9]+]]:fpr128 = SMAXPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMAXPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule474_id983_at_idx35428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule474_id983_at_idx35428
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMINPv8i8_:%[0-9]+]]:fpr64 = SMINPv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule475_id984_at_idx35488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule475_id984_at_idx35488
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMINPv16i8_:%[0-9]+]]:fpr128 = SMINPv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule476_id985_at_idx35548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule476_id985_at_idx35548
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMINPv4i16_:%[0-9]+]]:fpr64 = SMINPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule477_id986_at_idx35608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule477_id986_at_idx35608
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMINPv8i16_:%[0-9]+]]:fpr128 = SMINPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule478_id987_at_idx35668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule478_id987_at_idx35668
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMINPv2i32_:%[0-9]+]]:fpr64 = SMINPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule479_id988_at_idx35728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule479_id988_at_idx35728
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SMINPv4i32_:%[0-9]+]]:fpr128 = SMINPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMINPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule480_id995_at_idx35788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule480_id995_at_idx35788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQADDv8i8_:%[0-9]+]]:fpr64 = SQADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule481_id996_at_idx35848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule481_id996_at_idx35848
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQADDv16i8_:%[0-9]+]]:fpr128 = SQADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule482_id997_at_idx35908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule482_id997_at_idx35908
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQADDv4i16_:%[0-9]+]]:fpr64 = SQADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule483_id998_at_idx35968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule483_id998_at_idx35968
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQADDv8i16_:%[0-9]+]]:fpr128 = SQADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule484_id999_at_idx36028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule484_id999_at_idx36028
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQADDv2i32_:%[0-9]+]]:fpr64 = SQADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule485_id1000_at_idx36088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule485_id1000_at_idx36088
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQADDv4i32_:%[0-9]+]]:fpr128 = SQADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule486_id1001_at_idx36148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule486_id1001_at_idx36148
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQADDv2i64_:%[0-9]+]]:fpr128 = SQADDv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule487_id1002_at_idx36208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule487_id1002_at_idx36208
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMULHv4i16_:%[0-9]+]]:fpr64 = SQDMULHv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULHv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule488_id1003_at_idx36268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule488_id1003_at_idx36268
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMULHv8i16_:%[0-9]+]]:fpr128 = SQDMULHv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULHv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule489_id1004_at_idx36328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule489_id1004_at_idx36328
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMULHv2i32_:%[0-9]+]]:fpr64 = SQDMULHv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULHv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule490_id1005_at_idx36388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule490_id1005_at_idx36388
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQDMULHv4i32_:%[0-9]+]]:fpr128 = SQDMULHv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULHv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule491_id1006_at_idx36448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule491_id1006_at_idx36448
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMULHv4i16_:%[0-9]+]]:fpr64 = SQRDMULHv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMULHv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule492_id1007_at_idx36508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule492_id1007_at_idx36508
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMULHv8i16_:%[0-9]+]]:fpr128 = SQRDMULHv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMULHv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule493_id1008_at_idx36568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule493_id1008_at_idx36568
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRDMULHv2i32_:%[0-9]+]]:fpr64 = SQRDMULHv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMULHv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule494_id1009_at_idx36628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule494_id1009_at_idx36628
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRDMULHv4i32_:%[0-9]+]]:fpr128 = SQRDMULHv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMULHv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule495_id1010_at_idx36688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule495_id1010_at_idx36688
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHLv8i8_:%[0-9]+]]:fpr64 = SQRSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule496_id1011_at_idx36748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule496_id1011_at_idx36748
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHLv16i8_:%[0-9]+]]:fpr128 = SQRSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule497_id1012_at_idx36808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule497_id1012_at_idx36808
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHLv4i16_:%[0-9]+]]:fpr64 = SQRSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule498_id1013_at_idx36868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule498_id1013_at_idx36868
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHLv8i16_:%[0-9]+]]:fpr128 = SQRSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule499_id1014_at_idx36928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule499_id1014_at_idx36928
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHLv2i32_:%[0-9]+]]:fpr64 = SQRSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule500_id1015_at_idx36988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule500_id1015_at_idx36988
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHLv4i32_:%[0-9]+]]:fpr128 = SQRSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule501_id1016_at_idx37048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule501_id1016_at_idx37048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQRSHLv2i64_:%[0-9]+]]:fpr128 = SQRSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule502_id1017_at_idx37108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule502_id1017_at_idx37108
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHLv8i8_:%[0-9]+]]:fpr64 = SQSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule503_id1018_at_idx37168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule503_id1018_at_idx37168
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHLv16i8_:%[0-9]+]]:fpr128 = SQSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule504_id1019_at_idx37228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule504_id1019_at_idx37228
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHLv4i16_:%[0-9]+]]:fpr64 = SQSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule505_id1020_at_idx37288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule505_id1020_at_idx37288
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHLv8i16_:%[0-9]+]]:fpr128 = SQSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule506_id1021_at_idx37348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule506_id1021_at_idx37348
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHLv2i32_:%[0-9]+]]:fpr64 = SQSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule507_id1022_at_idx37408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule507_id1022_at_idx37408
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHLv4i32_:%[0-9]+]]:fpr128 = SQSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule508_id1023_at_idx37468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule508_id1023_at_idx37468
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSHLv2i64_:%[0-9]+]]:fpr128 = SQSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule509_id1024_at_idx37528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule509_id1024_at_idx37528
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSUBv8i8_:%[0-9]+]]:fpr64 = SQSUBv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule510_id1025_at_idx37588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule510_id1025_at_idx37588
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSUBv16i8_:%[0-9]+]]:fpr128 = SQSUBv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule511_id1026_at_idx37648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule511_id1026_at_idx37648
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSUBv4i16_:%[0-9]+]]:fpr64 = SQSUBv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule512_id1027_at_idx37708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule512_id1027_at_idx37708
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSUBv8i16_:%[0-9]+]]:fpr128 = SQSUBv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule513_id1028_at_idx37768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule513_id1028_at_idx37768
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSUBv2i32_:%[0-9]+]]:fpr64 = SQSUBv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule514_id1029_at_idx37828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule514_id1029_at_idx37828
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSUBv4i32_:%[0-9]+]]:fpr128 = SQSUBv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule515_id1030_at_idx37888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule515_id1030_at_idx37888
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQSUBv2i64_:%[0-9]+]]:fpr128 = SQSUBv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule516_id1031_at_idx37948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule516_id1031_at_idx37948
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRHADDv8i8_:%[0-9]+]]:fpr64 = SRHADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule517_id1032_at_idx38008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule517_id1032_at_idx38008
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRHADDv16i8_:%[0-9]+]]:fpr128 = SRHADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule518_id1033_at_idx38068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule518_id1033_at_idx38068
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRHADDv4i16_:%[0-9]+]]:fpr64 = SRHADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule519_id1034_at_idx38128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule519_id1034_at_idx38128
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRHADDv8i16_:%[0-9]+]]:fpr128 = SRHADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule520_id1035_at_idx38188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule520_id1035_at_idx38188
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRHADDv2i32_:%[0-9]+]]:fpr64 = SRHADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule521_id1036_at_idx38248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule521_id1036_at_idx38248
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRHADDv4i32_:%[0-9]+]]:fpr128 = SRHADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRHADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule522_id1037_at_idx38308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule522_id1037_at_idx38308
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRSHLv8i8_:%[0-9]+]]:fpr64 = SRSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule523_id1038_at_idx38368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule523_id1038_at_idx38368
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRSHLv16i8_:%[0-9]+]]:fpr128 = SRSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule524_id1039_at_idx38428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule524_id1039_at_idx38428
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRSHLv4i16_:%[0-9]+]]:fpr64 = SRSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule525_id1040_at_idx38488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule525_id1040_at_idx38488
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRSHLv8i16_:%[0-9]+]]:fpr128 = SRSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule526_id1041_at_idx38548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule526_id1041_at_idx38548
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRSHLv2i32_:%[0-9]+]]:fpr64 = SRSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule527_id1042_at_idx38608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule527_id1042_at_idx38608
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRSHLv4i32_:%[0-9]+]]:fpr128 = SRSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule528_id1043_at_idx38668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule528_id1043_at_idx38668
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SRSHLv2i64_:%[0-9]+]]:fpr128 = SRSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule529_id1044_at_idx38728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule529_id1044_at_idx38728
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLv8i8_:%[0-9]+]]:fpr64 = SSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule530_id1045_at_idx38788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule530_id1045_at_idx38788
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSHLv16i8_:%[0-9]+]]:fpr128 = SSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule531_id1046_at_idx38848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule531_id1046_at_idx38848
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule532_id1047_at_idx38908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule532_id1047_at_idx38908
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSHLv8i16_:%[0-9]+]]:fpr128 = SSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule533_id1048_at_idx38968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule533_id1048_at_idx38968
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule534_id1049_at_idx39028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule534_id1049_at_idx39028
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule535_id1050_at_idx39088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule535_id1050_at_idx39088
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule536_id1064_at_idx39148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule536_id1064_at_idx39148
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDv8i8_:%[0-9]+]]:fpr64 = UABDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule537_id1065_at_idx39208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule537_id1065_at_idx39208
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABDv16i8_:%[0-9]+]]:fpr128 = UABDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule538_id1066_at_idx39268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule538_id1066_at_idx39268
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDv4i16_:%[0-9]+]]:fpr64 = UABDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule539_id1067_at_idx39328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule539_id1067_at_idx39328
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABDv8i16_:%[0-9]+]]:fpr128 = UABDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule540_id1068_at_idx39388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule540_id1068_at_idx39388
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UABDv2i32_:%[0-9]+]]:fpr64 = UABDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule541_id1069_at_idx39448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule541_id1069_at_idx39448
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UABDv4i32_:%[0-9]+]]:fpr128 = UABDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UABDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule542_id1070_at_idx39508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule542_id1070_at_idx39508
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHADDv8i8_:%[0-9]+]]:fpr64 = UHADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule543_id1071_at_idx39568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule543_id1071_at_idx39568
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHADDv16i8_:%[0-9]+]]:fpr128 = UHADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule544_id1072_at_idx39628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule544_id1072_at_idx39628
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHADDv4i16_:%[0-9]+]]:fpr64 = UHADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule545_id1073_at_idx39688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule545_id1073_at_idx39688
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHADDv8i16_:%[0-9]+]]:fpr128 = UHADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule546_id1074_at_idx39748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule546_id1074_at_idx39748
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHADDv2i32_:%[0-9]+]]:fpr64 = UHADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule547_id1075_at_idx39808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule547_id1075_at_idx39808
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHADDv4i32_:%[0-9]+]]:fpr128 = UHADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule548_id1076_at_idx39868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule548_id1076_at_idx39868
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHSUBv8i8_:%[0-9]+]]:fpr64 = UHSUBv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule549_id1077_at_idx39928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule549_id1077_at_idx39928
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHSUBv16i8_:%[0-9]+]]:fpr128 = UHSUBv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule550_id1078_at_idx39988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule550_id1078_at_idx39988
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHSUBv4i16_:%[0-9]+]]:fpr64 = UHSUBv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule551_id1079_at_idx40048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule551_id1079_at_idx40048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHSUBv8i16_:%[0-9]+]]:fpr128 = UHSUBv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule552_id1080_at_idx40108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule552_id1080_at_idx40108
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UHSUBv2i32_:%[0-9]+]]:fpr64 = UHSUBv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule553_id1081_at_idx40168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule553_id1081_at_idx40168
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UHSUBv4i32_:%[0-9]+]]:fpr128 = UHSUBv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UHSUBv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule554_id1082_at_idx40228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule554_id1082_at_idx40228
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMAXPv8i8_:%[0-9]+]]:fpr64 = UMAXPv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule555_id1083_at_idx40288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule555_id1083_at_idx40288
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMAXPv16i8_:%[0-9]+]]:fpr128 = UMAXPv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule556_id1084_at_idx40348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule556_id1084_at_idx40348
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMAXPv4i16_:%[0-9]+]]:fpr64 = UMAXPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule557_id1085_at_idx40408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule557_id1085_at_idx40408
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMAXPv8i16_:%[0-9]+]]:fpr128 = UMAXPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule558_id1086_at_idx40468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule558_id1086_at_idx40468
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMAXPv2i32_:%[0-9]+]]:fpr64 = UMAXPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule559_id1087_at_idx40528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule559_id1087_at_idx40528
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMAXPv4i32_:%[0-9]+]]:fpr128 = UMAXPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMAXPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule560_id1094_at_idx40588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule560_id1094_at_idx40588
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMINPv8i8_:%[0-9]+]]:fpr64 = UMINPv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule561_id1095_at_idx40648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule561_id1095_at_idx40648
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMINPv16i8_:%[0-9]+]]:fpr128 = UMINPv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule562_id1096_at_idx40708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule562_id1096_at_idx40708
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMINPv4i16_:%[0-9]+]]:fpr64 = UMINPv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule563_id1097_at_idx40768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule563_id1097_at_idx40768
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMINPv8i16_:%[0-9]+]]:fpr128 = UMINPv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule564_id1098_at_idx40828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule564_id1098_at_idx40828
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMINPv2i32_:%[0-9]+]]:fpr64 = UMINPv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule565_id1099_at_idx40888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule565_id1099_at_idx40888
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UMINPv4i32_:%[0-9]+]]:fpr128 = UMINPv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMINPv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule566_id1106_at_idx40948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule566_id1106_at_idx40948
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQADDv8i8_:%[0-9]+]]:fpr64 = UQADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule567_id1107_at_idx41008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule567_id1107_at_idx41008
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQADDv16i8_:%[0-9]+]]:fpr128 = UQADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule568_id1108_at_idx41068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule568_id1108_at_idx41068
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQADDv4i16_:%[0-9]+]]:fpr64 = UQADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule569_id1109_at_idx41128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule569_id1109_at_idx41128
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQADDv8i16_:%[0-9]+]]:fpr128 = UQADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule570_id1110_at_idx41188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule570_id1110_at_idx41188
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQADDv2i32_:%[0-9]+]]:fpr64 = UQADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule571_id1111_at_idx41248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule571_id1111_at_idx41248
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQADDv4i32_:%[0-9]+]]:fpr128 = UQADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule572_id1112_at_idx41308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule572_id1112_at_idx41308
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQADDv2i64_:%[0-9]+]]:fpr128 = UQADDv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule573_id1113_at_idx41368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule573_id1113_at_idx41368
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQRSHLv8i8_:%[0-9]+]]:fpr64 = UQRSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule574_id1114_at_idx41428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule574_id1114_at_idx41428
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHLv16i8_:%[0-9]+]]:fpr128 = UQRSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule575_id1115_at_idx41488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule575_id1115_at_idx41488
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQRSHLv4i16_:%[0-9]+]]:fpr64 = UQRSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule576_id1116_at_idx41548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule576_id1116_at_idx41548
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHLv8i16_:%[0-9]+]]:fpr128 = UQRSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule577_id1117_at_idx41608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule577_id1117_at_idx41608
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQRSHLv2i32_:%[0-9]+]]:fpr64 = UQRSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule578_id1118_at_idx41668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule578_id1118_at_idx41668
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHLv4i32_:%[0-9]+]]:fpr128 = UQRSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule579_id1119_at_idx41728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule579_id1119_at_idx41728
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQRSHLv2i64_:%[0-9]+]]:fpr128 = UQRSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule580_id1120_at_idx41788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule580_id1120_at_idx41788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSHLv8i8_:%[0-9]+]]:fpr64 = UQSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule581_id1121_at_idx41848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule581_id1121_at_idx41848
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHLv16i8_:%[0-9]+]]:fpr128 = UQSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule582_id1122_at_idx41908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule582_id1122_at_idx41908
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSHLv4i16_:%[0-9]+]]:fpr64 = UQSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule583_id1123_at_idx41968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule583_id1123_at_idx41968
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHLv8i16_:%[0-9]+]]:fpr128 = UQSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule584_id1124_at_idx42028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule584_id1124_at_idx42028
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSHLv2i32_:%[0-9]+]]:fpr64 = UQSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule585_id1125_at_idx42088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule585_id1125_at_idx42088
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHLv4i32_:%[0-9]+]]:fpr128 = UQSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule586_id1126_at_idx42148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule586_id1126_at_idx42148
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSHLv2i64_:%[0-9]+]]:fpr128 = UQSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule587_id1127_at_idx42208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule587_id1127_at_idx42208
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSUBv8i8_:%[0-9]+]]:fpr64 = UQSUBv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule588_id1128_at_idx42268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule588_id1128_at_idx42268
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSUBv16i8_:%[0-9]+]]:fpr128 = UQSUBv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule589_id1129_at_idx42328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule589_id1129_at_idx42328
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSUBv4i16_:%[0-9]+]]:fpr64 = UQSUBv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule590_id1130_at_idx42388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule590_id1130_at_idx42388
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSUBv8i16_:%[0-9]+]]:fpr128 = UQSUBv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule591_id1131_at_idx42448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule591_id1131_at_idx42448
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSUBv2i32_:%[0-9]+]]:fpr64 = UQSUBv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule592_id1132_at_idx42508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule592_id1132_at_idx42508
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSUBv4i32_:%[0-9]+]]:fpr128 = UQSUBv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule593_id1133_at_idx42568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule593_id1133_at_idx42568
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQSUBv2i64_:%[0-9]+]]:fpr128 = UQSUBv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule594_id1134_at_idx42628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule594_id1134_at_idx42628
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URHADDv8i8_:%[0-9]+]]:fpr64 = URHADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule595_id1135_at_idx42688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule595_id1135_at_idx42688
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URHADDv16i8_:%[0-9]+]]:fpr128 = URHADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule596_id1136_at_idx42748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule596_id1136_at_idx42748
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URHADDv4i16_:%[0-9]+]]:fpr64 = URHADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule597_id1137_at_idx42808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule597_id1137_at_idx42808
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URHADDv8i16_:%[0-9]+]]:fpr128 = URHADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule598_id1138_at_idx42868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule598_id1138_at_idx42868
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URHADDv2i32_:%[0-9]+]]:fpr64 = URHADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule599_id1139_at_idx42928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule599_id1139_at_idx42928
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URHADDv4i32_:%[0-9]+]]:fpr128 = URHADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URHADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule600_id1140_at_idx42988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule600_id1140_at_idx42988
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSHLv8i8_:%[0-9]+]]:fpr64 = URSHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule601_id1141_at_idx43048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule601_id1141_at_idx43048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URSHLv16i8_:%[0-9]+]]:fpr128 = URSHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule602_id1142_at_idx43108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule602_id1142_at_idx43108
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSHLv4i16_:%[0-9]+]]:fpr64 = URSHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule603_id1143_at_idx43168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule603_id1143_at_idx43168
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URSHLv8i16_:%[0-9]+]]:fpr128 = URSHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule604_id1144_at_idx43228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule604_id1144_at_idx43228
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSHLv2i32_:%[0-9]+]]:fpr64 = URSHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule605_id1145_at_idx43288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule605_id1145_at_idx43288
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URSHLv4i32_:%[0-9]+]]:fpr128 = URSHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule606_id1146_at_idx43348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule606_id1146_at_idx43348
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URSHLv2i64_:%[0-9]+]]:fpr128 = URSHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule607_id1147_at_idx43408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule607_id1147_at_idx43408
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLv8i8_:%[0-9]+]]:fpr64 = USHLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule608_id1148_at_idx43468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule608_id1148_at_idx43468
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule609_id1149_at_idx43528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule609_id1149_at_idx43528
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule610_id1150_at_idx43588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule610_id1150_at_idx43588
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule611_id1151_at_idx43648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule611_id1151_at_idx43648
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule612_id1152_at_idx43708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule612_id1152_at_idx43708
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule613_id1153_at_idx43768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule613_id1153_at_idx43768
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule614_id1183_at_idx43828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule614_id1183_at_idx43828
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FABD64_:%[0-9]+]]:fpr64 = FABD64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABD64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule615_id1184_at_idx43888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule615_id1184_at_idx43888
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FABD32_:%[0-9]+]]:fpr32 = FABD32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABD32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule616_id1185_at_idx43948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule616_id1185_at_idx43948
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FABD16_:%[0-9]+]]:fpr16 = FABD16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABD16_]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s16), %2(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule617_id1186_at_idx44008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule617_id1186_at_idx44008
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGE64_:%[0-9]+]]:fpr64 = FACGE64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGE64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule618_id1187_at_idx44068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule618_id1187_at_idx44068
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FACGE32_:%[0-9]+]]:fpr32 = FACGE32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGE32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule619_id1188_at_idx44128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule619_id1188_at_idx44128
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FACGT64_:%[0-9]+]]:fpr64 = FACGT64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGT64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule620_id1189_at_idx44188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule620_id1189_at_idx44188
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FACGT32_:%[0-9]+]]:fpr32 = FACGT32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FACGT32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule621_id1196_at_idx44248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule621_id1196_at_idx44248
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULX64_:%[0-9]+]]:fpr64 = FMULX64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULX64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule622_id1197_at_idx44308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule622_id1197_at_idx44308
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FMULX32_:%[0-9]+]]:fpr32 = FMULX32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULX32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule623_id1198_at_idx44368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule623_id1198_at_idx44368
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FMULX16_:%[0-9]+]]:fpr16 = FMULX16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULX16_]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s16), %2(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule624_id1199_at_idx44428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule624_id1199_at_idx44428
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPS64_:%[0-9]+]]:fpr64 = FRECPS64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPS64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule625_id1200_at_idx44488
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule625_id1200_at_idx44488
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRECPS32_:%[0-9]+]]:fpr32 = FRECPS32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPS32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule626_id1201_at_idx44548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule626_id1201_at_idx44548
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRECPS16_:%[0-9]+]]:fpr16 = FRECPS16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPS16_]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s16), %2(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule627_id1202_at_idx44608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule627_id1202_at_idx44608
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTS64_:%[0-9]+]]:fpr64 = FRSQRTS64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTS64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule628_id1203_at_idx44668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule628_id1203_at_idx44668
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRSQRTS32_:%[0-9]+]]:fpr32 = FRSQRTS32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTS32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule629_id1204_at_idx44728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule629_id1204_at_idx44728
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRSQRTS16_:%[0-9]+]]:fpr16 = FRSQRTS16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTS16_]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s16), %2(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule630_id1205_at_idx44788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule630_id1205_at_idx44788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQADDv1i64_:%[0-9]+]]:fpr64 = SQADDv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule631_id1206_at_idx44848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule631_id1206_at_idx44848
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQDMULHv1i32_:%[0-9]+]]:fpr32 = SQDMULHv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULHv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule632_id1207_at_idx44908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule632_id1207_at_idx44908
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQRDMULHv1i32_:%[0-9]+]]:fpr32 = SQRDMULHv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRDMULHv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule633_id1208_at_idx44968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule633_id1208_at_idx44968
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQRSHLv1i64_:%[0-9]+]]:fpr64 = SQRSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule634_id1209_at_idx45028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule634_id1209_at_idx45028
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSHLv1i64_:%[0-9]+]]:fpr64 = SQSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule635_id1210_at_idx45088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule635_id1210_at_idx45088
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQSUBv1i64_:%[0-9]+]]:fpr64 = SQSUBv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule636_id1211_at_idx45148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule636_id1211_at_idx45148
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRSHLv1i64_:%[0-9]+]]:fpr64 = SRSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule637_id1212_at_idx45208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule637_id1212_at_idx45208
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLv1i64_:%[0-9]+]]:fpr64 = SSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule638_id1214_at_idx45268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule638_id1214_at_idx45268
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQADDv1i64_:%[0-9]+]]:fpr64 = UQADDv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule639_id1215_at_idx45328
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule639_id1215_at_idx45328
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQRSHLv1i64_:%[0-9]+]]:fpr64 = UQRSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule640_id1216_at_idx45388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule640_id1216_at_idx45388
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSHLv1i64_:%[0-9]+]]:fpr64 = UQSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule641_id1217_at_idx45448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule641_id1217_at_idx45448
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQSUBv1i64_:%[0-9]+]]:fpr64 = UQSUBv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule642_id1218_at_idx45508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule642_id1218_at_idx45508
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSHLv1i64_:%[0-9]+]]:fpr64 = URSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule643_id1219_at_idx45568
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule643_id1219_at_idx45568
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLv1i64_:%[0-9]+]]:fpr64 = USHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule644_id1220_at_idx45628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule644_id1220_at_idx45628
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQDMULLi32_:%[0-9]+]]:fpr64 = SQDMULLi32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULLi32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule645_id1233_at_idx45688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule645_id1233_at_idx45688
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUQADDv1i64_:%[0-9]+]]:fpr64 = SUQADDv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule646_id1234_at_idx45748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule646_id1234_at_idx45748
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SUQADDv1i32_:%[0-9]+]]:fpr32 = SUQADDv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUQADDv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule647_id1239_at_idx45808
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule647_id1239_at_idx45808
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USQADDv1i64_:%[0-9]+]]:fpr64 = USQADDv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule648_id1240_at_idx45868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule648_id1240_at_idx45868
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[USQADDv1i32_:%[0-9]+]]:fpr32 = USQADDv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USQADDv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule649_id1241_at_idx45928
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule649_id1241_at_idx45928
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDHNv8i16_v8i8_:%[0-9]+]]:fpr64 = ADDHNv8i16_v8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDHNv8i16_v8i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule650_id1242_at_idx45988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule650_id1242_at_idx45988
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDHNv4i32_v4i16_:%[0-9]+]]:fpr64 = ADDHNv4i32_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDHNv4i32_v4i16_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule651_id1243_at_idx46048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule651_id1243_at_idx46048
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDHNv2i64_v2i32_:%[0-9]+]]:fpr64 = ADDHNv2i64_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDHNv2i64_v2i32_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule652_id1244_at_idx46108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule652_id1244_at_idx46108
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBHNv8i16_v8i8_:%[0-9]+]]:fpr64 = SUBHNv8i16_v8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBHNv8i16_v8i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule653_id1245_at_idx46168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule653_id1245_at_idx46168
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBHNv4i32_v4i16_:%[0-9]+]]:fpr64 = SUBHNv4i32_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBHNv4i32_v4i16_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule654_id1246_at_idx46228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule654_id1246_at_idx46228
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBHNv2i64_v2i32_:%[0-9]+]]:fpr64 = SUBHNv2i64_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBHNv2i64_v2i32_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule655_id1247_at_idx46288
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule655_id1247_at_idx46288
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RADDHNv8i16_v8i8_:%[0-9]+]]:fpr64 = RADDHNv8i16_v8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RADDHNv8i16_v8i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule656_id1248_at_idx46348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule656_id1248_at_idx46348
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RADDHNv4i32_v4i16_:%[0-9]+]]:fpr64 = RADDHNv4i32_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RADDHNv4i32_v4i16_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule657_id1249_at_idx46408
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule657_id1249_at_idx46408
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RADDHNv2i64_v2i32_:%[0-9]+]]:fpr64 = RADDHNv2i64_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RADDHNv2i64_v2i32_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule658_id1250_at_idx46468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule658_id1250_at_idx46468
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSUBHNv8i16_v8i8_:%[0-9]+]]:fpr64 = RSUBHNv8i16_v8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSUBHNv8i16_v8i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<8 x s16>), %2(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule659_id1251_at_idx46528
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule659_id1251_at_idx46528
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSUBHNv4i32_v4i16_:%[0-9]+]]:fpr64 = RSUBHNv4i32_v4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSUBHNv4i32_v4i16_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule660_id1252_at_idx46588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule660_id1252_at_idx46588
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RSUBHNv2i64_v2i32_:%[0-9]+]]:fpr64 = RSUBHNv2i64_v2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RSUBHNv2i64_v2i32_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<2 x s64>), %2(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule661_id1253_at_idx46648
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule661_id1253_at_idx46648
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[PMULLv8i8_:%[0-9]+]]:fpr128 = PMULLv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PMULLv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmull), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule662_id1290_at_idx46708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule662_id1290_at_idx46708
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULLv8i8_v8i16_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule663_id1292_at_idx46768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule663_id1292_at_idx46768
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULLv4i16_v4i32_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule664_id1294_at_idx46828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule664_id1294_at_idx46828
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SMULLv2i32_v2i64_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule665_id1304_at_idx46888
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule665_id1304_at_idx46888
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SQDMULLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULLv4i16_v4i32_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule666_id1306_at_idx46948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule666_id1306_at_idx46948
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQDMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SQDMULLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQDMULLv2i32_v2i64_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule667_id1350_at_idx47008
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule667_id1350_at_idx47008
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMULLv8i8_v8i16_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<8 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule668_id1352_at_idx47068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule668_id1352_at_idx47068
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMULLv4i16_v4i32_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<4 x s16>), %2(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule669_id1354_at_idx47128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule669_id1354_at_idx47128
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UMULLv2i32_v2i64_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<2 x s32>), %2(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule670_id1732_at_idx47188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule670_id1732_at_idx47188
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESErr:%[0-9]+]]:fpr128 = AESErr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESErr]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule671_id1733_at_idx47248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule671_id1733_at_idx47248
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESDrr:%[0-9]+]]:fpr128 = AESDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESDrr]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesd), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule672_id1744_at_idx47308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule672_id1744_at_idx47308
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA1SU1rr:%[0-9]+]]:fpr128 = SHA1SU1rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1SU1rr]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule673_id1745_at_idx47368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule673_id1745_at_idx47368
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SHA256SU0rr:%[0-9]+]]:fpr128 = SHA256SU0rr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA256SU0rr]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule681_id1852_at_idx47848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule681_id1852_at_idx47848
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQADDv1i32_:%[0-9]+]]:fpr32 = SQADDv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQADDv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule683_id1861_at_idx47968
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule683_id1861_at_idx47968
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQRSHLv1i32_:%[0-9]+]]:fpr32 = SQRSHLv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQRSHLv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule685_id1870_at_idx48088
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule685_id1870_at_idx48088
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQSHLv1i32_:%[0-9]+]]:fpr32 = SQSHLv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSHLv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule687_id1879_at_idx48208
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule687_id1879_at_idx48208
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQSUBv1i32_:%[0-9]+]]:fpr32 = SQSUBv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQSUBv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule690_id1907_at_idx48388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule690_id1907_at_idx48388
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[UQADDv1i32_:%[0-9]+]]:fpr32 = UQADDv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQADDv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule692_id1909_at_idx48508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule692_id1909_at_idx48508
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[UQRSHLv1i32_:%[0-9]+]]:fpr32 = UQRSHLv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQRSHLv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule694_id1914_at_idx48628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule694_id1914_at_idx48628
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[UQSHLv1i32_:%[0-9]+]]:fpr32 = UQSHLv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSHLv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule696_id1920_at_idx48748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule696_id1920_at_idx48748
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[UQSUBv1i32_:%[0-9]+]]:fpr32 = UQSUBv1i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQSUBv1i32_]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule698_id1979_at_idx48868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule698_id1979_at_idx48868
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIVWr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.udiv), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule699_id1980_at_idx48926
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule699_id1980_at_idx48926
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.udiv), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule700_id1981_at_idx48984
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule700_id1981_at_idx48984
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIVWr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), %1(s32), %2(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule701_id1982_at_idx49042
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule701_id1982_at_idx49042
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule702_id2457_at_idx49100
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule702_id2457_at_idx49100
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FABD64_:%[0-9]+]]:fpr64 = FABD64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FABD64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule703_id2542_at_idx49158
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule703_id2542_at_idx49158
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[PMULLv1i64_:%[0-9]+]]:fpr128 = PMULLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[PMULLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmull64), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule704_id2573_at_idx49216
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$d0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule704_id2573_at_idx49216
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[TBLv8i8One]]
+    %2:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbl1), %1(<16 x s8>), %2(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule705_id2574_at_idx49274
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule705_id2574_at_idx49274
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[TBLv16i8One]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbl1), %1(<16 x s8>), %2(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule706_id3395_at_idx49332
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule706_id3395_at_idx49332
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLv1i64_:%[0-9]+]]:fpr64 = SSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule707_id3396_at_idx49390
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule707_id3396_at_idx49390
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLv1i64_:%[0-9]+]]:fpr64 = USHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule708_id3397_at_idx49448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule708_id3397_at_idx49448
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SRSHLv1i64_:%[0-9]+]]:fpr64 = SRSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SRSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule709_id3398_at_idx49506
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule709_id3398_at_idx49506
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSHLv1i64_:%[0-9]+]]:fpr64 = URSHLv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSHLv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(s64), %2(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule710_id263_at_idx49564
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule710_id263_at_idx49564
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTASUWHr:%[0-9]+]]:gpr32 = FCVTASUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule711_id264_at_idx49612
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule711_id264_at_idx49612
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTASUXHr:%[0-9]+]]:gpr64 = FCVTASUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule712_id265_at_idx49660
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule712_id265_at_idx49660
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTASUWSr:%[0-9]+]]:gpr32 = FCVTASUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule713_id266_at_idx49708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule713_id266_at_idx49708
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTASUXSr:%[0-9]+]]:gpr64 = FCVTASUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule714_id267_at_idx49756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule714_id267_at_idx49756
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTASUWDr:%[0-9]+]]:gpr32 = FCVTASUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule715_id268_at_idx49804
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule715_id268_at_idx49804
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTASUXDr:%[0-9]+]]:gpr64 = FCVTASUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule716_id269_at_idx49852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule716_id269_at_idx49852
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTAUUWHr:%[0-9]+]]:gpr32 = FCVTAUUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule717_id270_at_idx49900
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule717_id270_at_idx49900
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTAUUXHr:%[0-9]+]]:gpr64 = FCVTAUUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule718_id271_at_idx49948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule718_id271_at_idx49948
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTAUUWSr:%[0-9]+]]:gpr32 = FCVTAUUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule719_id272_at_idx49996
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule719_id272_at_idx49996
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTAUUXSr:%[0-9]+]]:gpr64 = FCVTAUUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule720_id273_at_idx50044
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule720_id273_at_idx50044
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTAUUWDr:%[0-9]+]]:gpr32 = FCVTAUUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule721_id274_at_idx50092
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule721_id274_at_idx50092
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTAUUXDr:%[0-9]+]]:gpr64 = FCVTAUUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule722_id275_at_idx50140
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule722_id275_at_idx50140
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTMSUWHr:%[0-9]+]]:gpr32 = FCVTMSUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule723_id276_at_idx50188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule723_id276_at_idx50188
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTMSUXHr:%[0-9]+]]:gpr64 = FCVTMSUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule724_id277_at_idx50236
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule724_id277_at_idx50236
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTMSUWSr:%[0-9]+]]:gpr32 = FCVTMSUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule725_id278_at_idx50284
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule725_id278_at_idx50284
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTMSUXSr:%[0-9]+]]:gpr64 = FCVTMSUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule726_id279_at_idx50332
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule726_id279_at_idx50332
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMSUWDr:%[0-9]+]]:gpr32 = FCVTMSUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule727_id280_at_idx50380
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule727_id280_at_idx50380
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMSUXDr:%[0-9]+]]:gpr64 = FCVTMSUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule728_id281_at_idx50428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule728_id281_at_idx50428
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTMUUWHr:%[0-9]+]]:gpr32 = FCVTMUUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule729_id282_at_idx50476
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule729_id282_at_idx50476
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTMUUXHr:%[0-9]+]]:gpr64 = FCVTMUUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule730_id283_at_idx50524
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule730_id283_at_idx50524
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTMUUWSr:%[0-9]+]]:gpr32 = FCVTMUUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule731_id284_at_idx50572
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule731_id284_at_idx50572
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTMUUXSr:%[0-9]+]]:gpr64 = FCVTMUUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule732_id285_at_idx50620
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule732_id285_at_idx50620
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMUUWDr:%[0-9]+]]:gpr32 = FCVTMUUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule733_id286_at_idx50668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule733_id286_at_idx50668
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMUUXDr:%[0-9]+]]:gpr64 = FCVTMUUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule734_id287_at_idx50716
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule734_id287_at_idx50716
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTNSUWHr:%[0-9]+]]:gpr32 = FCVTNSUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule735_id288_at_idx50764
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule735_id288_at_idx50764
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTNSUXHr:%[0-9]+]]:gpr64 = FCVTNSUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule736_id289_at_idx50812
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule736_id289_at_idx50812
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTNSUWSr:%[0-9]+]]:gpr32 = FCVTNSUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule737_id290_at_idx50860
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule737_id290_at_idx50860
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTNSUXSr:%[0-9]+]]:gpr64 = FCVTNSUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule738_id291_at_idx50908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule738_id291_at_idx50908
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNSUWDr:%[0-9]+]]:gpr32 = FCVTNSUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule739_id292_at_idx50956
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule739_id292_at_idx50956
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNSUXDr:%[0-9]+]]:gpr64 = FCVTNSUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule740_id293_at_idx51004
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule740_id293_at_idx51004
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTNUUWHr:%[0-9]+]]:gpr32 = FCVTNUUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule741_id294_at_idx51052
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule741_id294_at_idx51052
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTNUUXHr:%[0-9]+]]:gpr64 = FCVTNUUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule742_id295_at_idx51100
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule742_id295_at_idx51100
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTNUUWSr:%[0-9]+]]:gpr32 = FCVTNUUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule743_id296_at_idx51148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule743_id296_at_idx51148
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTNUUXSr:%[0-9]+]]:gpr64 = FCVTNUUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule744_id297_at_idx51196
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule744_id297_at_idx51196
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNUUWDr:%[0-9]+]]:gpr32 = FCVTNUUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule745_id298_at_idx51244
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule745_id298_at_idx51244
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNUUXDr:%[0-9]+]]:gpr64 = FCVTNUUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule746_id299_at_idx51292
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule746_id299_at_idx51292
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTPSUWHr:%[0-9]+]]:gpr32 = FCVTPSUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule747_id300_at_idx51340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule747_id300_at_idx51340
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTPSUXHr:%[0-9]+]]:gpr64 = FCVTPSUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule748_id301_at_idx51388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule748_id301_at_idx51388
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTPSUWSr:%[0-9]+]]:gpr32 = FCVTPSUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule749_id302_at_idx51436
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule749_id302_at_idx51436
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTPSUXSr:%[0-9]+]]:gpr64 = FCVTPSUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule750_id303_at_idx51484
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule750_id303_at_idx51484
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPSUWDr:%[0-9]+]]:gpr32 = FCVTPSUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule751_id304_at_idx51532
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule751_id304_at_idx51532
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPSUXDr:%[0-9]+]]:gpr64 = FCVTPSUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule752_id305_at_idx51580
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule752_id305_at_idx51580
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTPUUWHr:%[0-9]+]]:gpr32 = FCVTPUUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule753_id306_at_idx51628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule753_id306_at_idx51628
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTPUUXHr:%[0-9]+]]:gpr64 = FCVTPUUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule754_id307_at_idx51676
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule754_id307_at_idx51676
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTPUUWSr:%[0-9]+]]:gpr32 = FCVTPUUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule755_id308_at_idx51724
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule755_id308_at_idx51724
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTPUUXSr:%[0-9]+]]:gpr64 = FCVTPUUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule756_id309_at_idx51772
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule756_id309_at_idx51772
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPUUWDr:%[0-9]+]]:gpr32 = FCVTPUUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule757_id310_at_idx51820
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule757_id310_at_idx51820
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPUUXDr:%[0-9]+]]:gpr64 = FCVTPUUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule758_id383_at_idx51868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule758_id383_at_idx51868
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRINTNHr:%[0-9]+]]:fpr16 = FRINTNHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule759_id384_at_idx51916
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule759_id384_at_idx51916
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRINTNSr:%[0-9]+]]:fpr32 = FRINTNSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule760_id385_at_idx51964
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule760_id385_at_idx51964
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRINTNDr:%[0-9]+]]:fpr64 = FRINTNDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule761_id465_at_idx52012
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule761_id465_at_idx52012
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[CLSv8i8_:%[0-9]+]]:fpr64 = CLSv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule762_id466_at_idx52060
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule762_id466_at_idx52060
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[CLSv16i8_:%[0-9]+]]:fpr128 = CLSv16i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv16i8_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule763_id467_at_idx52108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule763_id467_at_idx52108
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[CLSv4i16_:%[0-9]+]]:fpr64 = CLSv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule764_id468_at_idx52156
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule764_id468_at_idx52156
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[CLSv8i16_:%[0-9]+]]:fpr128 = CLSv8i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv8i16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule765_id469_at_idx52204
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule765_id469_at_idx52204
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[CLSv2i32_:%[0-9]+]]:fpr64 = CLSv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule766_id470_at_idx52252
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule766_id470_at_idx52252
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[CLSv4i32_:%[0-9]+]]:fpr128 = CLSv4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[CLSv4i32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule767_id544_at_idx52300
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule767_id544_at_idx52300
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTASv4f16_:%[0-9]+]]:fpr64 = FCVTASv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule768_id545_at_idx52348
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule768_id545_at_idx52348
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTASv8f16_:%[0-9]+]]:fpr128 = FCVTASv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule769_id546_at_idx52396
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule769_id546_at_idx52396
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTASv2f32_:%[0-9]+]]:fpr64 = FCVTASv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule770_id547_at_idx52444
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule770_id547_at_idx52444
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTASv4f32_:%[0-9]+]]:fpr128 = FCVTASv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule771_id548_at_idx52492
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule771_id548_at_idx52492
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTASv2f64_:%[0-9]+]]:fpr128 = FCVTASv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule772_id549_at_idx52540
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule772_id549_at_idx52540
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTAUv4f16_:%[0-9]+]]:fpr64 = FCVTAUv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule773_id550_at_idx52588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule773_id550_at_idx52588
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTAUv8f16_:%[0-9]+]]:fpr128 = FCVTAUv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule774_id551_at_idx52636
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule774_id551_at_idx52636
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTAUv2f32_:%[0-9]+]]:fpr64 = FCVTAUv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule775_id552_at_idx52684
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule775_id552_at_idx52684
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTAUv4f32_:%[0-9]+]]:fpr128 = FCVTAUv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule776_id553_at_idx52732
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule776_id553_at_idx52732
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTAUv2f64_:%[0-9]+]]:fpr128 = FCVTAUv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule777_id554_at_idx52780
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule777_id554_at_idx52780
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMSv4f16_:%[0-9]+]]:fpr64 = FCVTMSv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule778_id555_at_idx52828
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule778_id555_at_idx52828
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMSv8f16_:%[0-9]+]]:fpr128 = FCVTMSv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule779_id556_at_idx52876
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule779_id556_at_idx52876
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMSv2f32_:%[0-9]+]]:fpr64 = FCVTMSv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule780_id557_at_idx52924
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule780_id557_at_idx52924
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMSv4f32_:%[0-9]+]]:fpr128 = FCVTMSv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule781_id558_at_idx52972
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule781_id558_at_idx52972
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMSv2f64_:%[0-9]+]]:fpr128 = FCVTMSv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule782_id559_at_idx53020
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule782_id559_at_idx53020
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMUv4f16_:%[0-9]+]]:fpr64 = FCVTMUv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule783_id560_at_idx53068
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule783_id560_at_idx53068
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMUv8f16_:%[0-9]+]]:fpr128 = FCVTMUv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule784_id561_at_idx53116
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule784_id561_at_idx53116
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMUv2f32_:%[0-9]+]]:fpr64 = FCVTMUv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule785_id562_at_idx53164
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule785_id562_at_idx53164
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMUv4f32_:%[0-9]+]]:fpr128 = FCVTMUv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule786_id563_at_idx53212
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule786_id563_at_idx53212
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTMUv2f64_:%[0-9]+]]:fpr128 = FCVTMUv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule787_id564_at_idx53260
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule787_id564_at_idx53260
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNSv4f16_:%[0-9]+]]:fpr64 = FCVTNSv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule788_id565_at_idx53308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule788_id565_at_idx53308
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNSv8f16_:%[0-9]+]]:fpr128 = FCVTNSv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule789_id566_at_idx53356
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule789_id566_at_idx53356
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNSv2f32_:%[0-9]+]]:fpr64 = FCVTNSv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule790_id567_at_idx53404
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule790_id567_at_idx53404
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNSv4f32_:%[0-9]+]]:fpr128 = FCVTNSv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule791_id568_at_idx53452
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule791_id568_at_idx53452
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNSv2f64_:%[0-9]+]]:fpr128 = FCVTNSv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule792_id569_at_idx53500
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule792_id569_at_idx53500
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNUv4f16_:%[0-9]+]]:fpr64 = FCVTNUv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule793_id570_at_idx53548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule793_id570_at_idx53548
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNUv8f16_:%[0-9]+]]:fpr128 = FCVTNUv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule794_id571_at_idx53596
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule794_id571_at_idx53596
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNUv2f32_:%[0-9]+]]:fpr64 = FCVTNUv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule795_id572_at_idx53644
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule795_id572_at_idx53644
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNUv4f32_:%[0-9]+]]:fpr128 = FCVTNUv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule796_id573_at_idx53692
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule796_id573_at_idx53692
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNUv2f64_:%[0-9]+]]:fpr128 = FCVTNUv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule797_id574_at_idx53740
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule797_id574_at_idx53740
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPSv4f16_:%[0-9]+]]:fpr64 = FCVTPSv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule798_id575_at_idx53788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule798_id575_at_idx53788
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPSv8f16_:%[0-9]+]]:fpr128 = FCVTPSv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule799_id576_at_idx53836
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule799_id576_at_idx53836
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPSv2f32_:%[0-9]+]]:fpr64 = FCVTPSv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule800_id577_at_idx53884
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule800_id577_at_idx53884
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPSv4f32_:%[0-9]+]]:fpr128 = FCVTPSv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule801_id578_at_idx53932
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule801_id578_at_idx53932
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPSv2f64_:%[0-9]+]]:fpr128 = FCVTPSv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule802_id579_at_idx53980
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule802_id579_at_idx53980
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPUv4f16_:%[0-9]+]]:fpr64 = FCVTPUv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule803_id580_at_idx54028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule803_id580_at_idx54028
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPUv8f16_:%[0-9]+]]:fpr128 = FCVTPUv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule804_id581_at_idx54076
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule804_id581_at_idx54076
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPUv2f32_:%[0-9]+]]:fpr64 = FCVTPUv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule805_id582_at_idx54124
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule805_id582_at_idx54124
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPUv4f32_:%[0-9]+]]:fpr128 = FCVTPUv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule806_id583_at_idx54172
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule806_id583_at_idx54172
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTPUv2f64_:%[0-9]+]]:fpr128 = FCVTPUv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule807_id584_at_idx54220
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule807_id584_at_idx54220
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTXNv2f32_:%[0-9]+]]:fpr64 = FCVTXNv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTXNv2f32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtxn), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule808_id600_at_idx54268
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule808_id600_at_idx54268
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPEv4f16_:%[0-9]+]]:fpr64 = FRECPEv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule809_id601_at_idx54316
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule809_id601_at_idx54316
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPEv8f16_:%[0-9]+]]:fpr128 = FRECPEv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule810_id602_at_idx54364
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule810_id602_at_idx54364
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPEv2f32_:%[0-9]+]]:fpr64 = FRECPEv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule811_id603_at_idx54412
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule811_id603_at_idx54412
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPEv4f32_:%[0-9]+]]:fpr128 = FRECPEv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule812_id604_at_idx54460
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule812_id604_at_idx54460
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRECPEv2f64_:%[0-9]+]]:fpr128 = FRECPEv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule813_id620_at_idx54508
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule813_id620_at_idx54508
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRINTNv4f16_:%[0-9]+]]:fpr64 = FRINTNv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule814_id621_at_idx54556
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule814_id621_at_idx54556
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRINTNv8f16_:%[0-9]+]]:fpr128 = FRINTNv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule815_id622_at_idx54604
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule815_id622_at_idx54604
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRINTNv2f32_:%[0-9]+]]:fpr64 = FRINTNv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule816_id623_at_idx54652
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule816_id623_at_idx54652
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRINTNv4f32_:%[0-9]+]]:fpr128 = FRINTNv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule817_id624_at_idx54700
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule817_id624_at_idx54700
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRINTNv2f64_:%[0-9]+]]:fpr128 = FRINTNv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule818_id640_at_idx54748
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule818_id640_at_idx54748
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTEv4f16_:%[0-9]+]]:fpr64 = FRSQRTEv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule819_id641_at_idx54796
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule819_id641_at_idx54796
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTEv8f16_:%[0-9]+]]:fpr128 = FRSQRTEv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule820_id642_at_idx54844
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule820_id642_at_idx54844
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTEv2f32_:%[0-9]+]]:fpr64 = FRSQRTEv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule821_id643_at_idx54892
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule821_id643_at_idx54892
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTEv4f32_:%[0-9]+]]:fpr128 = FRSQRTEv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule822_id644_at_idx54940
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule822_id644_at_idx54940
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FRSQRTEv2f64_:%[0-9]+]]:fpr128 = FRSQRTEv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule823_id659_at_idx54988
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule823_id659_at_idx54988
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[RBITv8i8_:%[0-9]+]]:fpr64 = RBITv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RBITv8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rbit), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule824_id660_at_idx55036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule824_id660_at_idx55036
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[RBITv16i8_:%[0-9]+]]:fpr128 = RBITv16i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[RBITv16i8_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rbit), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule825_id679_at_idx55084
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule825_id679_at_idx55084
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLPv8i8_v4i16_:%[0-9]+]]:fpr64 = SADDLPv8i8_v4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv8i8_v4i16_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule826_id680_at_idx55132
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule826_id680_at_idx55132
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDLPv16i8_v8i16_:%[0-9]+]]:fpr128 = SADDLPv16i8_v8i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv16i8_v8i16_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule827_id681_at_idx55180
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule827_id681_at_idx55180
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLPv4i16_v2i32_:%[0-9]+]]:fpr64 = SADDLPv4i16_v2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv4i16_v2i32_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule828_id682_at_idx55228
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule828_id682_at_idx55228
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDLPv8i16_v4i32_:%[0-9]+]]:fpr128 = SADDLPv8i16_v4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv8i16_v4i32_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule829_id683_at_idx55276
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule829_id683_at_idx55276
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SADDLPv2i32_v1i64_:%[0-9]+]]:fpr64 = SADDLPv2i32_v1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv2i32_v1i64_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule830_id684_at_idx55324
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule830_id684_at_idx55324
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDLPv4i32_v2i64_:%[0-9]+]]:fpr128 = SADDLPv4i32_v2i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDLPv4i32_v2i64_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule831_id690_at_idx55372
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule831_id690_at_idx55372
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQABSv8i8_:%[0-9]+]]:fpr64 = SQABSv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule832_id691_at_idx55420
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule832_id691_at_idx55420
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQABSv16i8_:%[0-9]+]]:fpr128 = SQABSv16i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv16i8_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule833_id692_at_idx55468
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule833_id692_at_idx55468
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQABSv4i16_:%[0-9]+]]:fpr64 = SQABSv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule834_id693_at_idx55516
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule834_id693_at_idx55516
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQABSv8i16_:%[0-9]+]]:fpr128 = SQABSv8i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv8i16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule835_id694_at_idx55564
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule835_id694_at_idx55564
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQABSv2i32_:%[0-9]+]]:fpr64 = SQABSv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule836_id695_at_idx55612
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule836_id695_at_idx55612
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQABSv4i32_:%[0-9]+]]:fpr128 = SQABSv4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv4i32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule837_id696_at_idx55660
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule837_id696_at_idx55660
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQABSv2i64_:%[0-9]+]]:fpr128 = SQABSv2i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv2i64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule838_id697_at_idx55708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule838_id697_at_idx55708
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQNEGv8i8_:%[0-9]+]]:fpr64 = SQNEGv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule839_id698_at_idx55756
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule839_id698_at_idx55756
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQNEGv16i8_:%[0-9]+]]:fpr128 = SQNEGv16i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv16i8_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule840_id699_at_idx55804
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule840_id699_at_idx55804
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQNEGv4i16_:%[0-9]+]]:fpr64 = SQNEGv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule841_id700_at_idx55852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule841_id700_at_idx55852
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQNEGv8i16_:%[0-9]+]]:fpr128 = SQNEGv8i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv8i16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule842_id701_at_idx55900
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule842_id701_at_idx55900
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQNEGv2i32_:%[0-9]+]]:fpr64 = SQNEGv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule843_id702_at_idx55948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule843_id702_at_idx55948
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQNEGv4i32_:%[0-9]+]]:fpr128 = SQNEGv4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv4i32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule844_id703_at_idx55996
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule844_id703_at_idx55996
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQNEGv2i64_:%[0-9]+]]:fpr128 = SQNEGv2i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv2i64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule845_id704_at_idx56044
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule845_id704_at_idx56044
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTNv8i8_:%[0-9]+]]:fpr64 = SQXTNv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTNv8i8_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule846_id705_at_idx56092
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule846_id705_at_idx56092
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTNv4i16_:%[0-9]+]]:fpr64 = SQXTNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule847_id706_at_idx56140
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule847_id706_at_idx56140
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTNv2i32_:%[0-9]+]]:fpr64 = SQXTNv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTNv2i32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule848_id707_at_idx56188
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule848_id707_at_idx56188
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTUNv8i8_:%[0-9]+]]:fpr64 = SQXTUNv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTUNv8i8_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule849_id708_at_idx56236
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule849_id708_at_idx56236
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTUNv4i16_:%[0-9]+]]:fpr64 = SQXTUNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTUNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule850_id709_at_idx56284
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule850_id709_at_idx56284
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SQXTUNv2i32_:%[0-9]+]]:fpr64 = SQXTUNv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTUNv2i32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule851_id723_at_idx56332
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule851_id723_at_idx56332
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLPv8i8_v4i16_:%[0-9]+]]:fpr64 = UADDLPv8i8_v4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv8i8_v4i16_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule852_id724_at_idx56380
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule852_id724_at_idx56380
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDLPv16i8_v8i16_:%[0-9]+]]:fpr128 = UADDLPv16i8_v8i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv16i8_v8i16_]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule853_id725_at_idx56428
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule853_id725_at_idx56428
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLPv4i16_v2i32_:%[0-9]+]]:fpr64 = UADDLPv4i16_v2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv4i16_v2i32_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule854_id726_at_idx56476
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule854_id726_at_idx56476
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDLPv8i16_v4i32_:%[0-9]+]]:fpr128 = UADDLPv8i16_v4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv8i16_v4i32_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule855_id727_at_idx56524
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule855_id727_at_idx56524
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UADDLPv2i32_v1i64_:%[0-9]+]]:fpr64 = UADDLPv2i32_v1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv2i32_v1i64_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule856_id728_at_idx56572
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule856_id728_at_idx56572
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDLPv4i32_v2i64_:%[0-9]+]]:fpr128 = UADDLPv4i32_v2i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDLPv4i32_v2i64_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule857_id734_at_idx56620
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule857_id734_at_idx56620
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQXTNv8i8_:%[0-9]+]]:fpr64 = UQXTNv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQXTNv8i8_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule858_id735_at_idx56668
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule858_id735_at_idx56668
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQXTNv4i16_:%[0-9]+]]:fpr64 = UQXTNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQXTNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule859_id736_at_idx56716
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule859_id736_at_idx56716
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UQXTNv2i32_:%[0-9]+]]:fpr64 = UQXTNv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQXTNv2i32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule860_id737_at_idx56764
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule860_id737_at_idx56764
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URECPEv2i32_:%[0-9]+]]:fpr64 = URECPEv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URECPEv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urecpe), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule861_id738_at_idx56812
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule861_id738_at_idx56812
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URECPEv4i32_:%[0-9]+]]:fpr128 = URECPEv4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URECPEv4i32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urecpe), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule862_id739_at_idx56860
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule862_id739_at_idx56860
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[URSQRTEv2i32_:%[0-9]+]]:fpr64 = URSQRTEv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSQRTEv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ursqrte), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule863_id740_at_idx56908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule863_id740_at_idx56908
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[URSQRTEv4i32_:%[0-9]+]]:fpr128 = URSQRTEv4i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[URSQRTEv4i32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ursqrte), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule864_id1222_at_idx56956
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule864_id1222_at_idx56956
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTXNv1i64_:%[0-9]+]]:fpr32 = FCVTXNv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTXNv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fcvtxn), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule865_id1227_at_idx57004
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule865_id1227_at_idx57004
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQABSv1i64_:%[0-9]+]]:fpr64 = SQABSv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule866_id1228_at_idx57052
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule866_id1228_at_idx57052
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQABSv1i32_:%[0-9]+]]:fpr32 = SQABSv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQABSv1i32_]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule867_id1229_at_idx57100
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule867_id1229_at_idx57100
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQNEGv1i64_:%[0-9]+]]:fpr64 = SQNEGv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule868_id1230_at_idx57148
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule868_id1230_at_idx57148
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SQNEGv1i32_:%[0-9]+]]:fpr32 = SQNEGv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQNEGv1i32_]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule869_id1231_at_idx57196
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule869_id1231_at_idx57196
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQXTNv1i32_:%[0-9]+]]:fpr32 = SQXTNv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTNv1i32_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.sqxtn), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule870_id1232_at_idx57244
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule870_id1232_at_idx57244
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SQXTUNv1i32_:%[0-9]+]]:fpr32 = SQXTUNv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SQXTUNv1i32_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.sqxtun), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule871_id1238_at_idx57292
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule871_id1238_at_idx57292
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UQXTNv1i32_:%[0-9]+]]:fpr32 = UQXTNv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UQXTNv1i32_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.uqxtn), %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule872_id1438_at_idx57340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule872_id1438_at_idx57340
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXNMVv4i16v:%[0-9]+]]:fpr16 = FMAXNMVv4i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMVv4i16v]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule873_id1439_at_idx57388
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule873_id1439_at_idx57388
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMVv8i16v:%[0-9]+]]:fpr16 = FMAXNMVv8i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMVv8i16v]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule874_id1440_at_idx57436
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule874_id1440_at_idx57436
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMVv4i32v:%[0-9]+]]:fpr32 = FMAXNMVv4i32v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMVv4i32v]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule875_id1441_at_idx57484
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule875_id1441_at_idx57484
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXVv4i16v:%[0-9]+]]:fpr16 = FMAXVv4i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXVv4i16v]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule876_id1442_at_idx57532
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule876_id1442_at_idx57532
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXVv8i16v:%[0-9]+]]:fpr16 = FMAXVv8i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXVv8i16v]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule877_id1443_at_idx57580
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule877_id1443_at_idx57580
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXVv4i32v:%[0-9]+]]:fpr32 = FMAXVv4i32v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXVv4i32v]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule878_id1444_at_idx57628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule878_id1444_at_idx57628
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINNMVv4i16v:%[0-9]+]]:fpr16 = FMINNMVv4i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMVv4i16v]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule879_id1445_at_idx57676
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule879_id1445_at_idx57676
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMVv8i16v:%[0-9]+]]:fpr16 = FMINNMVv8i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMVv8i16v]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule880_id1446_at_idx57724
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule880_id1446_at_idx57724
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMVv4i32v:%[0-9]+]]:fpr32 = FMINNMVv4i32v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMVv4i32v]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule881_id1447_at_idx57772
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule881_id1447_at_idx57772
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINVv4i16v:%[0-9]+]]:fpr16 = FMINVv4i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINVv4i16v]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule882_id1448_at_idx57820
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule882_id1448_at_idx57820
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINVv8i16v:%[0-9]+]]:fpr16 = FMINVv8i16v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINVv8i16v]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule883_id1449_at_idx57868
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule883_id1449_at_idx57868
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINVv4i32v:%[0-9]+]]:fpr32 = FMINVv4i32v [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINVv4i32v]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule884_id1734_at_idx57916
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule884_id1734_at_idx57916
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESMCrr:%[0-9]+]]:fpr128 = AESMCrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESMCrr]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule885_id1735_at_idx57964
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule885_id1735_at_idx57964
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[AESIMCrr:%[0-9]+]]:fpr128 = AESIMCrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[AESIMCrr]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesimc), %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule886_id1743_at_idx58012
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule886_id1743_at_idx58012
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[SHA1Hrr:%[0-9]+]]:fpr32 = SHA1Hrr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SHA1Hrr]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1h), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule889_id2362_at_idx58156
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule889_id2362_at_idx58156
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRINTNDr:%[0-9]+]]:fpr64 = FRINTNDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRINTNDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule890_id2381_at_idx58202
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule890_id2381_at_idx58202
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvthf2fp), %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule891_id2387_at_idx58248
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule891_id2387_at_idx58248
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2hf), %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule892_id2463_at_idx58294
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule892_id2463_at_idx58294
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTASv1i64_:%[0-9]+]]:fpr64 = FCVTASv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTASv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule893_id2464_at_idx58340
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule893_id2464_at_idx58340
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTAUv1i64_:%[0-9]+]]:fpr64 = FCVTAUv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTAUv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule894_id2465_at_idx58386
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule894_id2465_at_idx58386
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMSv1i64_:%[0-9]+]]:fpr64 = FCVTMSv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMSv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule895_id2466_at_idx58432
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule895_id2466_at_idx58432
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTMUv1i64_:%[0-9]+]]:fpr64 = FCVTMUv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTMUv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule896_id2467_at_idx58478
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule896_id2467_at_idx58478
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNSv1i64_:%[0-9]+]]:fpr64 = FCVTNSv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNSv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule897_id2468_at_idx58524
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule897_id2468_at_idx58524
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTNUv1i64_:%[0-9]+]]:fpr64 = FCVTNUv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNUv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule898_id2469_at_idx58570
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule898_id2469_at_idx58570
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPSv1i64_:%[0-9]+]]:fpr64 = FCVTPSv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPSv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule899_id2470_at_idx58616
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule899_id2470_at_idx58616
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTPUv1i64_:%[0-9]+]]:fpr64 = FCVTPUv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTPUv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule900_id2471_at_idx58662
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule900_id2471_at_idx58662
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRECPEv1f16_:%[0-9]+]]:fpr16 = FRECPEv1f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv1f16_]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule901_id2472_at_idx58708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule901_id2472_at_idx58708
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRECPEv1i32_:%[0-9]+]]:fpr32 = FRECPEv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv1i32_]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule902_id2473_at_idx58754
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule902_id2473_at_idx58754
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPEv1i64_:%[0-9]+]]:fpr64 = FRECPEv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPEv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule904_id2486_at_idx58846
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule904_id2486_at_idx58846
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRECPXv1f16_:%[0-9]+]]:fpr16 = FRECPXv1f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPXv1f16_]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule905_id2487_at_idx58892
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule905_id2487_at_idx58892
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRECPXv1i32_:%[0-9]+]]:fpr32 = FRECPXv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPXv1i32_]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule906_id2488_at_idx58938
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule906_id2488_at_idx58938
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRECPXv1i64_:%[0-9]+]]:fpr64 = FRECPXv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRECPXv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule907_id2489_at_idx58984
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule907_id2489_at_idx58984
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FRSQRTEv1f16_:%[0-9]+]]:fpr16 = FRSQRTEv1f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv1f16_]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s16)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule908_id2490_at_idx59030
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule908_id2490_at_idx59030
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FRSQRTEv1i32_:%[0-9]+]]:fpr32 = FRSQRTEv1i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv1i32_]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule909_id2491_at_idx59076
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule909_id2491_at_idx59076
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FRSQRTEv1i64_:%[0-9]+]]:fpr64 = FRSQRTEv1i64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FRSQRTEv1i64_]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule911_id2579_at_idx59168
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule911_id2579_at_idx59168
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FADDPv2i32p:%[0-9]+]]:fpr32 = FADDPv2i32p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDPv2i32p]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.faddv), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule912_id2581_at_idx59214
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule912_id2581_at_idx59214
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FADDPv2i64p:%[0-9]+]]:fpr64 = FADDPv2i64p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDPv2i64p]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.faddv), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule913_id2582_at_idx59260
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule913_id2582_at_idx59260
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXNMPv2i32p:%[0-9]+]]:fpr32 = FMAXNMPv2i32p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv2i32p]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule914_id2583_at_idx59306
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule914_id2583_at_idx59306
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXNMPv2i64p:%[0-9]+]]:fpr64 = FMAXNMPv2i64p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXNMPv2i64p]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule915_id2584_at_idx59352
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule915_id2584_at_idx59352
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMAXPv2i32p:%[0-9]+]]:fpr32 = FMAXPv2i32p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv2i32p]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule916_id2585_at_idx59398
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule916_id2585_at_idx59398
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMAXPv2i64p:%[0-9]+]]:fpr64 = FMAXPv2i64p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMAXPv2i64p]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule917_id2586_at_idx59444
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule917_id2586_at_idx59444
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINNMPv2i32p:%[0-9]+]]:fpr32 = FMINNMPv2i32p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv2i32p]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule918_id2587_at_idx59490
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule918_id2587_at_idx59490
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINNMPv2i64p:%[0-9]+]]:fpr64 = FMINNMPv2i64p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINNMPv2i64p]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule919_id2588_at_idx59536
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule919_id2588_at_idx59536
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMINPv2i32p:%[0-9]+]]:fpr32 = FMINPv2i32p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv2i32p]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule920_id2589_at_idx59582
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule920_id2589_at_idx59582
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMINPv2i64p:%[0-9]+]]:fpr64 = FMINPv2i64p [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMINPv2i64p]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule921_id1983_at_idx59628
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule921_id1983_at_idx59628
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY]], $wzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MADDWrrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule922_id1984_at_idx59685
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule922_id1984_at_idx59685
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY1]], [[COPY]], $xzr
+    ; SELECTED: $noreg = PATCHABLE_RET [[MADDXrrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule923_id2005_at_idx59742
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule923_id2005_at_idx59742
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNWrr]]
+    %1:gpr(s32) = COPY $w0
+    %2:gpr(s32) = G_CONSTANT -1
+    %0:gpr(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule924_id2006_at_idx59795
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule924_id2006_at_idx59795
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORNXrr]]
+    %1:gpr(s64) = COPY $x0
+    %2:gpr(s64) = G_CONSTANT -1
+    %0:gpr(s64) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule925_id3488_at_idx59848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule925_id3488_at_idx59848
+    ; SELECTED: CLREX 15
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.clrex)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule926_id2019_at_idx59877
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule926_id2019_at_idx59877
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 1, 63
+    ; SELECTED: $noreg = PATCHABLE_RET [[UBFMXri]]
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule927_id2020_at_idx59948
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule927_id2020_at_idx59948
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 1, 63
+    ; SELECTED: $noreg = PATCHABLE_RET [[UBFMXri]]
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_CONSTANT 1
+    %1:gpr(s64) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule928_id2367_at_idx60019
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule928_id2367_at_idx60019
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FNEG %4
+    %1:fpr(s32) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule929_id2368_at_idx60105
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule929_id2368_at_idx60105
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
+    %4:fpr(s64) = COPY $d2
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FNEG %4
+    %1:fpr(s64) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule930_id2446_at_idx60191
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule930_id2446_at_idx60191
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FNEG %4
+    %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule931_id2447_at_idx60277
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule931_id2447_at_idx60277
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FNEG %4
+    %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule932_id2448_at_idx60363
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule932_id2448_at_idx60363
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
+    %4:fpr(<2 x s64>) = COPY $q2
+    %3:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FNEG %4
+    %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule933_id428_at_idx60449
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%2' }
+  - { reg: '$h1', virtual-reg: '%3' }
+  - { reg: '$h2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1, $h2
+
+    ; SELECTED-LABEL: name: test_rule933_id428_at_idx60449
+    ; SELECTED: liveins: $h0, $h1, $h2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FMSUBHrrr:%[0-9]+]]:fpr16 = FMSUBHrrr [[COPY2]], [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMSUBHrrr]]
+    %4:fpr(s16) = COPY $h2
+    %3:fpr(s16) = COPY $h1
+    %2:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FNEG %4
+    %1:fpr(s16) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule934_id429_at_idx60537
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule934_id429_at_idx60537
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FNEG %4
+    %1:fpr(s32) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule935_id430_at_idx60625
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule935_id430_at_idx60625
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
+    %4:fpr(s64) = COPY $d2
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FNEG %4
+    %1:fpr(s64) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule936_id897_at_idx60713
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule936_id897_at_idx60713
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMLSv4f16_:%[0-9]+]]:fpr64 = FMLSv4f16 [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv4f16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FNEG %4
+    %1:fpr(<4 x s16>) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule937_id898_at_idx60801
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule937_id898_at_idx60801
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLSv8f16_:%[0-9]+]]:fpr128 = FMLSv8f16 [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv8f16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FNEG %4
+    %1:fpr(<8 x s16>) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule938_id899_at_idx60889
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule938_id899_at_idx60889
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FNEG %4
+    %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule939_id900_at_idx60977
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule939_id900_at_idx60977
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FNEG %4
+    %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule940_id901_at_idx61065
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule940_id901_at_idx61065
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
+    %4:fpr(<2 x s64>) = COPY $q2
+    %3:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FNEG %4
+    %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule941_id434_at_idx61153
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%2' }
+  - { reg: '$h1', virtual-reg: '%3' }
+  - { reg: '$h2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1, $h2
+
+    ; SELECTED-LABEL: name: test_rule941_id434_at_idx61153
+    ; SELECTED: liveins: $h0, $h1, $h2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FNMSUBHrrr:%[0-9]+]]:fpr16 = FNMSUBHrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMSUBHrrr]]
+    %4:fpr(s16) = COPY $h2
+    %3:fpr(s16) = COPY $h1
+    %2:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FNEG %4
+    %1:fpr(s16) = G_FMA %2, %3, %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule942_id435_at_idx61241
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule942_id435_at_idx61241
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FNEG %4
+    %1:fpr(s32) = G_FMA %2, %3, %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule943_id436_at_idx61329
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule943_id436_at_idx61329
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
+    %4:fpr(s64) = COPY $d2
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FNEG %4
+    %1:fpr(s64) = G_FMA %2, %3, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule944_id3803_at_idx61417
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule944_id3803_at_idx61417
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_MUL %3, %4
+    %1:fpr(<8 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule945_id3804_at_idx61505
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule945_id3804_at_idx61505
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_MUL %3, %4
+    %1:fpr(<16 x s8>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule946_id3805_at_idx61593
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule946_id3805_at_idx61593
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_MUL %3, %4
+    %1:fpr(<4 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule947_id3806_at_idx61681
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule947_id3806_at_idx61681
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_MUL %3, %4
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule948_id3807_at_idx61769
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule948_id3807_at_idx61769
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv2i32_:%[0-9]+]]:fpr64 = MLAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_MUL %3, %4
+    %1:fpr(<2 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule949_id3808_at_idx61857
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule949_id3808_at_idx61857
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv4i32_:%[0-9]+]]:fpr128 = MLAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_MUL %3, %4
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule950_id3869_at_idx61945
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule950_id3869_at_idx61945
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule951_id3871_at_idx62021
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule951_id3871_at_idx62021
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule952_id3873_at_idx62097
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule952_id3873_at_idx62097
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule953_id3887_at_idx62173
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule953_id3887_at_idx62173
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule954_id3889_at_idx62249
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule954_id3889_at_idx62249
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule955_id3891_at_idx62325
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule955_id3891_at_idx62325
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %0, %2
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule956_id927_at_idx62401
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule956_id927_at_idx62401
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_MUL %3, %4
+    %1:fpr(<8 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule957_id928_at_idx62489
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule957_id928_at_idx62489
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_MUL %3, %4
+    %1:fpr(<16 x s8>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule958_id929_at_idx62577
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule958_id929_at_idx62577
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_MUL %3, %4
+    %1:fpr(<4 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule959_id930_at_idx62665
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule959_id930_at_idx62665
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_MUL %3, %4
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule960_id931_at_idx62753
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule960_id931_at_idx62753
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLAv2i32_:%[0-9]+]]:fpr64 = MLAv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_MUL %3, %4
+    %1:fpr(<2 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule961_id932_at_idx62841
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule961_id932_at_idx62841
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLAv4i32_:%[0-9]+]]:fpr128 = MLAv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLAv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_MUL %3, %4
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule962_id1272_at_idx62929
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule962_id1272_at_idx62929
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule963_id1274_at_idx63005
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule963_id1274_at_idx63005
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule964_id1276_at_idx63081
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule964_id1276_at_idx63081
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule965_id1332_at_idx63157
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule965_id1332_at_idx63157
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule966_id1334_at_idx63233
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule966_id1334_at_idx63233
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule967_id1336_at_idx63309
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule967_id1336_at_idx63309
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_ADD %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule968_id1759_at_idx63385
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule968_id1759_at_idx63385
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+    ; SELECTED: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ASRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ANYEXT %3(s32)
+    %1:gpr(s64) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule969_id1760_at_idx63459
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule969_id1760_at_idx63459
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY1]], [[SBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ASRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SEXT %3(s32)
+    %1:gpr(s64) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule970_id1758_at_idx63533
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule970_id1758_at_idx63533
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY1]], [[UBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ASRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ZEXT %3(s32)
+    %1:gpr(s64) = G_ASHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule971_id1818_at_idx63607
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule971_id1818_at_idx63607
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+    ; SELECTED: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ANYEXT %3(s32)
+    %1:gpr(s64) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule972_id1819_at_idx63681
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule972_id1819_at_idx63681
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY1]], [[SBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SEXT %3(s32)
+    %1:gpr(s64) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule973_id1817_at_idx63755
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule973_id1817_at_idx63755
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY1]], [[UBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSRVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ZEXT %3(s32)
+    %1:gpr(s64) = G_LSHR %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule974_id1814_at_idx63829
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule974_id1814_at_idx63829
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+    ; SELECTED: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSLVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ANYEXT %3(s32)
+    %1:gpr(s64) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule975_id1815_at_idx63903
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule975_id1815_at_idx63903
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY1]], [[SBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSLVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SEXT %3(s32)
+    %1:gpr(s64) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule976_id1813_at_idx63977
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%2' }
+  - { reg: '$w0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $w0
+
+    ; SELECTED-LABEL: name: test_rule976_id1813_at_idx63977
+    ; SELECTED: liveins: $x0, $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; SELECTED: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; SELECTED: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY1]], [[UBFMXri]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSLVXr]]
+    %3:gpr(s32) = COPY $w0
+    %2:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ZEXT %3(s32)
+    %1:gpr(s64) = G_SHL %2, %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule977_id933_at_idx64051
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule977_id933_at_idx64051
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLSv8i8_:%[0-9]+]]:fpr64 = MLSv8i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv8i8_]]
+    %4:fpr(<8 x s8>) = COPY $d2
+    %3:fpr(<8 x s8>) = COPY $d1
+    %2:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_MUL %3, %4
+    %1:fpr(<8 x s8>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s8>)
+
+...
+---
+name:            test_rule978_id934_at_idx64139
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule978_id934_at_idx64139
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLSv16i8_:%[0-9]+]]:fpr128 = MLSv16i8 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv16i8_]]
+    %4:fpr(<16 x s8>) = COPY $q2
+    %3:fpr(<16 x s8>) = COPY $q1
+    %2:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_MUL %3, %4
+    %1:fpr(<16 x s8>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<16 x s8>)
+
+...
+---
+name:            test_rule979_id935_at_idx64227
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule979_id935_at_idx64227
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLSv4i16_:%[0-9]+]]:fpr64 = MLSv4i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv4i16_]]
+    %4:fpr(<4 x s16>) = COPY $d2
+    %3:fpr(<4 x s16>) = COPY $d1
+    %2:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_MUL %3, %4
+    %1:fpr(<4 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s16>)
+
+...
+---
+name:            test_rule980_id936_at_idx64315
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule980_id936_at_idx64315
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLSv8i16_:%[0-9]+]]:fpr128 = MLSv8i16 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv8i16_]]
+    %4:fpr(<8 x s16>) = COPY $q2
+    %3:fpr(<8 x s16>) = COPY $q1
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_MUL %3, %4
+    %1:fpr(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule981_id937_at_idx64403
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule981_id937_at_idx64403
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MLSv2i32_:%[0-9]+]]:fpr64 = MLSv2i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv2i32_]]
+    %4:fpr(<2 x s32>) = COPY $d2
+    %3:fpr(<2 x s32>) = COPY $d1
+    %2:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_MUL %3, %4
+    %1:fpr(<2 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s32>)
+
+...
+---
+name:            test_rule982_id938_at_idx64491
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$q1', virtual-reg: '%3' }
+  - { reg: '$q2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule982_id938_at_idx64491
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MLSv4i32_:%[0-9]+]]:fpr128 = MLSv4i32 [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MLSv4i32_]]
+    %4:fpr(<4 x s32>) = COPY $q2
+    %3:fpr(<4 x s32>) = COPY $q1
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_MUL %3, %4
+    %1:fpr(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule983_id1314_at_idx64579
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule983_id1314_at_idx64579
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule984_id1316_at_idx64655
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule984_id1316_at_idx64655
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule985_id1318_at_idx64731
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule985_id1318_at_idx64731
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule986_id1362_at_idx64807
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule986_id1362_at_idx64807
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]
+    %3:fpr(<8 x s8>) = COPY $d0
+    %2:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+    %1:fpr(<8 x s16>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<8 x s16>)
+
+...
+---
+name:            test_rule987_id1364_at_idx64883
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule987_id1364_at_idx64883
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]
+    %3:fpr(<4 x s16>) = COPY $d0
+    %2:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+    %1:fpr(<4 x s32>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<4 x s32>)
+
+...
+---
+name:            test_rule988_id1366_at_idx64959
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%2' }
+  - { reg: '$d0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $d0
+
+    ; SELECTED-LABEL: name: test_rule988_id1366_at_idx64959
+    ; SELECTED: liveins: $q0, $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]
+    %3:fpr(<2 x s32>) = COPY $d0
+    %2:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+    %1:fpr(<2 x s64>) = G_SUB %2, %0
+    $noreg = PATCHABLE_RET %1(<2 x s64>)
+
+...
+---
+name:            test_rule989_id431_at_idx65035
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%2' }
+  - { reg: '$h1', virtual-reg: '%3' }
+  - { reg: '$h2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1, $h2
+
+    ; SELECTED-LABEL: name: test_rule989_id431_at_idx65035
+    ; SELECTED: liveins: $h0, $h1, $h2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FNMADDHrrr:%[0-9]+]]:fpr16 = FNMADDHrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDHrrr]]
+    %4:fpr(s16) = COPY $h2
+    %3:fpr(s16) = COPY $h1
+    %2:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FMA %2, %3, %4
+    %1:fpr(s16) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule990_id432_at_idx65123
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+  - { reg: '$s2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule990_id432_at_idx65123
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
+    %4:fpr(s32) = COPY $s2
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FMA %2, %3, %4
+    %1:fpr(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule991_id433_at_idx65211
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+  - { id: 4, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+  - { reg: '$d2', virtual-reg: '%4' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule991_id433_at_idx65211
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
+    %4:fpr(s64) = COPY $d2
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FMA %2, %3, %4
+    %1:fpr(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule992_id419_at_idx65299
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%2' }
+  - { reg: '$h1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule992_id419_at_idx65299
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FNMULHrr:%[0-9]+]]:fpr16 = FNMULHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMULHrr]]
+    %3:fpr(s16) = COPY $h1
+    %2:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FMUL %2, %3
+    %1:fpr(s16) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s16)
+
+...
+---
+name:            test_rule993_id420_at_idx65375
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%2' }
+  - { reg: '$s1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule993_id420_at_idx65375
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMULSrr]]
+    %3:fpr(s32) = COPY $s1
+    %2:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FMUL %2, %3
+    %1:fpr(s32) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s32)
+
+...
+---
+name:            test_rule994_id421_at_idx65451
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%2' }
+  - { reg: '$d1', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule994_id421_at_idx65451
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNMULDrr]]
+    %3:fpr(s64) = COPY $d1
+    %2:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FMUL %2, %3
+    %1:fpr(s64) = G_FNEG %0
+    $noreg = PATCHABLE_RET %1(s64)
+
+...
+---
+name:            test_rule995_id3669_at_idx65527
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+  - { reg: '$x2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1, $x2
+
+    ; SELECTED-LABEL: name: test_rule995_id3669_at_idx65527
+    ; SELECTED: liveins: $x0, $x1, $x2
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x2
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY2]], [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASX]]
+    %3:gpr(p0) = COPY $x2
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule996_id3670_at_idx65606
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+  - { reg: '$x2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1, $x2
+
+    ; SELECTED-LABEL: name: test_rule996_id3670_at_idx65606
+    ; SELECTED: liveins: $x0, $x1, $x2
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x2
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[CASAX:%[0-9]+]]:gpr64 = CASAX [[COPY2]], [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASAX]]
+    %3:gpr(p0) = COPY $x2
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule997_id3671_at_idx65685
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+  - { reg: '$x2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1, $x2
+
+    ; SELECTED-LABEL: name: test_rule997_id3671_at_idx65685
+    ; SELECTED: liveins: $x0, $x1, $x2
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x2
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[CASLX:%[0-9]+]]:gpr64 = CASLX [[COPY2]], [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASLX]]
+    %3:gpr(p0) = COPY $x2
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule998_id3672_at_idx65764
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+  - { reg: '$x2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1, $x2
+
+    ; SELECTED-LABEL: name: test_rule998_id3672_at_idx65764
+    ; SELECTED: liveins: $x0, $x1, $x2
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x2
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[CASALX:%[0-9]+]]:gpr64 = CASALX [[COPY2]], [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALX]]
+    %3:gpr(p0) = COPY $x2
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule999_id3673_at_idx65843
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+  - { reg: '$x2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1, $x2
+
+    ; SELECTED-LABEL: name: test_rule999_id3673_at_idx65843
+    ; SELECTED: liveins: $x0, $x1, $x2
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x2
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[CASALX:%[0-9]+]]:gpr64 = CASALX [[COPY2]], [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALX]]
+    %3:gpr(p0) = COPY $x2
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1000_id3674_at_idx65922
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1000_id3674_at_idx65922
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY2]], [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1001_id3675_at_idx66001
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1001_id3675_at_idx66001
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASAW:%[0-9]+]]:gpr32 = CASAW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASAW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1002_id3676_at_idx66080
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1002_id3676_at_idx66080
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASLW:%[0-9]+]]:gpr32 = CASLW [[COPY2]], [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASLW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1003_id3677_at_idx66159
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1003_id3677_at_idx66159
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1004_id3678_at_idx66238
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1004_id3678_at_idx66238
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1005_id3679_at_idx66317
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1005_id3679_at_idx66317
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY2]], [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1006_id3680_at_idx66396
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1006_id3680_at_idx66396
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASAW:%[0-9]+]]:gpr32 = CASAW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASAW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1007_id3681_at_idx66475
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1007_id3681_at_idx66475
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASLW:%[0-9]+]]:gpr32 = CASLW [[COPY2]], [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASLW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1008_id3682_at_idx66554
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1008_id3682_at_idx66554
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1009_id3683_at_idx66633
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1009_id3683_at_idx66633
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1010_id3684_at_idx66712
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1010_id3684_at_idx66712
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY2]], [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1011_id3685_at_idx66791
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1011_id3685_at_idx66791
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASAW:%[0-9]+]]:gpr32 = CASAW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASAW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1012_id3686_at_idx66870
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1012_id3686_at_idx66870
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASLW:%[0-9]+]]:gpr32 = CASLW [[COPY2]], [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASLW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1013_id3687_at_idx66949
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1013_id3687_at_idx66949
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1014_id3688_at_idx67028
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+  - { reg: '$x0', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $x0
+
+    ; SELECTED-LABEL: name: test_rule1014_id3688_at_idx67028
+    ; SELECTED: liveins: $w0, $w1, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[CASALW:%[0-9]+]]:gpr32 = CASALW [[COPY2]], [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[CASALW]]
+    %3:gpr(p0) = COPY $x0
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1015_id3489_at_idx67107
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1015_id3489_at_idx67107
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1016_id3490_at_idx67174
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1016_id3490_at_idx67174
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDADDAX:%[0-9]+]]:gpr64 = LDADDAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1017_id3491_at_idx67241
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1017_id3491_at_idx67241
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDADDLX:%[0-9]+]]:gpr64 = LDADDLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1018_id3492_at_idx67308
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1018_id3492_at_idx67308
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDADDALX:%[0-9]+]]:gpr64 = LDADDALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1019_id3493_at_idx67375
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1019_id3493_at_idx67375
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDADDALX:%[0-9]+]]:gpr64 = LDADDALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1020_id3494_at_idx67442
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1020_id3494_at_idx67442
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1021_id3495_at_idx67509
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1021_id3495_at_idx67509
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1022_id3496_at_idx67576
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1022_id3496_at_idx67576
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1023_id3497_at_idx67643
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1023_id3497_at_idx67643
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1024_id3498_at_idx67710
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1024_id3498_at_idx67710
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1025_id3499_at_idx67777
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1025_id3499_at_idx67777
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1026_id3500_at_idx67844
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1026_id3500_at_idx67844
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1027_id3501_at_idx67911
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1027_id3501_at_idx67911
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1028_id3502_at_idx67978
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1028_id3502_at_idx67978
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1029_id3503_at_idx68045
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1029_id3503_at_idx68045
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1030_id3504_at_idx68112
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1030_id3504_at_idx68112
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1031_id3505_at_idx68179
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1031_id3505_at_idx68179
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1032_id3506_at_idx68246
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1032_id3506_at_idx68246
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1033_id3507_at_idx68313
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1033_id3507_at_idx68313
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1034_id3508_at_idx68380
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1034_id3508_at_idx68380
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1035_id3709_at_idx68447
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1035_id3709_at_idx68447
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDCLRX:%[0-9]+]]:gpr64 = LDCLRX [[ORNXrr]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1036_id3710_at_idx68533
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1036_id3710_at_idx68533
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDCLRAX:%[0-9]+]]:gpr64 = LDCLRAX [[ORNXrr]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1037_id3711_at_idx68619
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1037_id3711_at_idx68619
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDCLRLX:%[0-9]+]]:gpr64 = LDCLRLX [[ORNXrr]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1038_id3712_at_idx68705
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1038_id3712_at_idx68705
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALX:%[0-9]+]]:gpr64 = LDCLRALX [[ORNXrr]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1039_id3713_at_idx68791
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1039_id3713_at_idx68791
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALX:%[0-9]+]]:gpr64 = LDCLRALX [[ORNXrr]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1040_id3714_at_idx68877
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1040_id3714_at_idx68877
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRW:%[0-9]+]]:gpr32 = LDCLRW [[ORNWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1041_id3715_at_idx68963
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1041_id3715_at_idx68963
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1042_id3716_at_idx69049
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1042_id3716_at_idx69049
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRLW:%[0-9]+]]:gpr32 = LDCLRLW [[ORNWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1043_id3717_at_idx69135
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1043_id3717_at_idx69135
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1044_id3718_at_idx69221
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1044_id3718_at_idx69221
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1045_id3719_at_idx69307
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1045_id3719_at_idx69307
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRW:%[0-9]+]]:gpr32 = LDCLRW [[ORNWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1046_id3720_at_idx69393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1046_id3720_at_idx69393
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1047_id3721_at_idx69479
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1047_id3721_at_idx69479
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRLW:%[0-9]+]]:gpr32 = LDCLRLW [[ORNWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1048_id3722_at_idx69565
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1048_id3722_at_idx69565
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1049_id3723_at_idx69651
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1049_id3723_at_idx69651
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1050_id3724_at_idx69737
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1050_id3724_at_idx69737
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRW:%[0-9]+]]:gpr32 = LDCLRW [[ORNWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1051_id3725_at_idx69823
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1051_id3725_at_idx69823
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1052_id3726_at_idx69909
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1052_id3726_at_idx69909
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRLW:%[0-9]+]]:gpr32 = LDCLRLW [[ORNWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1053_id3727_at_idx69995
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1053_id3727_at_idx69995
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1054_id3728_at_idx70081
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1054_id3728_at_idx70081
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDCLRALW:%[0-9]+]]:gpr32 = LDCLRALW [[ORNWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDCLRALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1055_id3569_at_idx70167
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1055_id3569_at_idx70167
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMAXX:%[0-9]+]]:gpr64 = LDSMAXX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1056_id3570_at_idx70234
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1056_id3570_at_idx70234
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMAXAX:%[0-9]+]]:gpr64 = LDSMAXAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1057_id3571_at_idx70301
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1057_id3571_at_idx70301
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMAXLX:%[0-9]+]]:gpr64 = LDSMAXLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1058_id3572_at_idx70368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1058_id3572_at_idx70368
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMAXALX:%[0-9]+]]:gpr64 = LDSMAXALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1059_id3573_at_idx70435
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1059_id3573_at_idx70435
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMAXALX:%[0-9]+]]:gpr64 = LDSMAXALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1060_id3574_at_idx70502
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1060_id3574_at_idx70502
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXW:%[0-9]+]]:gpr32 = LDSMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1061_id3575_at_idx70569
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1061_id3575_at_idx70569
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXAW:%[0-9]+]]:gpr32 = LDSMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1062_id3576_at_idx70636
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1062_id3576_at_idx70636
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXLW:%[0-9]+]]:gpr32 = LDSMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1063_id3577_at_idx70703
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1063_id3577_at_idx70703
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1064_id3578_at_idx70770
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1064_id3578_at_idx70770
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1065_id3579_at_idx70837
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1065_id3579_at_idx70837
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXW:%[0-9]+]]:gpr32 = LDSMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1066_id3580_at_idx70904
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1066_id3580_at_idx70904
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXAW:%[0-9]+]]:gpr32 = LDSMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1067_id3581_at_idx70971
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1067_id3581_at_idx70971
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXLW:%[0-9]+]]:gpr32 = LDSMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1068_id3582_at_idx71038
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1068_id3582_at_idx71038
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1069_id3583_at_idx71105
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1069_id3583_at_idx71105
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1070_id3584_at_idx71172
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1070_id3584_at_idx71172
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXW:%[0-9]+]]:gpr32 = LDSMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1071_id3585_at_idx71239
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1071_id3585_at_idx71239
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXAW:%[0-9]+]]:gpr32 = LDSMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1072_id3586_at_idx71306
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1072_id3586_at_idx71306
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXLW:%[0-9]+]]:gpr32 = LDSMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1073_id3587_at_idx71373
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1073_id3587_at_idx71373
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1074_id3588_at_idx71440
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1074_id3588_at_idx71440
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1075_id3589_at_idx71507
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1075_id3589_at_idx71507
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMINX:%[0-9]+]]:gpr64 = LDSMINX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1076_id3590_at_idx71574
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1076_id3590_at_idx71574
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMINAX:%[0-9]+]]:gpr64 = LDSMINAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1077_id3591_at_idx71641
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1077_id3591_at_idx71641
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMINLX:%[0-9]+]]:gpr64 = LDSMINLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1078_id3592_at_idx71708
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1078_id3592_at_idx71708
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMINALX:%[0-9]+]]:gpr64 = LDSMINALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1079_id3593_at_idx71775
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1079_id3593_at_idx71775
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSMINALX:%[0-9]+]]:gpr64 = LDSMINALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1080_id3594_at_idx71842
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1080_id3594_at_idx71842
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINW:%[0-9]+]]:gpr32 = LDSMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1081_id3595_at_idx71909
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1081_id3595_at_idx71909
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINAW:%[0-9]+]]:gpr32 = LDSMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1082_id3596_at_idx71976
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1082_id3596_at_idx71976
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINLW:%[0-9]+]]:gpr32 = LDSMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1083_id3597_at_idx72043
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1083_id3597_at_idx72043
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1084_id3598_at_idx72110
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1084_id3598_at_idx72110
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1085_id3599_at_idx72177
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1085_id3599_at_idx72177
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINW:%[0-9]+]]:gpr32 = LDSMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1086_id3600_at_idx72244
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1086_id3600_at_idx72244
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINAW:%[0-9]+]]:gpr32 = LDSMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1087_id3601_at_idx72311
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1087_id3601_at_idx72311
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINLW:%[0-9]+]]:gpr32 = LDSMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1088_id3602_at_idx72378
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1088_id3602_at_idx72378
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1089_id3603_at_idx72445
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1089_id3603_at_idx72445
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1090_id3604_at_idx72512
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1090_id3604_at_idx72512
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINW:%[0-9]+]]:gpr32 = LDSMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1091_id3605_at_idx72579
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1091_id3605_at_idx72579
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINAW:%[0-9]+]]:gpr32 = LDSMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1092_id3606_at_idx72646
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1092_id3606_at_idx72646
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINLW:%[0-9]+]]:gpr32 = LDSMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1093_id3607_at_idx72713
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1093_id3607_at_idx72713
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1094_id3608_at_idx72780
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1094_id3608_at_idx72780
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1095_id3509_at_idx72847
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1095_id3509_at_idx72847
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSETX:%[0-9]+]]:gpr64 = LDSETX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1096_id3510_at_idx72914
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1096_id3510_at_idx72914
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSETAX:%[0-9]+]]:gpr64 = LDSETAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1097_id3511_at_idx72981
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1097_id3511_at_idx72981
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSETLX:%[0-9]+]]:gpr64 = LDSETLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1098_id3512_at_idx73048
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1098_id3512_at_idx73048
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSETALX:%[0-9]+]]:gpr64 = LDSETALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1099_id3513_at_idx73115
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1099_id3513_at_idx73115
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDSETALX:%[0-9]+]]:gpr64 = LDSETALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1100_id3514_at_idx73182
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1100_id3514_at_idx73182
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETW:%[0-9]+]]:gpr32 = LDSETW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1101_id3515_at_idx73249
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1101_id3515_at_idx73249
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETAW:%[0-9]+]]:gpr32 = LDSETAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1102_id3516_at_idx73316
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1102_id3516_at_idx73316
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1103_id3517_at_idx73383
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1103_id3517_at_idx73383
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1104_id3518_at_idx73450
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1104_id3518_at_idx73450
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1105_id3519_at_idx73517
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1105_id3519_at_idx73517
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETW:%[0-9]+]]:gpr32 = LDSETW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1106_id3520_at_idx73584
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1106_id3520_at_idx73584
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETAW:%[0-9]+]]:gpr32 = LDSETAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1107_id3521_at_idx73651
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1107_id3521_at_idx73651
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1108_id3522_at_idx73718
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1108_id3522_at_idx73718
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1109_id3523_at_idx73785
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1109_id3523_at_idx73785
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1110_id3524_at_idx73852
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1110_id3524_at_idx73852
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETW:%[0-9]+]]:gpr32 = LDSETW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1111_id3525_at_idx73919
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1111_id3525_at_idx73919
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETAW:%[0-9]+]]:gpr32 = LDSETAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1112_id3526_at_idx73986
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1112_id3526_at_idx73986
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1113_id3527_at_idx74053
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1113_id3527_at_idx74053
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1114_id3528_at_idx74120
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1114_id3528_at_idx74120
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDSETALW:%[0-9]+]]:gpr32 = LDSETALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDSETALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1115_id3689_at_idx74187
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1115_id3689_at_idx74187
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBXrr]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1116_id3690_at_idx74273
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1116_id3690_at_idx74273
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDADDAX:%[0-9]+]]:gpr64 = LDADDAX [[SUBXrr]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1117_id3691_at_idx74359
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1117_id3691_at_idx74359
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDADDLX:%[0-9]+]]:gpr64 = LDADDLX [[SUBXrr]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1118_id3692_at_idx74445
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1118_id3692_at_idx74445
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDADDALX:%[0-9]+]]:gpr64 = LDADDALX [[SUBXrr]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1119_id3693_at_idx74531
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1119_id3693_at_idx74531
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr $xzr, [[COPY1]]
+    ; SELECTED: [[LDADDALX:%[0-9]+]]:gpr64 = LDADDALX [[SUBXrr]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1120_id3694_at_idx74617
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1120_id3694_at_idx74617
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[SUBWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1121_id3695_at_idx74703
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1121_id3695_at_idx74703
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[SUBWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1122_id3696_at_idx74789
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1122_id3696_at_idx74789
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[SUBWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1123_id3697_at_idx74875
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1123_id3697_at_idx74875
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1124_id3698_at_idx74961
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1124_id3698_at_idx74961
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1125_id3699_at_idx75047
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1125_id3699_at_idx75047
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[SUBWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1126_id3700_at_idx75133
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1126_id3700_at_idx75133
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[SUBWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1127_id3701_at_idx75219
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1127_id3701_at_idx75219
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[SUBWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1128_id3702_at_idx75305
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1128_id3702_at_idx75305
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1129_id3703_at_idx75391
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1129_id3703_at_idx75391
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1130_id3704_at_idx75477
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1130_id3704_at_idx75477
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDW:%[0-9]+]]:gpr32 = LDADDW [[SUBWrr]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1131_id3705_at_idx75563
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1131_id3705_at_idx75563
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDAW:%[0-9]+]]:gpr32 = LDADDAW [[SUBWrr]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1132_id3706_at_idx75649
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1132_id3706_at_idx75649
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDLW:%[0-9]+]]:gpr32 = LDADDLW [[SUBWrr]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1133_id3707_at_idx75735
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1133_id3707_at_idx75735
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1134_id3708_at_idx75821
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1134_id3708_at_idx75821
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr $wzr, [[COPY1]]
+    ; SELECTED: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[SUBWrr]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDADDALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1135_id3609_at_idx75907
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1135_id3609_at_idx75907
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMAXX:%[0-9]+]]:gpr64 = LDUMAXX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1136_id3610_at_idx75974
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1136_id3610_at_idx75974
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMAXAX:%[0-9]+]]:gpr64 = LDUMAXAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1137_id3611_at_idx76041
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1137_id3611_at_idx76041
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMAXLX:%[0-9]+]]:gpr64 = LDUMAXLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1138_id3612_at_idx76108
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1138_id3612_at_idx76108
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMAXALX:%[0-9]+]]:gpr64 = LDUMAXALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1139_id3613_at_idx76175
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1139_id3613_at_idx76175
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMAXALX:%[0-9]+]]:gpr64 = LDUMAXALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1140_id3614_at_idx76242
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1140_id3614_at_idx76242
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXW:%[0-9]+]]:gpr32 = LDUMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1141_id3615_at_idx76309
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1141_id3615_at_idx76309
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXAW:%[0-9]+]]:gpr32 = LDUMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1142_id3616_at_idx76376
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1142_id3616_at_idx76376
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXLW:%[0-9]+]]:gpr32 = LDUMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1143_id3617_at_idx76443
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1143_id3617_at_idx76443
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1144_id3618_at_idx76510
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1144_id3618_at_idx76510
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1145_id3619_at_idx76577
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1145_id3619_at_idx76577
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXW:%[0-9]+]]:gpr32 = LDUMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1146_id3620_at_idx76644
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1146_id3620_at_idx76644
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXAW:%[0-9]+]]:gpr32 = LDUMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1147_id3621_at_idx76711
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1147_id3621_at_idx76711
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXLW:%[0-9]+]]:gpr32 = LDUMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1148_id3622_at_idx76778
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1148_id3622_at_idx76778
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1149_id3623_at_idx76845
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1149_id3623_at_idx76845
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1150_id3624_at_idx76912
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1150_id3624_at_idx76912
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXW:%[0-9]+]]:gpr32 = LDUMAXW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1151_id3625_at_idx76979
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1151_id3625_at_idx76979
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXAW:%[0-9]+]]:gpr32 = LDUMAXAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1152_id3626_at_idx77046
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1152_id3626_at_idx77046
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXLW:%[0-9]+]]:gpr32 = LDUMAXLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1153_id3627_at_idx77113
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1153_id3627_at_idx77113
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1154_id3628_at_idx77180
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1154_id3628_at_idx77180
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMAXALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1155_id3629_at_idx77247
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1155_id3629_at_idx77247
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMINX:%[0-9]+]]:gpr64 = LDUMINX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1156_id3630_at_idx77314
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1156_id3630_at_idx77314
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMINAX:%[0-9]+]]:gpr64 = LDUMINAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1157_id3631_at_idx77381
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1157_id3631_at_idx77381
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMINLX:%[0-9]+]]:gpr64 = LDUMINLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1158_id3632_at_idx77448
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1158_id3632_at_idx77448
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMINALX:%[0-9]+]]:gpr64 = LDUMINALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1159_id3633_at_idx77515
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1159_id3633_at_idx77515
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDUMINALX:%[0-9]+]]:gpr64 = LDUMINALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1160_id3634_at_idx77582
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1160_id3634_at_idx77582
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINW:%[0-9]+]]:gpr32 = LDUMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1161_id3635_at_idx77649
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1161_id3635_at_idx77649
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINAW:%[0-9]+]]:gpr32 = LDUMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1162_id3636_at_idx77716
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1162_id3636_at_idx77716
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINLW:%[0-9]+]]:gpr32 = LDUMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1163_id3637_at_idx77783
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1163_id3637_at_idx77783
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1164_id3638_at_idx77850
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1164_id3638_at_idx77850
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1165_id3639_at_idx77917
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1165_id3639_at_idx77917
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINW:%[0-9]+]]:gpr32 = LDUMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1166_id3640_at_idx77984
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1166_id3640_at_idx77984
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINAW:%[0-9]+]]:gpr32 = LDUMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1167_id3641_at_idx78051
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1167_id3641_at_idx78051
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINLW:%[0-9]+]]:gpr32 = LDUMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1168_id3642_at_idx78118
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1168_id3642_at_idx78118
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1169_id3643_at_idx78185
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1169_id3643_at_idx78185
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1170_id3644_at_idx78252
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1170_id3644_at_idx78252
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINW:%[0-9]+]]:gpr32 = LDUMINW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1171_id3645_at_idx78319
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1171_id3645_at_idx78319
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINAW:%[0-9]+]]:gpr32 = LDUMINAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1172_id3646_at_idx78386
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1172_id3646_at_idx78386
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINLW:%[0-9]+]]:gpr32 = LDUMINLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1173_id3647_at_idx78453
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1173_id3647_at_idx78453
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1174_id3648_at_idx78520
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1174_id3648_at_idx78520
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDUMINALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1175_id3649_at_idx78587
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1175_id3649_at_idx78587
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1176_id3650_at_idx78654
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1176_id3650_at_idx78654
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SWPAX:%[0-9]+]]:gpr64 = SWPAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1177_id3651_at_idx78721
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1177_id3651_at_idx78721
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SWPLX:%[0-9]+]]:gpr64 = SWPLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1178_id3652_at_idx78788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1178_id3652_at_idx78788
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SWPALX:%[0-9]+]]:gpr64 = SWPALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1179_id3653_at_idx78855
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1179_id3653_at_idx78855
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SWPALX:%[0-9]+]]:gpr64 = SWPALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1180_id3654_at_idx78922
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1180_id3654_at_idx78922
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPW:%[0-9]+]]:gpr32 = SWPW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1181_id3655_at_idx78989
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1181_id3655_at_idx78989
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPAW:%[0-9]+]]:gpr32 = SWPAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1182_id3656_at_idx79056
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1182_id3656_at_idx79056
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPLW:%[0-9]+]]:gpr32 = SWPLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1183_id3657_at_idx79123
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1183_id3657_at_idx79123
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1184_id3658_at_idx79190
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1184_id3658_at_idx79190
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1185_id3659_at_idx79257
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1185_id3659_at_idx79257
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPW:%[0-9]+]]:gpr32 = SWPW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1186_id3660_at_idx79324
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1186_id3660_at_idx79324
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPAW:%[0-9]+]]:gpr32 = SWPAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1187_id3661_at_idx79391
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1187_id3661_at_idx79391
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPLW:%[0-9]+]]:gpr32 = SWPLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1188_id3662_at_idx79458
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1188_id3662_at_idx79458
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1189_id3663_at_idx79525
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1189_id3663_at_idx79525
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1190_id3664_at_idx79592
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1190_id3664_at_idx79592
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPW:%[0-9]+]]:gpr32 = SWPW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1191_id3665_at_idx79659
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1191_id3665_at_idx79659
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPAW:%[0-9]+]]:gpr32 = SWPAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1192_id3666_at_idx79726
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1192_id3666_at_idx79726
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPLW:%[0-9]+]]:gpr32 = SWPLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1193_id3667_at_idx79793
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1193_id3667_at_idx79793
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1194_id3668_at_idx79860
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1194_id3668_at_idx79860
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SWPALW:%[0-9]+]]:gpr32 = SWPALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[SWPALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1195_id3529_at_idx79927
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1195_id3529_at_idx79927
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDEORX:%[0-9]+]]:gpr64 = LDEORX [[COPY1]], [[COPY]] :: (load store monotonic 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1196_id3530_at_idx79994
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1196_id3530_at_idx79994
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDEORAX:%[0-9]+]]:gpr64 = LDEORAX [[COPY1]], [[COPY]] :: (load store acquire 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORAX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1197_id3531_at_idx80061
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1197_id3531_at_idx80061
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDEORLX:%[0-9]+]]:gpr64 = LDEORLX [[COPY1]], [[COPY]] :: (load store release 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORLX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1198_id3532_at_idx80128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1198_id3532_at_idx80128
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDEORALX:%[0-9]+]]:gpr64 = LDEORALX [[COPY1]], [[COPY]] :: (load store acq_rel 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1199_id3533_at_idx80195
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1199_id3533_at_idx80195
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LDEORALX:%[0-9]+]]:gpr64 = LDEORALX [[COPY1]], [[COPY]] :: (load store seq_cst 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALX]]
+    %2:gpr(p0) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1200_id3534_at_idx80262
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1200_id3534_at_idx80262
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORW:%[0-9]+]]:gpr32 = LDEORW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1201_id3535_at_idx80329
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1201_id3535_at_idx80329
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORAW:%[0-9]+]]:gpr32 = LDEORAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1202_id3536_at_idx80396
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1202_id3536_at_idx80396
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORLW:%[0-9]+]]:gpr32 = LDEORLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1203_id3537_at_idx80463
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1203_id3537_at_idx80463
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1204_id3538_at_idx80530
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1204_id3538_at_idx80530
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1205_id3539_at_idx80597
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1205_id3539_at_idx80597
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORW:%[0-9]+]]:gpr32 = LDEORW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1206_id3540_at_idx80664
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1206_id3540_at_idx80664
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORAW:%[0-9]+]]:gpr32 = LDEORAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1207_id3541_at_idx80731
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1207_id3541_at_idx80731
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORLW:%[0-9]+]]:gpr32 = LDEORLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1208_id3542_at_idx80798
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1208_id3542_at_idx80798
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1209_id3543_at_idx80865
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1209_id3543_at_idx80865
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1210_id3544_at_idx80932
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1210_id3544_at_idx80932
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORW:%[0-9]+]]:gpr32 = LDEORW [[COPY1]], [[COPY]] :: (load store monotonic 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1211_id3545_at_idx80999
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1211_id3545_at_idx80999
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORAW:%[0-9]+]]:gpr32 = LDEORAW [[COPY1]], [[COPY]] :: (load store acquire 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORAW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1212_id3546_at_idx81066
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1212_id3546_at_idx81066
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORLW:%[0-9]+]]:gpr32 = LDEORLW [[COPY1]], [[COPY]] :: (load store release 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORLW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1213_id3547_at_idx81133
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1213_id3547_at_idx81133
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store acq_rel 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1214_id3548_at_idx81200
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$x0', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1214_id3548_at_idx81200
+    ; SELECTED: liveins: $w0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[COPY1]], [[COPY]] :: (load store seq_cst 4)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDEORALW]]
+    %2:gpr(p0) = COPY $x0
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1215_id359_at_idx81267
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1215_id359_at_idx81267
+    ; SELECTED: [[FMOVH0_:%[0-9]+]]:fpr16 = FMOVH0
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMOVH0_]]
+    %0:fpr(s16) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1216_id360_at_idx81302
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1216_id360_at_idx81302
+    ; SELECTED: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMOVS0_]]
+    %0:fpr(s32) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1217_id361_at_idx81335
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1217_id361_at_idx81335
+    ; SELECTED: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMOVD0_]]
+    %0:fpr(s64) = G_FCONSTANT double 0.000000e+00
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1218_id2957_at_idx81368
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1218_id2957_at_idx81368
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1219_id2958_at_idx81404
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1219_id2958_at_idx81404
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1220_id2959_at_idx81440
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1220_id2959_at_idx81440
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1221_id2960_at_idx81476
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1221_id2960_at_idx81476
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRQui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1222_id2961_at_idx81512
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1222_id2961_at_idx81512
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1223_id2962_at_idx81548
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1223_id2962_at_idx81548
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1224_id2963_at_idx81584
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1224_id2963_at_idx81584
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1225_id2964_at_idx81620
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1225_id2964_at_idx81620
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8)
+    ; SELECTED: $noreg = PATCHABLE_RET [[LDRDui]]
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1226_id2965_at_idx81656
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1226_id2965_at_idx81656
+    ; SELECTED: liveins: $q0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: STRQui [[COPY1]], [[COPY]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<16 x s8>) = COPY $q0
+    G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1227_id2966_at_idx81688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1227_id2966_at_idx81688
+    ; SELECTED: liveins: $q0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: STRQui [[COPY1]], [[COPY]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<8 x s16>) = COPY $q0
+    G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1228_id2967_at_idx81720
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1228_id2967_at_idx81720
+    ; SELECTED: liveins: $q0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: STRQui [[COPY1]], [[COPY]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<4 x s32>) = COPY $q0
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1229_id2968_at_idx81752
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%0' }
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $x0
+
+    ; SELECTED-LABEL: name: test_rule1229_id2968_at_idx81752
+    ; SELECTED: liveins: $q0, $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: STRQui [[COPY1]], [[COPY]], 0 :: (store 16)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x0
+    %0:fpr(<2 x s64>) = COPY $q0
+    G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1230_id2969_at_idx81784
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1230_id2969_at_idx81784
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
+    ; SELECTED: ST1Onev8b [[COPY2]], [[COPY]] :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(<8 x s8>) = COPY $x0
+    G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1231_id2970_at_idx81816
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1231_id2970_at_idx81816
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
+    ; SELECTED: ST1Onev4h [[COPY2]], [[COPY]] :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(<4 x s16>) = COPY $x0
+    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1232_id2971_at_idx81848
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1232_id2971_at_idx81848
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
+    ; SELECTED: ST1Onev2s [[COPY2]], [[COPY]] :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(<2 x s32>) = COPY $x0
+    G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1233_id2972_at_idx81880
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1233_id2972_at_idx81880
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: STRXui [[COPY1]], [[COPY]], 0 :: (store 8)
+    ; SELECTED: $noreg = PATCHABLE_RET
+    %1:gpr(p0) = COPY $x1
+    %0:gpr(s64) = COPY $x0
+    G_STORE %0(s64), %1(p0) :: (store 8)
+    $noreg = PATCHABLE_RET
+
+...
+---
+name:            test_rule1234_id425_at_idx81912
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+  - { reg: '$h2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1, $h2
+
+    ; SELECTED-LABEL: name: test_rule1234_id425_at_idx81912
+    ; SELECTED: liveins: $h0, $h1, $h2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FMADDHrrr:%[0-9]+]]:fpr16 = FMADDHrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMADDHrrr]]
+    %3:fpr(s16) = COPY $h2
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1235_id426_at_idx81963
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+  - { reg: '$s2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1, $s2
+
+    ; SELECTED-LABEL: name: test_rule1235_id426_at_idx81963
+    ; SELECTED: liveins: $s0, $s1, $s2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMADDSrrr]]
+    %3:fpr(s32) = COPY $s2
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1236_id427_at_idx82014
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+  - { reg: '$d2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule1236_id427_at_idx82014
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMADDDrrr:%[0-9]+]]:fpr64 = FMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMADDDrrr]]
+    %3:fpr(s64) = COPY $d2
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1237_id892_at_idx82065
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+  - { reg: '$d2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule1237_id892_at_idx82065
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMLAv4f16_:%[0-9]+]]:fpr64 = FMLAv4f16 [[COPY]], [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLAv4f16_]]
+    %3:fpr(<4 x s16>) = COPY $d2
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1238_id893_at_idx82133
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule1238_id893_at_idx82133
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLAv8f16_:%[0-9]+]]:fpr128 = FMLAv8f16 [[COPY]], [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLAv8f16_]]
+    %3:fpr(<8 x s16>) = COPY $q2
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1239_id894_at_idx82201
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+  - { reg: '$d2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1, $d2
+
+    ; SELECTED-LABEL: name: test_rule1239_id894_at_idx82201
+    ; SELECTED: liveins: $d0, $d1, $d2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
+    %3:fpr(<2 x s32>) = COPY $d2
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1240_id895_at_idx82269
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule1240_id895_at_idx82269
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
+    %3:fpr(<4 x s32>) = COPY $q2
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1241_id896_at_idx82337
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+  - { id: 3, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+  - { reg: '$q2', virtual-reg: '%3' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1, $q2
+
+    ; SELECTED-LABEL: name: test_rule1241_id896_at_idx82337
+    ; SELECTED: liveins: $q0, $q1, $q2
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
+    %3:fpr(<2 x s64>) = COPY $q2
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1242_id26_at_idx82405
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1242_id26_at_idx82405
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1243_id27_at_idx82446
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1243_id27_at_idx82446
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1244_id751_at_idx82487
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1244_id751_at_idx82487
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1245_id752_at_idx82530
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1245_id752_at_idx82530
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1246_id753_at_idx82573
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1246_id753_at_idx82573
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1247_id754_at_idx82616
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1247_id754_at_idx82616
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1248_id755_at_idx82659
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1248_id755_at_idx82659
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDv2i32_:%[0-9]+]]:fpr64 = ADDv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1249_id756_at_idx82702
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1249_id756_at_idx82702
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDv4i32_:%[0-9]+]]:fpr128 = ADDv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1250_id757_at_idx82745
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1250_id757_at_idx82745
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1251_id1176_at_idx82788
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1251_id1176_at_idx82788
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ADDv1i64_:%[0-9]+]]:fpr64 = ADDv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ADDv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_ADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1252_id86_at_idx82831
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1252_id86_at_idx82831
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1253_id87_at_idx82872
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1253_id87_at_idx82872
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1254_id1162_at_idx82913
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1254_id1162_at_idx82913
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1255_id1163_at_idx82956
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1255_id1163_at_idx82956
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1256_id1751_at_idx82999
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1256_id1751_at_idx82999
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv8i8_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1257_id1752_at_idx83042
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1257_id1752_at_idx83042
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv8i8_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1258_id1753_at_idx83085
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1258_id1753_at_idx83085
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv8i8_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1259_id1754_at_idx83128
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1259_id1754_at_idx83128
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv16i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1260_id1755_at_idx83171
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1260_id1755_at_idx83171
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv16i8_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1261_id1756_at_idx83214
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1261_id1756_at_idx83214
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ANDv16i8_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_AND %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1262_id52_at_idx83257
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1262_id52_at_idx83257
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ASRVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_ASHR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1263_id398_at_idx83298
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule1263_id398_at_idx83298
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FADDHrr:%[0-9]+]]:fpr16 = FADDHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDHrr]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1264_id399_at_idx83341
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule1264_id399_at_idx83341
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDSrr]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1265_id400_at_idx83384
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1265_id400_at_idx83384
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDDrr]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1266_id827_at_idx83427
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1266_id827_at_idx83427
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1267_id828_at_idx83470
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1267_id828_at_idx83470
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1268_id829_at_idx83513
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1268_id829_at_idx83513
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1269_id830_at_idx83556
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1269_id830_at_idx83556
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1270_id831_at_idx83599
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1270_id831_at_idx83599
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FADDv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FADD %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1271_id401_at_idx83642
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule1271_id401_at_idx83642
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FDIVHrr:%[0-9]+]]:fpr16 = FDIVHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVHrr]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1272_id402_at_idx83685
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule1272_id402_at_idx83685
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVSrr]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1273_id403_at_idx83728
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1273_id403_at_idx83728
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVDrr]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1274_id847_at_idx83771
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1274_id847_at_idx83771
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FDIVv4f16_:%[0-9]+]]:fpr64 = FDIVv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1275_id848_at_idx83814
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1275_id848_at_idx83814
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FDIVv8f16_:%[0-9]+]]:fpr128 = FDIVv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1276_id849_at_idx83857
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1276_id849_at_idx83857
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1277_id850_at_idx83900
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1277_id850_at_idx83900
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1278_id851_at_idx83943
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1278_id851_at_idx83943
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FDIV %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1279_id416_at_idx83986
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule1279_id416_at_idx83986
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FMULHrr:%[0-9]+]]:fpr16 = FMULHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULHrr]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1280_id417_at_idx84029
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule1280_id417_at_idx84029
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULSrr]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1281_id418_at_idx84072
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1281_id418_at_idx84072
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULDrr]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1282_id907_at_idx84115
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1282_id907_at_idx84115
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULv4f16_:%[0-9]+]]:fpr64 = FMULv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1283_id908_at_idx84158
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1283_id908_at_idx84158
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULv8f16_:%[0-9]+]]:fpr128 = FMULv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1284_id909_at_idx84201
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1284_id909_at_idx84201
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1285_id910_at_idx84244
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1285_id910_at_idx84244
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1286_id911_at_idx84287
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1286_id911_at_idx84287
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FMULv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FMUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1287_id422_at_idx84330
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+  - { reg: '$h1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $h0, $h1
+
+    ; SELECTED-LABEL: name: test_rule1287_id422_at_idx84330
+    ; SELECTED: liveins: $h0, $h1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FSUBHrr:%[0-9]+]]:fpr16 = FSUBHrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBHrr]]
+    %2:fpr(s16) = COPY $h1
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1288_id423_at_idx84373
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+  - { reg: '$s1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $s0, $s1
+
+    ; SELECTED-LABEL: name: test_rule1288_id423_at_idx84373
+    ; SELECTED: liveins: $s0, $s1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBSrr]]
+    %2:fpr(s32) = COPY $s1
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1289_id424_at_idx84416
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1289_id424_at_idx84416
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBDrr]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1290_id922_at_idx84459
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1290_id922_at_idx84459
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FSUBv4f16_:%[0-9]+]]:fpr64 = FSUBv4f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBv4f16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1291_id923_at_idx84502
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1291_id923_at_idx84502
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FSUBv8f16_:%[0-9]+]]:fpr128 = FSUBv8f16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBv8f16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1292_id924_at_idx84545
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1292_id924_at_idx84545
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1293_id925_at_idx84588
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1293_id925_at_idx84588
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1294_id926_at_idx84631
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1294_id926_at_idx84631
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FSUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1295_id54_at_idx84674
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1295_id54_at_idx84674
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSRVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_LSHR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1296_id939_at_idx84715
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1296_id939_at_idx84715
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1297_id940_at_idx84758
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1297_id940_at_idx84758
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1298_id941_at_idx84801
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1298_id941_at_idx84801
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1299_id942_at_idx84844
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1299_id942_at_idx84844
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1300_id943_at_idx84887
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1300_id943_at_idx84887
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[MULv2i32_:%[0-9]+]]:fpr64 = MULv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1301_id944_at_idx84930
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1301_id944_at_idx84930
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[MULv4i32_:%[0-9]+]]:fpr128 = MULv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[MULv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_MUL %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1302_id106_at_idx84973
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1302_id106_at_idx84973
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1303_id107_at_idx85014
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1303_id107_at_idx85014
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1304_id1174_at_idx85055
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1304_id1174_at_idx85055
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1305_id1175_at_idx85098
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1305_id1175_at_idx85098
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1306_id1827_at_idx85141
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1306_id1827_at_idx85141
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv8i8_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1307_id1828_at_idx85184
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1307_id1828_at_idx85184
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv8i8_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1308_id1829_at_idx85227
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1308_id1829_at_idx85227
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv8i8_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1309_id1830_at_idx85270
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1309_id1830_at_idx85270
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv16i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1310_id1831_at_idx85313
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1310_id1831_at_idx85313
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv16i8_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1311_id1832_at_idx85356
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1311_id1832_at_idx85356
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[ORRv16i8_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_OR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1312_id50_at_idx85399
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1312_id50_at_idx85399
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIVWr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_SDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1313_id51_at_idx85440
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1313_id51_at_idx85440
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SDIVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1314_id53_at_idx85481
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1314_id53_at_idx85481
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[LSLVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SHL %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1315_id1051_at_idx85522
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1315_id1051_at_idx85522
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1316_id1052_at_idx85565
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1316_id1052_at_idx85565
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1317_id1053_at_idx85608
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1317_id1053_at_idx85608
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv4i16_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1318_id1054_at_idx85651
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1318_id1054_at_idx85651
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv8i16_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1319_id1055_at_idx85694
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1319_id1055_at_idx85694
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUBv2i32_:%[0-9]+]]:fpr64 = SUBv2i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv2i32_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1320_id1056_at_idx85737
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1320_id1056_at_idx85737
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBv4i32_:%[0-9]+]]:fpr128 = SUBv4i32 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv4i32_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1321_id1057_at_idx85780
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1321_id1057_at_idx85780
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SUBv2i64_:%[0-9]+]]:fpr128 = SUBv2i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv2i64_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1322_id1213_at_idx85823
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1322_id1213_at_idx85823
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SUBv1i64_:%[0-9]+]]:fpr64 = SUBv1i64 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBv1i64_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1323_id1965_at_idx85866
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1323_id1965_at_idx85866
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBSWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1324_id1966_at_idx85910
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1324_id1966_at_idx85910
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; SELECTED: $noreg = PATCHABLE_RET [[SUBSXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_SUB %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1325_id48_at_idx85954
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1325_id48_at_idx85954
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIVWr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_UDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1326_id49_at_idx85995
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1326_id49_at_idx85995
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UDIVXr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_UDIV %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1327_id98_at_idx86036
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; SELECTED-LABEL: name: test_rule1327_id98_at_idx86036
+    ; SELECTED: liveins: $w0, $w1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORWrr]]
+    %2:gpr(s32) = COPY $w1
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1328_id99_at_idx86077
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; SELECTED-LABEL: name: test_rule1328_id99_at_idx86077
+    ; SELECTED: liveins: $x0, $x1
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORXrr]]
+    %2:gpr(s64) = COPY $x1
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1329_id1170_at_idx86118
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1329_id1170_at_idx86118
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv8i8_]]
+    %2:fpr(<8 x s8>) = COPY $d1
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1330_id1171_at_idx86161
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1330_id1171_at_idx86161
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv16i8_]]
+    %2:fpr(<16 x s8>) = COPY $q1
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1331_id1791_at_idx86204
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1331_id1791_at_idx86204
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv8i8_]]
+    %2:fpr(<4 x s16>) = COPY $d1
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1332_id1792_at_idx86247
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1332_id1792_at_idx86247
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv8i8_]]
+    %2:fpr(<2 x s32>) = COPY $d1
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1333_id1793_at_idx86290
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+  - { reg: '$d1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $d0, $d1
+
+    ; SELECTED-LABEL: name: test_rule1333_id1793_at_idx86290
+    ; SELECTED: liveins: $d0, $d1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv8i8_]]
+    %2:fpr(s64) = COPY $d1
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1334_id1794_at_idx86333
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1334_id1794_at_idx86333
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv16i8_]]
+    %2:fpr(<8 x s16>) = COPY $q1
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1335_id1795_at_idx86376
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1335_id1795_at_idx86376
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv16i8_]]
+    %2:fpr(<4 x s32>) = COPY $q1
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1336_id1796_at_idx86419
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+  - { reg: '$q1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $q0, $q1
+
+    ; SELECTED-LABEL: name: test_rule1336_id1796_at_idx86419
+    ; SELECTED: liveins: $q0, $q1
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[EORv16i8_]]
+    %2:fpr(<2 x s64>) = COPY $q1
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_XOR %1, %2
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1337_id2925_at_idx86462
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1337_id2925_at_idx86462
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1338_id2928_at_idx86507
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1338_id2928_at_idx86507
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1339_id2931_at_idx86552
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1339_id2931_at_idx86552
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1340_id3134_at_idx86597
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1340_id3134_at_idx86597
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1341_id3135_at_idx86634
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1341_id3135_at_idx86634
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1342_id3136_at_idx86671
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1342_id3136_at_idx86671
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1345_id3139_at_idx86782
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1345_id3139_at_idx86782
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:gpr(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1346_id3140_at_idx86819
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1346_id3140_at_idx86819
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:gpr(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1347_id3141_at_idx86856
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1347_id3141_at_idx86856
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:gpr(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1350_id3144_at_idx86967
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1350_id3144_at_idx86967
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1351_id3145_at_idx87004
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1351_id3145_at_idx87004
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1352_id3146_at_idx87064
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1352_id3146_at_idx87064
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1353_id3147_at_idx87124
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1353_id3147_at_idx87124
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1356_id3150_at_idx87304
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1356_id3150_at_idx87304
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v8i8_:%[0-9]+]]:fpr64 = REV64v8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1357_id3151_at_idx87364
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1357_id3151_at_idx87364
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v4i16_:%[0-9]+]]:fpr64 = REV64v4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1358_id3152_at_idx87424
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1358_id3152_at_idx87424
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v2i32_:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1361_id3155_at_idx87604
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1361_id3155_at_idx87604
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1363_id3157_at_idx87674
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1363_id3157_at_idx87674
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1364_id3161_at_idx87709
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1364_id3161_at_idx87709
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+    ; SELECTED: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1365_id3162_at_idx87744
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1365_id3162_at_idx87744
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_BITCAST %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1369_id3166_at_idx87884
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1369_id3166_at_idx87884
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v2i32_:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1370_id3167_at_idx87930
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1370_id3167_at_idx87930
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v4i16_:%[0-9]+]]:fpr64 = REV64v4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1371_id3168_at_idx87976
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1371_id3168_at_idx87976
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v8i8_:%[0-9]+]]:fpr64 = REV64v8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1374_id3171_at_idx88114
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1374_id3171_at_idx88114
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v2i32_:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1375_id3172_at_idx88149
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1375_id3172_at_idx88149
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v4i16_:%[0-9]+]]:fpr64 = REV64v4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1376_id3173_at_idx88184
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1376_id3173_at_idx88184
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[REV64v8i8_:%[0-9]+]]:fpr64 = REV64v8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REV64v8i8_]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1379_id3176_at_idx88289
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1379_id3176_at_idx88289
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1381_id3178_at_idx88377
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1381_id3178_at_idx88377
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1382_id3179_at_idx88423
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1382_id3179_at_idx88423
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1383_id3180_at_idx88469
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1383_id3180_at_idx88469
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1387_id3184_at_idx88653
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1387_id3184_at_idx88653
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1388_id3185_at_idx88688
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1388_id3185_at_idx88688
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1389_id3186_at_idx88723
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1389_id3186_at_idx88723
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1393_id3190_at_idx88863
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1393_id3190_at_idx88863
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1394_id3191_at_idx88907
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1394_id3191_at_idx88907
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1395_id3192_at_idx88953
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1395_id3192_at_idx88953
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1396_id3193_at_idx88999
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1396_id3193_at_idx88999
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1400_id3197_at_idx89183
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1400_id3197_at_idx89183
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1401_id3198_at_idx89218
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1401_id3198_at_idx89218
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1402_id3199_at_idx89253
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1402_id3199_at_idx89253
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1406_id3203_at_idx89393
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1406_id3203_at_idx89393
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1420_id3217_at_idx89967
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1420_id3217_at_idx89967
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1421_id3218_at_idx90013
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1421_id3218_at_idx90013
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1422_id3219_at_idx90059
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1422_id3219_at_idx90059
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1427_id3224_at_idx90289
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1427_id3224_at_idx90289
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1428_id3225_at_idx90324
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1428_id3225_at_idx90324
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1429_id3226_at_idx90359
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1429_id3226_at_idx90359
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1471_id3268_at_idx92050
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1471_id3268_at_idx92050
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1472_id3269_at_idx92096
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1472_id3269_at_idx92096
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1473_id3270_at_idx92142
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1473_id3270_at_idx92142
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1477_id3274_at_idx92326
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1477_id3274_at_idx92326
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1478_id3275_at_idx92372
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1478_id3275_at_idx92372
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1479_id3276_at_idx92423
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1479_id3276_at_idx92423
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1480_id3277_at_idx92506
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1480_id3277_at_idx92506
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1484_id3281_at_idx92806
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1484_id3281_at_idx92806
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(s128) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(s128)
+
+...
+---
+name:            test_rule1485_id3282_at_idx92889
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1485_id3282_at_idx92889
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1486_id3283_at_idx92935
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1486_id3283_at_idx92935
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1487_id3284_at_idx92981
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1487_id3284_at_idx92981
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1489_id3286_at_idx93073
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1489_id3286_at_idx93073
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1491_id3288_at_idx93165
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1491_id3288_at_idx93165
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1492_id3289_at_idx93216
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1492_id3289_at_idx93216
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1493_id3290_at_idx93251
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1493_id3290_at_idx93251
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1495_id3292_at_idx93321
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1495_id3292_at_idx93321
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1497_id3294_at_idx93391
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1497_id3294_at_idx93391
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1498_id3295_at_idx93435
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1498_id3295_at_idx93435
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1499_id3296_at_idx93481
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1499_id3296_at_idx93481
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1501_id3298_at_idx93573
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1501_id3298_at_idx93573
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1502_id3299_at_idx93619
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1502_id3299_at_idx93619
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1504_id3301_at_idx93711
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1504_id3301_at_idx93711
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1505_id3302_at_idx93794
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1505_id3302_at_idx93794
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1507_id3304_at_idx93864
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1507_id3304_at_idx93864
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1508_id3305_at_idx93899
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1508_id3305_at_idx93899
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1510_id3307_at_idx93969
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1510_id3307_at_idx93969
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1537_id3334_at_idx95137
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1537_id3334_at_idx95137
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1538_id3335_at_idx95183
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1538_id3335_at_idx95183
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1539_id3336_at_idx95229
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1539_id3336_at_idx95229
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1540_id3337_at_idx95275
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1540_id3337_at_idx95275
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1543_id3340_at_idx95413
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1543_id3340_at_idx95413
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1544_id3341_at_idx95496
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1544_id3341_at_idx95496
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1545_id3342_at_idx95531
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1545_id3342_at_idx95531
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1546_id3343_at_idx95566
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1546_id3343_at_idx95566
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<16 x s8>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1549_id3346_at_idx95671
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1549_id3346_at_idx95671
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1563_id3360_at_idx96293
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1563_id3360_at_idx96293
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1564_id3361_at_idx96339
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1564_id3361_at_idx96339
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1565_id3362_at_idx96385
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1565_id3362_at_idx96385
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1566_id3363_at_idx96431
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1566_id3363_at_idx96431
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1570_id3367_at_idx96615
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1570_id3367_at_idx96615
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(s128) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(s128)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1571_id3368_at_idx96698
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1571_id3368_at_idx96698
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1572_id3369_at_idx96733
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1572_id3369_at_idx96733
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1573_id3370_at_idx96768
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1573_id3370_at_idx96768
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<16 x s8>)
+
+...
+---
+name:            test_rule1577_id115_at_idx96908
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1577_id115_at_idx96908
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVWr]]
+    %1:gpr(s32) = COPY $w0
+    %0:gpr(s32) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1578_id116_at_idx96941
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1578_id116_at_idx96941
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[REVXr]]
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s64) = G_BSWAP %1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1579_id14_at_idx96974
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1579_id14_at_idx96974
+    ; SELECTED: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVi32imm]]
+    %0:gpr(s32) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1580_id15_at_idx97007
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+body:             |
+  bb.0.entry:
+    ; SELECTED-LABEL: name: test_rule1580_id15_at_idx97007
+    ; SELECTED: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1
+    ; SELECTED: $noreg = PATCHABLE_RET [[MOVi64imm]]
+    %0:gpr(s64) = G_CONSTANT 1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1581_id371_at_idx97040
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1581_id371_at_idx97040
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FNEGHr:%[0-9]+]]:fpr16 = FNEGHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s16) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1582_id372_at_idx97075
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1582_id372_at_idx97075
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s32) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1583_id373_at_idx97110
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1583_id373_at_idx97110
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s64) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1584_id595_at_idx97145
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1584_id595_at_idx97145
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNEGv4f16_:%[0-9]+]]:fpr64 = FNEGv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1585_id596_at_idx97180
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1585_id596_at_idx97180
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FNEGv8f16_:%[0-9]+]]:fpr128 = FNEGv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1586_id597_at_idx97215
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1586_id597_at_idx97215
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1587_id598_at_idx97250
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1587_id598_at_idx97250
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1588_id599_at_idx97285
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1588_id599_at_idx97285
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FNEGv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FNEG %1
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1589_id364_at_idx97320
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1589_id364_at_idx97320
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTDHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s64) = G_FPEXT %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1590_id365_at_idx97355
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1590_id365_at_idx97355
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTSHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:fpr(s32) = G_FPEXT %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1591_id366_at_idx97390
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1591_id366_at_idx97390
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTDSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s64) = G_FPEXT %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1592_id2383_at_idx97425
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1592_id2383_at_idx97425
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1593_id2385_at_idx97458
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1593_id2385_at_idx97458
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1594_id311_at_idx97491
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1594_id311_at_idx97491
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTZSUWHr:%[0-9]+]]:gpr32 = FCVTZSUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_FPTOSI %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1595_id312_at_idx97526
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1595_id312_at_idx97526
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTZSUXHr:%[0-9]+]]:gpr64 = FCVTZSUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_FPTOSI %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1596_id313_at_idx97561
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1596_id313_at_idx97561
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1597_id314_at_idx97596
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1597_id314_at_idx97596
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_FPTOSI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1598_id315_at_idx97631
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1598_id315_at_idx97631
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1599_id316_at_idx97666
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1599_id316_at_idx97666
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_FPTOSI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1600_id585_at_idx97701
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1600_id585_at_idx97701
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSv4f16_:%[0-9]+]]:fpr64 = FCVTZSv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FPTOSI %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1601_id586_at_idx97736
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1601_id586_at_idx97736
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv8f16_:%[0-9]+]]:fpr128 = FCVTZSv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1602_id587_at_idx97771
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1602_id587_at_idx97771
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1603_id588_at_idx97806
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1603_id588_at_idx97806
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1604_id589_at_idx97841
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1604_id589_at_idx97841
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1605_id317_at_idx97876
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1605_id317_at_idx97876
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTZUUWHr:%[0-9]+]]:gpr32 = FCVTZUUWHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUWHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s32) = G_FPTOUI %1(s16)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1606_id318_at_idx97911
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$h0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $h0
+
+    ; SELECTED-LABEL: name: test_rule1606_id318_at_idx97911
+    ; SELECTED: liveins: $h0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; SELECTED: [[FCVTZUUXHr:%[0-9]+]]:gpr64 = FCVTZUUXHr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUXHr]]
+    %1:fpr(s16) = COPY $h0
+    %0:gpr(s64) = G_FPTOUI %1(s16)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1607_id319_at_idx97946
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1607_id319_at_idx97946
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUWSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s32) = G_FPTOUI %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1608_id320_at_idx97981
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1608_id320_at_idx97981
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUXSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:gpr(s64) = G_FPTOUI %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1609_id321_at_idx98016
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1609_id321_at_idx98016
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUWDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s32) = G_FPTOUI %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1610_id322_at_idx98051
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1610_id322_at_idx98051
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUUXDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:gpr(s64) = G_FPTOUI %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1611_id590_at_idx98086
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1611_id590_at_idx98086
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUv4f16_:%[0-9]+]]:fpr64 = FCVTZUv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_FPTOUI %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1612_id591_at_idx98121
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1612_id591_at_idx98121
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv8f16_:%[0-9]+]]:fpr128 = FCVTZUv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1613_id592_at_idx98156
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1613_id592_at_idx98156
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1614_id593_at_idx98191
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1614_id593_at_idx98191
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1615_id594_at_idx98226
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1615_id594_at_idx98226
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1616_id362_at_idx98261
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1616_id362_at_idx98261
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTHDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s16) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1617_id363_at_idx98296
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1617_id363_at_idx98296
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTSDr]]
+    %1:fpr(s64) = COPY $d0
+    %0:fpr(s32) = G_FPTRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1618_id367_at_idx98331
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$s0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $s0
+
+    ; SELECTED-LABEL: name: test_rule1618_id367_at_idx98331
+    ; SELECTED: liveins: $s0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; SELECTED: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTHSr]]
+    %1:fpr(s32) = COPY $s0
+    %0:fpr(s16) = G_FPTRUNC %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1619_id2389_at_idx98366
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1619_id2389_at_idx98366
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1620_id2390_at_idx98399
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1620_id2390_at_idx98399
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1621_id2923_at_idx98432
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1621_id2923_at_idx98432
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1622_id2926_at_idx98477
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1622_id2926_at_idx98477
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1623_id2929_at_idx98522
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1623_id2929_at_idx98522
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1624_id335_at_idx98567
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1624_id335_at_idx98567
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SCVTFUWHri:%[0-9]+]]:fpr16 = SCVTFUWHri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUWHri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s16) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1625_id336_at_idx98602
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1625_id336_at_idx98602
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUWSri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s32) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1626_id337_at_idx98637
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1626_id337_at_idx98637
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUWDri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s64) = G_SITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1627_id338_at_idx98672
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1627_id338_at_idx98672
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SCVTFUXHri:%[0-9]+]]:fpr16 = SCVTFUXHri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUXHri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s16) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1628_id339_at_idx98707
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1628_id339_at_idx98707
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUXSri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s32) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1629_id340_at_idx98742
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1629_id340_at_idx98742
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFUXDri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s64) = G_SITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1630_id685_at_idx98777
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1630_id685_at_idx98777
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SCVTFv4f16_:%[0-9]+]]:fpr64 = SCVTFv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_SITOFP %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1631_id686_at_idx98812
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1631_id686_at_idx98812
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv8f16_:%[0-9]+]]:fpr128 = SCVTFv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1632_id687_at_idx98847
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1632_id687_at_idx98847
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1633_id688_at_idx98882
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1633_id688_at_idx98882
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1634_id689_at_idx98917
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1634_id689_at_idx98917
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1635_id748_at_idx98952
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1635_id748_at_idx98952
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XTNv8i8_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s8>)
+
+...
+---
+name:            test_rule1636_id749_at_idx98987
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1636_id749_at_idx98987
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XTNv4i16_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1637_id750_at_idx99022
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1637_id750_at_idx99022
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[XTNv2i32_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1638_id3062_at_idx99057
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1638_id3062_at_idx99057
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; SELECTED: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
+    ; SELECTED: $noreg = PATCHABLE_RET [[COPY1]]
+    %1:gpr(s64) = COPY $x0
+    %0:gpr(s32) = G_TRUNC %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1639_id347_at_idx99106
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1639_id347_at_idx99106
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UCVTFUWHri:%[0-9]+]]:fpr16 = UCVTFUWHri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUWHri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s16) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1640_id348_at_idx99141
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1640_id348_at_idx99141
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUWSri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s32) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1641_id349_at_idx99176
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; SELECTED-LABEL: name: test_rule1641_id349_at_idx99176
+    ; SELECTED: liveins: $w0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; SELECTED: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUWDri]]
+    %1:gpr(s32) = COPY $w0
+    %0:fpr(s64) = G_UITOFP %1(s32)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1642_id350_at_idx99211
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1642_id350_at_idx99211
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UCVTFUXHri:%[0-9]+]]:fpr16 = UCVTFUXHri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUXHri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s16) = G_UITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s16)
+
+...
+---
+name:            test_rule1643_id351_at_idx99246
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1643_id351_at_idx99246
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUXSri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s32) = G_UITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s32)
+
+...
+---
+name:            test_rule1644_id352_at_idx99281
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; SELECTED-LABEL: name: test_rule1644_id352_at_idx99281
+    ; SELECTED: liveins: $x0
+    ; SELECTED: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; SELECTED: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFUXDri]]
+    %1:gpr(s64) = COPY $x0
+    %0:fpr(s64) = G_UITOFP %1(s64)
+    $noreg = PATCHABLE_RET %0(s64)
+
+...
+---
+name:            test_rule1645_id729_at_idx99316
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1645_id729_at_idx99316
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UCVTFv4f16_:%[0-9]+]]:fpr64 = UCVTFv4f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv4f16_]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s16>) = G_UITOFP %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s16>)
+
+...
+---
+name:            test_rule1646_id730_at_idx99351
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1646_id730_at_idx99351
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv8f16_:%[0-9]+]]:fpr128 = UCVTFv8f16 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv8f16_]]
+    %1:fpr(<8 x s16>) = COPY $q0
+    %0:fpr(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1647_id731_at_idx99386
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1647_id731_at_idx99386
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s32>)
+
+...
+---
+name:            test_rule1648_id732_at_idx99421
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1648_id732_at_idx99421
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
+    %1:fpr(<4 x s32>) = COPY $q0
+    %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1649_id733_at_idx99456
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$q0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $q0
+
+    ; SELECTED-LABEL: name: test_rule1649_id733_at_idx99456
+    ; SELECTED: liveins: $q0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; SELECTED: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
+    ; SELECTED: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
+    %1:fpr(<2 x s64>) = COPY $q0
+    %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1650_id2924_at_idx99491
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1650_id2924_at_idx99491
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
+    %1:fpr(<8 x s8>) = COPY $d0
+    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    $noreg = PATCHABLE_RET %0(<8 x s16>)
+
+...
+---
+name:            test_rule1651_id2927_at_idx99536
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1651_id2927_at_idx99536
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
+    %1:fpr(<4 x s16>) = COPY $d0
+    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+    $noreg = PATCHABLE_RET %0(<4 x s32>)
+
+...
+---
+name:            test_rule1652_id2930_at_idx99581
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+liveins:
+  - { reg: '$d0', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $d0
+
+    ; SELECTED-LABEL: name: test_rule1652_id2930_at_idx99581
+    ; SELECTED: liveins: $d0
+    ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; SELECTED: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
+    ; SELECTED: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
+    %1:fpr(<2 x s32>) = COPY $d0
+    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+    $noreg = PATCHABLE_RET %0(<2 x s64>)
+
+...
+---
+name:            test_rule1653_id150_at_idx99626
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors:
+
+    ; SELECTED-LABEL: name: test_rule1653_id150_at_idx99626
+    ; SELECTED: successors:
+    ; SELECTED: B %bb.0
+    ; SELECTED: $noreg = PATCHABLE_RET
+    G_BR %bb.0
+    $noreg = PATCHABLE_RET
+
+...
Index: test/CodeGen/AArch64/GlobalISel/arm64-instruction-select-testgen-testgend.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/GlobalISel/arm64-instruction-select-testgen-testgend.mir
@@ -0,0 +1,33037 @@
+# NOTE: This test has been autogenerated by utils/update_instruction_select_testgen_tests.sh
+# RUN: llc -mtriple aarch64-- -run-pass instruction-select-testgen \
+# RUN:     -testgen-set-all-features -verify-machineinstrs -simplify-mir %s \
+# RUN:     -o - 2>&1 | FileCheck %s --check-prefix=TESTGEND
+#
+# TESTGEND:       ---
+# TESTGEND:       name:            test_return
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule0
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_SEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule2
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_SEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule3
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule4
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = G_LOAD %2(p0) :: (load 4)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule5
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule6
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule7
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule8
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule9
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule10
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = G_LOAD %1(p0) :: (load 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule11
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %1(p0) :: (load 2)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule12
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_LOAD %1(p0) :: (load 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule13
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule14
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule15
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(s64) = COPY $x0
+# TESTGEND:           G_STORE %0(s64), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule16
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = COPY $w0
+# TESTGEND:           G_STORE %0(s32), %1(p0) :: (store 4)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule17
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = COPY $h0
+# TESTGEND:           G_STORE %0(s16), %1(p0) :: (store 2)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule18
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = COPY $s0
+# TESTGEND:           G_STORE %0(s32), %1(p0) :: (store 4)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule19
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(s64) = COPY $d0
+# TESTGEND:           G_STORE %0(s64), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule20
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule21
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule22
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule27
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule28
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule29
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule30
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule34
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s128) = COPY $q0
+# TESTGEND:           G_STORE %0(s128), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule35
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %2:gpr(s64) = G_SEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule36
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %2:gpr(s64) = G_ZEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule37
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule38
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule39
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule40
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule41
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule42
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule43
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule44
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule45
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule46
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule47
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_SEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule48
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_ZEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %0, %4
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule49
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_SEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule50
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_ZEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_ADD %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule51
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule52
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule53
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_SEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule54
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:         - { id: 5, class: gpr }
+# TESTGEND:         - { id: 6, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%5' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%6' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0, $w1
+#
+# TESTGEND:           %6:gpr(s32) = COPY $w1
+# TESTGEND:           %5:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_ZEXT %6(s32)
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %5(s32)
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           %3:gpr(s64) = G_SUB %4, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %3(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule55
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_SEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule56
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule57
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_SEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule58
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule59
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = G_LOAD %2(p0) :: (load 4)
+# TESTGEND:           %1:gpr(s64) = G_SEXT %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule60
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule61
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule62
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %1:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<16 x s8>), %0(s64), %4(<16 x s8>), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule63
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %1:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %2:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<8 x s16>), %0(s64), %4(<8 x s16>), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule64
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %1:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %2:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<4 x s32>), %0(s64), %4(<4 x s32>), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule65
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %4:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %1:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:fpr(s64) = G_CONSTANT 1
+# TESTGEND:           %2:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcopy.lane), %3(<2 x s64>), %0(s64), %4(<2 x s64>), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule66
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule67
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule68
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule69
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule70
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s16>), %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule71
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<8 x s16>), %0(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule72
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<2 x s32>), %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule73
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule74
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule75
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule76
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<4 x s32>), %0(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule77
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(<2 x s64>), %0(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule78
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(s32), %4(s32)
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule79
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %3(s32), %4(s32)
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule80
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $s0, $s1
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s1
+# TESTGEND:           %3:fpr(s32) = COPY $s0
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %3(s32), %4(s32)
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %2(s64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule81
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $s0, $s1
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s1
+# TESTGEND:           %3:fpr(s32) = COPY $s0
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %3(s32), %4(s32)
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %2(s64), %0(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule82
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %0(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule83
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesd), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesimc), %0(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule84
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s32) = G_MUL %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule85
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %4:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s64) = G_MUL %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule86
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %3:gpr(s32) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s32) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s32) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule87
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %4:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %3:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s64) = G_SUB %3, %4
+# TESTGEND:           %1:gpr(s64) = G_MUL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule88
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s32) = G_MUL %3, %4
+# TESTGEND:           %1:gpr(s32) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule89
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %4:gpr(s64) = COPY $x1
+# TESTGEND:           %3:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT 0
+# TESTGEND:           %0:gpr(s64) = G_MUL %3, %4
+# TESTGEND:           %1:gpr(s64) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule90
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule91
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule92
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s1)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule93
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %2(p0) :: (load 2)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule94
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule95
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ANYEXT %0(s1)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule96
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s1)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule98
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s8) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s8)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule99
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
+# TESTGEND:           %1:gpr(s32) = G_ZEXT %0(s1)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule100
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %1:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_SEXT %3(s32)
+# TESTGEND:           %2:gpr(s64) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule101
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %1:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %0:gpr(s64) = G_ZEXT %3(s32)
+# TESTGEND:           %2:gpr(s64) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule102
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule103
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule104
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule105
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule106
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule107
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule108
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule109
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule110
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule111
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<8 x s8>), %5(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule112
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<4 x s16>), %5(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule113
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %5:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %4(<2 x s32>), %5(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule114
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %1:gpr(s64) = G_SEXT %4(s32)
+# TESTGEND:           %0:gpr(s64) = G_SEXT %3(s32)
+# TESTGEND:           %2:gpr(s64) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule115
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %1:gpr(s64) = G_ZEXT %4(s32)
+# TESTGEND:           %0:gpr(s64) = G_ZEXT %3(s32)
+# TESTGEND:           %2:gpr(s64) = G_MUL %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule116
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule117
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = G_LOAD %1(p0) :: (load 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule118
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_LOAD %1(p0) :: (load 2)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule119
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_LOAD %1(p0) :: (load 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule120
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule121
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule122
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(s64) = COPY $x0
+# TESTGEND:           G_STORE %0(s64), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule123
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = COPY $w0
+# TESTGEND:           G_STORE %0(s32), %1(p0) :: (store 4)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule124
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = COPY $h0
+# TESTGEND:           G_STORE %0(s16), %1(p0) :: (store 2)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule125
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = COPY $s0
+# TESTGEND:           G_STORE %0(s32), %1(p0) :: (store 4)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule126
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(s64) = COPY $d0
+# TESTGEND:           G_STORE %0(s64), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule127
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(s128) = COPY $q0
+# TESTGEND:           G_STORE %0(s128), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule128
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule129
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule130
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule135
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule136
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule137
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule138
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule143
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule145
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule146
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule150
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule152
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule154
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule155
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule157
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule158
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule159
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d1
+# TESTGEND:           %0:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule164
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule165
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule166
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule167
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %1:fpr(p0) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule172
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<8 x s8>), %3(<8 x s8>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule173
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<16 x s8>), %3(<16 x s8>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule174
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<4 x s16>), %3(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule175
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<8 x s16>), %3(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule176
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<2 x s32>), %3(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule177
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<4 x s32>), %3(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule178
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(<2 x s64>), %3(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule179
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<8 x s8>), %3(<8 x s8>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule180
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<16 x s8>), %3(<16 x s8>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule181
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<4 x s16>), %3(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule182
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<8 x s16>), %3(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule183
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<2 x s32>), %3(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule184
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<4 x s32>), %3(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule185
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(<2 x s64>), %3(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule186
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsli), %2(s64), %3(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule187
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vsri), %2(s64), %3(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule188
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule189
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule190
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule191
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule192
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule193
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule194
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule195
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule196
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rshrn), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule197
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule198
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule199
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrn), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule200
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule201
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule202
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshrun), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule203
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule204
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule205
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrn), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule206
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule207
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule208
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshrun), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule209
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule210
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule211
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshrn), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule212
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule213
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule214
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshrn), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule215
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule216
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule217
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule218
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule221
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule222
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(s32), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule223
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule224
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(s64), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule227
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule228
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule229
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.hint), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule230
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.dmb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule231
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.dsb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule232
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.isb), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule233
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule234
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule235
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule236
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule237
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxs), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule238
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule239
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule240
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule241
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule242
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2fxu), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule243
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule244
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule245
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule246
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule247
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxs2fp), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule248
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<4 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule249
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<8 x s16>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule250
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<2 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule251
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<4 x s32>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule252
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_CONSTANT 1
+# TESTGEND:           %1:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp), %2(<2 x s64>), %0(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule253
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule254
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule255
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule256
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule257
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule258
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule259
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule260
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule261
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule262
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule263
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule264
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule265
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule266
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule267
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule268
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule269
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule270
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule271
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule272
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule273
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule274
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule275
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(s64) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule276
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule277
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule278
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule279
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule280
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule281
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(s64) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule282
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule283
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule284
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule285
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule286
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule287
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule288
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule289
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule290
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<16 x s8>), %4(<16 x s8>)
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule291
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule292
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<8 x s16>), %4(<8 x s16>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule293
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule294
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %3(<4 x s32>), %4(<4 x s32>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule295
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule296
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule297
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule298
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule299
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule300
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule301
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule302
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule303
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule304
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<8 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule305
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(s64) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule306
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %3(<4 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule307
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule308
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<16 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule309
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule310
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<8 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule311
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(s64) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule312
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %3(<4 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule313
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule314
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule315
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule316
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_AND %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule317
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule318
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule319
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule320
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_OR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule321
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule322
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule323
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule324
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<8 x s8>), %4(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule325
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<4 x s16>), %4(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule326
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %3(<2 x s32>), %4(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule327
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule328
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule329
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %4:gpr(s32) = COPY $w1
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule330
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %4:gpr(s64) = COPY $x1
+# TESTGEND:           %3:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule331
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w1
+# TESTGEND:           %2:gpr(s32) = COPY $w0
+# TESTGEND:           %4:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s32) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule332
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:         - { id: 4, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %3:gpr(s64) = COPY $x1
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %4:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %3, %4
+# TESTGEND:           %1:gpr(s64) = G_XOR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule333
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule334
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule335
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule336
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<8 x s8>), %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule337
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<4 x s16>), %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule338
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %2(<2 x s32>), %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule339
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %5:fpr(s32) = COPY $s2
+# TESTGEND:           %4:fpr(s32) = COPY $s1
+# TESTGEND:           %3:fpr(s32) = COPY $s0
+# TESTGEND:           %1:fpr(s32) = G_FNEG %5
+# TESTGEND:           %0:fpr(s32) = G_FNEG %4
+# TESTGEND:           %2:fpr(s32) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule340
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %5:fpr(s64) = COPY $d2
+# TESTGEND:           %4:fpr(s64) = COPY $d1
+# TESTGEND:           %3:fpr(s64) = COPY $d0
+# TESTGEND:           %1:fpr(s64) = G_FNEG %5
+# TESTGEND:           %0:fpr(s64) = G_FNEG %4
+# TESTGEND:           %2:fpr(s64) = G_FMA %0, %3, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule341
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %5:fpr(s32) = COPY $s2
+# TESTGEND:           %4:fpr(s32) = COPY $s1
+# TESTGEND:           %3:fpr(s32) = COPY $s0
+# TESTGEND:           %1:fpr(s32) = G_FNEG %5
+# TESTGEND:           %0:fpr(s32) = G_FNEG %4
+# TESTGEND:           %2:fpr(s32) = G_FMA %3, %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule342
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:         - { id: 5, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%5' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %5:fpr(s64) = COPY $d2
+# TESTGEND:           %4:fpr(s64) = COPY $d1
+# TESTGEND:           %3:fpr(s64) = COPY $d0
+# TESTGEND:           %1:fpr(s64) = G_FNEG %5
+# TESTGEND:           %0:fpr(s64) = G_FNEG %4
+# TESTGEND:           %2:fpr(s64) = G_FMA %3, %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule343
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule344
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule345
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule346
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule347
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule348
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_ADD %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule349
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule350
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule351
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule352
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %2:fpr(<8 x s16>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule353
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %2:fpr(<4 x s32>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule354
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %2:fpr(<2 x s64>) = G_SUB %0, %1
+# TESTGEND:           $noreg = PATCHABLE_RET %2(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule355
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $s0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1c), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule356
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $s0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1p), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule357
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $s0, $q1
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1m), %1(<4 x s32>), %2(s32), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule358
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1su0), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule359
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256h), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule360
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256h2), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule361
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256su1), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule362
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $q0, $d1
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbx1), %1(<8 x s8>), %2(<16 x s8>), %3(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule363
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbx1), %1(<16 x s8>), %2(<16 x s8>), %3(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule364
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32b), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule365
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32h), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule366
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32w), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule367
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32x), %1(s32), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule368
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cb), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule369
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32ch), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule370
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cw), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule371
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crc32cx), %1(s32), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule372
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule373
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule374
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule375
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule376
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule377
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule378
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule379
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule380
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule381
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule382
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule383
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule384
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule385
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule386
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule387
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule388
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule389
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule390
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule391
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule392
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule393
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule394
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule395
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule396
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule397
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule398
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule399
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule400
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule401
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule402
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule403
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule404
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule405
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule406
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule407
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule408
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule409
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule410
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule411
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule412
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule413
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule414
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule415
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule416
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule417
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule418
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule419
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule420
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule421
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule422
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule423
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule424
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule425
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule426
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule427
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule428
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule429
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule430
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule431
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule432
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminp), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule433
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule434
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule435
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule436
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule437
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule438
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule439
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule440
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule441
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule442
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule443
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule444
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule445
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule446
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule447
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule448
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmul), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule449
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmul), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule450
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule451
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule452
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule453
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule454
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule455
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sabd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule456
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule457
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule458
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule459
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule460
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule461
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule462
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule463
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule464
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule465
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule466
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule467
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.shsub), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule468
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule469
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule470
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule471
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule472
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule473
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smaxp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule474
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule475
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule476
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule477
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule478
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule479
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sminp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule480
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule481
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule482
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule483
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule484
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule485
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule486
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule487
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule488
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule489
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule490
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule491
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule492
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule493
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule494
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule495
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule496
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule497
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule498
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule499
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule500
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule501
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule502
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule503
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule504
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule505
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule506
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule507
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule508
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule509
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule510
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule511
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule512
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule513
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule514
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule515
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule516
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule517
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule518
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule519
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule520
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule521
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srhadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule522
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule523
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule524
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule525
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule526
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule527
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule528
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule529
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule530
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule531
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule532
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule533
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule534
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule535
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule536
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule537
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule538
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule539
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule540
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule541
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uabd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule542
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule543
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule544
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule545
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule546
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule547
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule548
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule549
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule550
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule551
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule552
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule553
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uhsub), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule554
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule555
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule556
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule557
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule558
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule559
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umaxp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule560
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule561
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule562
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule563
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule564
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule565
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uminp), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule566
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule567
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule568
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule569
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule570
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule571
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule572
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule573
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule574
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule575
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule576
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule577
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule578
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule579
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule580
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule581
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule582
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule583
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule584
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule585
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule586
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule587
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule588
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule589
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule590
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule591
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule592
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule593
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule594
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule595
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule596
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule597
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule598
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule599
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urhadd), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule600
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule601
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule602
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule603
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule604
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule605
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule606
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule607
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule608
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule609
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule610
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule611
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule612
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule613
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule614
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule615
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule616
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fabd), %1(s16), %2(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule617
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule618
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facge), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule619
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule620
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.facgt), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule621
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule622
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule623
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmulx), %1(s16), %2(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule624
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule625
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule626
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecps), %1(s16), %2(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule627
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule628
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule629
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrts), %1(s16), %2(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule630
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule631
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulh), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule632
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrdmulh), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule633
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule634
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule635
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule636
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule637
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule638
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule639
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule640
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule641
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule642
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule643
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule644
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmulls.scalar), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule645
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule646
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.suqadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule647
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule648
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.usqadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule649
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule650
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule651
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.addhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule652
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule653
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule654
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.subhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule655
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule656
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule657
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.raddhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule658
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<8 x s16>), %2(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule659
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule660
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rsubhn), %1(<2 x s64>), %2(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule661
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmull), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule662
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule663
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule664
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.smull), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule665
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule666
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqdmull), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule667
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<8 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule668
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<4 x s16>), %2(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule669
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.umull), %1(<2 x s32>), %2(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule670
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule671
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesd), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule672
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1su1), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule673
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha256su0), %1(<4 x s32>), %2(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule681
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule683
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqrshl), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule685
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqshl), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule687
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqsub), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule690
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqadd), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule692
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqrshl), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule694
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqshl), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule696
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqsub), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule698
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.udiv), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule699
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.udiv), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule700
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), %1(s32), %2(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule701
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule702
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fabd), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule703
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.pmull64), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule704
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbl1), %1(<16 x s8>), %2(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule705
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.tbl1), %1(<16 x s8>), %2(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule706
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule707
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ushl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule708
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.srshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule709
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urshl), %1(s64), %2(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule710
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule711
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule712
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule713
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule714
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule715
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule716
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule717
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule718
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule719
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule720
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule721
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule722
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule723
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule724
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule725
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule726
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule727
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule728
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule729
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule730
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule731
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule732
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule733
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule734
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule735
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule736
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule737
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule738
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule739
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule740
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule741
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule742
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule743
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule744
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule745
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule746
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule747
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule748
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule749
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule750
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule751
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule752
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule753
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule754
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule755
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule756
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule757
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule758
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule759
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule760
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule761
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule762
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule763
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule764
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule765
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule766
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.cls), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule767
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule768
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule769
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule770
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule771
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule772
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule773
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule774
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule775
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule776
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule777
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule778
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule779
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule780
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule781
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule782
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule783
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule784
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule785
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule786
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule787
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule788
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule789
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule790
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule791
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule792
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule793
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule794
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule795
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule796
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule797
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule798
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule799
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule800
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule801
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule802
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule803
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule804
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule805
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule806
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule807
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtxn), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule808
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule809
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule810
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule811
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule812
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule813
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule814
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule815
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule816
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule817
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule818
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule819
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule820
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule821
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule822
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule823
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rbit), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule824
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.rbit), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule825
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule826
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule827
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule828
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule829
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule830
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.saddlp), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule831
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule832
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule833
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule834
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule835
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule836
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule837
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule838
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule839
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule840
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule841
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule842
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule843
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule844
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule845
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule846
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule847
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtn), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule848
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule849
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule850
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqxtun), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule851
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule852
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule853
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule854
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule855
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule856
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule857
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule858
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule859
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uqxtn), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule860
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urecpe), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule861
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.urecpe), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule862
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ursqrte), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule863
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.ursqrte), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule864
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sisd.fcvtxn), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule865
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule866
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqabs), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule867
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule868
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.sqneg), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule869
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.sqxtn), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule870
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.sqxtun), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule871
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.scalar.uqxtn), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule872
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule873
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule874
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule875
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule876
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule877
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule878
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule879
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule880
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule881
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule882
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule883
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule884
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule885
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesimc), %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule886
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.sha1h), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule889
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frintn), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule890
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvthf2fp), %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule891
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfp2hf), %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule892
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtas), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule893
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtau), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule894
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtms), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule895
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtmu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule896
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtns), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule897
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtnu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule898
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtps), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule899
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fcvtpu), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule900
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule901
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule902
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpe), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule904
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule905
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule906
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frecpx), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule907
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule908
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule909
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.frsqrte), %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule911
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.faddv), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule912
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.faddv), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule913
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule914
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxnmv), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule915
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule916
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fmaxv), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule917
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule918
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminnmv), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule919
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule920
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.fminv), %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule921
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule922
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule923
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s32) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule924
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %2:gpr(s64) = G_CONSTANT -1
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule925
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.clrex)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule926
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule927
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           %1:gpr(s64) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule928
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FNEG %4
+# TESTGEND:           %1:fpr(s32) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule929
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(s64) = COPY $d2
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FNEG %4
+# TESTGEND:           %1:fpr(s64) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule930
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule931
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule932
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<2 x s64>) = COPY $q2
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule933
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$h2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1, $h2
+#
+# TESTGEND:           %4:fpr(s16) = COPY $h2
+# TESTGEND:           %3:fpr(s16) = COPY $h1
+# TESTGEND:           %2:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FNEG %4
+# TESTGEND:           %1:fpr(s16) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule934
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FNEG %4
+# TESTGEND:           %1:fpr(s32) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule935
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(s64) = COPY $d2
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FNEG %4
+# TESTGEND:           %1:fpr(s64) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule936
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<4 x s16>) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule937
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<8 x s16>) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule938
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule939
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule940
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<2 x s64>) = COPY $q2
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FNEG %4
+# TESTGEND:           %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule941
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$h2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1, $h2
+#
+# TESTGEND:           %4:fpr(s16) = COPY $h2
+# TESTGEND:           %3:fpr(s16) = COPY $h1
+# TESTGEND:           %2:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FNEG %4
+# TESTGEND:           %1:fpr(s16) = G_FMA %2, %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule942
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FNEG %4
+# TESTGEND:           %1:fpr(s32) = G_FMA %2, %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule943
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(s64) = COPY $d2
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FNEG %4
+# TESTGEND:           %1:fpr(s64) = G_FMA %2, %3, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule944
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule945
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule946
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule947
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule948
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule949
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule950
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule951
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule952
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule953
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule954
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule955
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %0, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule956
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule957
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<16 x s8>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule958
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule959
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule960
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<2 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule961
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule962
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule963
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule964
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule965
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule966
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule967
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_ADD %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule968
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ANYEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule969
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule970
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ZEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_ASHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule971
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ANYEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule972
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule973
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ZEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_LSHR %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule974
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ANYEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule975
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule976
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $w0
+#
+# TESTGEND:           %3:gpr(s32) = COPY $w0
+# TESTGEND:           %2:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ZEXT %3(s32)
+# TESTGEND:           %1:gpr(s64) = G_SHL %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule977
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<8 x s8>) = COPY $d2
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s8>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule978
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<16 x s8>) = COPY $q2
+# TESTGEND:           %3:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<16 x s8>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule979
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule980
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule981
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<2 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule982
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %4:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_MUL %3, %4
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule983
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule984
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule985
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule986
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
+# TESTGEND:           %1:fpr(<8 x s16>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule987
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
+# TESTGEND:           %1:fpr(<4 x s32>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule988
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $d0
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
+# TESTGEND:           %1:fpr(<2 x s64>) = G_SUB %2, %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule989
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$h2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1, $h2
+#
+# TESTGEND:           %4:fpr(s16) = COPY $h2
+# TESTGEND:           %3:fpr(s16) = COPY $h1
+# TESTGEND:           %2:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FMA %2, %3, %4
+# TESTGEND:           %1:fpr(s16) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule990
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %4:fpr(s32) = COPY $s2
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FMA %2, %3, %4
+# TESTGEND:           %1:fpr(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule991
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:         - { id: 4, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%4' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %4:fpr(s64) = COPY $d2
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FMA %2, %3, %4
+# TESTGEND:           %1:fpr(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule992
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %3:fpr(s16) = COPY $h1
+# TESTGEND:           %2:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FMUL %2, %3
+# TESTGEND:           %1:fpr(s16) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule993
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %3:fpr(s32) = COPY $s1
+# TESTGEND:           %2:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FMUL %2, %3
+# TESTGEND:           %1:fpr(s32) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule994
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %3:fpr(s64) = COPY $d1
+# TESTGEND:           %2:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FMUL %2, %3
+# TESTGEND:           %1:fpr(s64) = G_FNEG %0
+# TESTGEND:           $noreg = PATCHABLE_RET %1(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule995
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1, $x2
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x2
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule996
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1, $x2
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x2
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule997
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1, $x2
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x2
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule998
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1, $x2
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x2
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule999
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1, $x2
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x2
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1000
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1001
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1002
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1003
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1004
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1005
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1006
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1007
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1008
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1009
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1010
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1011
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1012
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1013
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1014
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:         - { id: 3, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1, $x0
+#
+# TESTGEND:           %3:gpr(p0) = COPY $x0
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMIC_CMPXCHG %3(p0), %1, %2 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1015
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1016
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1017
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1018
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1019
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1020
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1021
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1022
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1023
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1024
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1025
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1026
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1027
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1028
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1029
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1030
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1031
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1032
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1033
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1034
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_ADD %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1035
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1036
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1037
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1038
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1039
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1040
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1041
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1042
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1043
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1044
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1045
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1046
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1047
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1048
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1049
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1050
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1051
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1052
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1053
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1054
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_AND %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1055
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1056
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1057
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1058
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1059
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1060
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1061
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1062
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1063
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1064
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1065
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1066
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1067
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1068
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1069
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1070
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1071
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1072
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1073
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1074
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1075
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1076
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1077
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1078
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1079
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1080
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1081
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1082
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1083
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1084
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1085
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1086
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1087
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1088
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1089
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1090
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1091
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1092
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1093
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1094
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_MIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1095
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1096
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1097
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1098
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1099
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1100
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1101
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1102
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1103
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1104
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1105
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1106
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1107
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1108
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1109
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1110
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1111
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1112
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1113
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1114
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_OR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1115
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1116
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1117
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1118
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1119
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1120
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1121
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1122
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1123
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1124
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1125
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1126
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1127
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1128
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1129
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1130
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1131
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1132
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1133
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1134
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_SUB %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1135
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1136
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1137
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1138
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1139
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1140
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1141
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1142
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1143
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1144
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1145
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1146
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1147
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1148
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1149
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1150
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1151
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1152
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1153
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1154
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMAX %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1155
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1156
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1157
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1158
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1159
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1160
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1161
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1162
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1163
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1164
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1165
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1166
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1167
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1168
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1169
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1170
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1171
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1172
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1173
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1174
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_UMIN %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1175
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1176
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1177
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1178
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1179
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1180
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1181
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1182
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1183
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1184
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1185
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1186
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1187
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1188
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1189
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1190
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1191
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1192
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1193
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1194
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XCHG %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1195
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1196
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1197
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1198
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1199
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1200
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1201
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1202
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1203
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1204
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1205
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1206
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1207
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1208
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1209
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1210
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store monotonic 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1211
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acquire 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1212
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store release 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1213
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store acq_rel 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1214
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $x0
+#
+# TESTGEND:           %2:gpr(p0) = COPY $x0
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ATOMICRMW_XOR %2(p0), %1 :: (load store seq_cst 4)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1215
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:fpr(s16) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1216
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:fpr(s32) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1217
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:fpr(s64) = G_FCONSTANT double 0.000000e+00
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1218
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1219
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1220
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1221
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1222
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1223
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1224
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1225
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(s64) = G_LOAD %1(p0) :: (load 8)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1226
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1227
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1228
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1229
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $x0
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x0
+# TESTGEND:           %0:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1230
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(<8 x s8>) = COPY $x0
+# TESTGEND:           G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1231
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(<4 x s16>) = COPY $x0
+# TESTGEND:           G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1232
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(<2 x s32>) = COPY $x0
+# TESTGEND:           G_STORE %0(<2 x s32>), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1233
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%0' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %1:gpr(p0) = COPY $x1
+# TESTGEND:           %0:gpr(s64) = COPY $x0
+# TESTGEND:           G_STORE %0(s64), %1(p0) :: (store 8)
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1234
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$h2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1, $h2
+#
+# TESTGEND:           %3:fpr(s16) = COPY $h2
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1235
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$s2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1, $s2
+#
+# TESTGEND:           %3:fpr(s32) = COPY $s2
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1236
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %3:fpr(s64) = COPY $d2
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1237
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %3:fpr(<4 x s16>) = COPY $d2
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1238
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<8 x s16>) = COPY $q2
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1239
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$d2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1, $d2
+#
+# TESTGEND:           %3:fpr(<2 x s32>) = COPY $d2
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1240
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<4 x s32>) = COPY $q2
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1241
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:         - { id: 3, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:         - { reg: '$q2', virtual-reg: '%3' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1, $q2
+#
+# TESTGEND:           %3:fpr(<2 x s64>) = COPY $q2
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1242
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1243
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1244
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1245
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1246
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1247
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1248
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1249
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1250
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1251
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_ADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1252
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1253
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1254
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1255
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1256
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1257
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1258
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1259
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1260
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1261
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_AND %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1262
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_ASHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1263
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1264
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1265
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1266
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1267
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1268
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1269
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1270
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FADD %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1271
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1272
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1273
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1274
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1275
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1276
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1277
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1278
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1279
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1280
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1281
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1282
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1283
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1284
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1285
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1286
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FMUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1287
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$h1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0, $h1
+#
+# TESTGEND:           %2:fpr(s16) = COPY $h1
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1288
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$s1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0, $s1
+#
+# TESTGEND:           %2:fpr(s32) = COPY $s1
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1289
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1290
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1291
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1292
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1293
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1294
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FSUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1295
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_LSHR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1296
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1297
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1298
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1299
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1300
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1301
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_MUL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1302
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1303
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1304
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1305
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1306
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1307
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1308
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1309
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1310
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1311
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_OR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1312
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_SDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1313
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1314
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SHL %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1315
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1316
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1317
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1318
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1319
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1320
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1321
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1322
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1323
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1324
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_SUB %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1325
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_UDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1326
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_UDIV %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1327
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$w1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0, $w1
+#
+# TESTGEND:           %2:gpr(s32) = COPY $w1
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1328
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:         - { id: 2, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$x1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0, $x1
+#
+# TESTGEND:           %2:gpr(s64) = COPY $x1
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1329
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<8 x s8>) = COPY $d1
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1330
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<16 x s8>) = COPY $q1
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1331
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<4 x s16>) = COPY $d1
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1332
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(<2 x s32>) = COPY $d1
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1333
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$d1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0, $d1
+#
+# TESTGEND:           %2:fpr(s64) = COPY $d1
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1334
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<8 x s16>) = COPY $q1
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1335
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<4 x s32>) = COPY $q1
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1336
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:         - { id: 2, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:         - { reg: '$q1', virtual-reg: '%2' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0, $q1
+#
+# TESTGEND:           %2:fpr(<2 x s64>) = COPY $q1
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_XOR %1, %2
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1337
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1338
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1339
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1340
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1341
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1342
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1345
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1346
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1347
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1350
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1351
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1352
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1353
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1356
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1357
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1358
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1361
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1363
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1364
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1365
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_BITCAST %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1369
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1370
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1371
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1374
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1375
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1376
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1379
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1381
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1382
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1383
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1387
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1388
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1389
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1393
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1394
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1395
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1396
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1400
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1401
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1402
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1406
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1420
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1421
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1422
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1427
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1428
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1429
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_BITCAST %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1471
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1472
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1473
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1477
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1478
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1479
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1480
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1484
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(s128) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s128)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1485
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1486
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1487
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1489
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1491
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1492
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1493
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1495
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1497
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1498
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1499
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1501
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1502
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1504
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1505
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1507
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1508
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1510
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1537
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1538
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1539
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1540
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1543
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1544
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1545
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1546
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<16 x s8>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<16 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1549
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1563
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1564
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1565
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1566
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1570
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(s128) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(s128)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1571
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1572
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1573
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<16 x s8>) = G_BITCAST %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<16 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1577
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:gpr(s32) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1578
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s64) = G_BSWAP %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1579
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s32) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1580
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           %0:gpr(s64) = G_CONSTANT 1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1581
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s16) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1582
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s32) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1583
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s64) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1584
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1585
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1586
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1587
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1588
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FNEG %1
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1589
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s64) = G_FPEXT %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1590
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:fpr(s32) = G_FPEXT %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1591
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s64) = G_FPEXT %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1592
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1593
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1594
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1595
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1596
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1597
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1598
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1599
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_FPTOSI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1600
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FPTOSI %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1601
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FPTOSI %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1602
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1603
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1604
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1605
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s32) = G_FPTOUI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1606
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$h0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $h0
+#
+# TESTGEND:           %1:fpr(s16) = COPY $h0
+# TESTGEND:           %0:gpr(s64) = G_FPTOUI %1(s16)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1607
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s32) = G_FPTOUI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1608
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:gpr(s64) = G_FPTOUI %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1609
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s32) = G_FPTOUI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1610
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:gpr(s64) = G_FPTOUI %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1611
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FPTOUI %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1612
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_FPTOUI %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1613
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1614
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1615
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1616
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s16) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1617
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(s64) = COPY $d0
+# TESTGEND:           %0:fpr(s32) = G_FPTRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1618
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$s0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $s0
+#
+# TESTGEND:           %1:fpr(s32) = COPY $s0
+# TESTGEND:           %0:fpr(s16) = G_FPTRUNC %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1619
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1620
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1621
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1622
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1623
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1624
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s16) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1625
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s32) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1626
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s64) = G_SITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1627
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1628
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s32) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1629
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s64) = G_SITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1630
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_SITOFP %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1631
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_SITOFP %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1632
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1633
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1634
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1635
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s8>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1636
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1637
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1638
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: gpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:gpr(s32) = G_TRUNC %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1639
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s16) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1640
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s32) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1641
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$w0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $w0
+#
+# TESTGEND:           %1:gpr(s32) = COPY $w0
+# TESTGEND:           %0:fpr(s64) = G_UITOFP %1(s32)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1642
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s16) = G_UITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s16)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1643
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s32) = G_UITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s32)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1644
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: gpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$x0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $x0
+#
+# TESTGEND:           %1:gpr(s64) = COPY $x0
+# TESTGEND:           %0:fpr(s64) = G_UITOFP %1(s64)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(s64)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1645
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s16>) = G_UITOFP %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1646
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<8 x s16>) = COPY $q0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_UITOFP %1(<8 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1647
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1648
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<4 x s32>) = COPY $q0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1649
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$q0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $q0
+#
+# TESTGEND:           %1:fpr(<2 x s64>) = COPY $q0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1650
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<8 x s8>) = COPY $d0
+# TESTGEND:           %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<8 x s16>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1651
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<4 x s16>) = COPY $d0
+# TESTGEND:           %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<4 x s32>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1652
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       registers:
+# TESTGEND:         - { id: 0, class: fpr }
+# TESTGEND:         - { id: 1, class: fpr }
+# TESTGEND:       liveins:
+# TESTGEND:         - { reg: '$d0', virtual-reg: '%1' }
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           liveins: $d0
+#
+# TESTGEND:           %1:fpr(<2 x s32>) = COPY $d0
+# TESTGEND:           %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
+# TESTGEND:           $noreg = PATCHABLE_RET %0(<2 x s64>)
+#
+# TESTGEND:       ...
+# TESTGEND:       ---
+# TESTGEND-LABEL: name:            test_rule1653
+# TESTGEND:       alignment:       2
+# TESTGEND:       legalized:       true
+# TESTGEND:       regBankSelected: true
+# TESTGEND:       tracksRegLiveness: true
+# TESTGEND:       body:             |
+# TESTGEND:         bb.0.entry:
+# TESTGEND:           successors:
+#
+# TESTGEND:           G_BR %bb.0
+# TESTGEND:           $noreg = PATCHABLE_RET
+#
+# TESTGEND:       ...
Index: test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ /dev/null
@@ -1,4543 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \
-# RUN:     -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \
-# RUN:     -o - | FileCheck %s
----
-name:            test_rule14_id188_at_idx1067
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule14_id188_at_idx1067
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
-    $noreg = PATCHABLE_RET %0(s128)
-
-...
----
-name:            test_rule21_id2237_at_idx1449
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%0' }
-  - { reg: '$d1', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule21_id2237_at_idx1449
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d1
-    %0:fpr(<8 x s8>) = COPY $d0
-    G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule22_id2238_at_idx1505
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%0' }
-  - { reg: '$d1', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule22_id2238_at_idx1505
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d1
-    %0:fpr(<4 x s16>) = COPY $d0
-    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule27_id2243_at_idx1781
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%0' }
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule27_id2243_at_idx1781
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<4 x s32>) = COPY $q0
-    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule28_id2244_at_idx1837
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%0' }
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule28_id2244_at_idx1837
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<2 x s64>) = COPY $q0
-    G_STORE %0(<2 x s64>), %1(p0) :: (store 16)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule29_id2245_at_idx1893
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%0' }
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule29_id2245_at_idx1893
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<16 x s8>) = COPY $q0
-    G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule30_id2246_at_idx1949
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%0' }
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule30_id2246_at_idx1949
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<8 x s16>) = COPY $q0
-    G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule34_id2250_at_idx2173
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%0' }
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule34_id2250_at_idx2173
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(s128) = COPY $q0
-    G_STORE %0(s128), %1(p0) :: (store 16)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule92_id2150_at_idx7770
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-liveins:
-  - { reg: '$x0', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $x0
-
-    ; CHECK-LABEL: name: test_rule92_id2150_at_idx7770
-    ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]]
-    %2:gpr(p0) = COPY $x0
-    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
-    %1:gpr(s32) = G_ANYEXT %0(s1)
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule96_id2146_at_idx8070
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-liveins:
-  - { reg: '$x0', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $x0
-
-    ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070
-    ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]]
-    %2:gpr(p0) = COPY $x0
-    %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
-    %1:gpr(s32) = G_ZEXT %0(s1)
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule129_id2130_at_idx10828
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule129_id2130_at_idx10828
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule130_id2131_at_idx10884
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule130_id2131_at_idx10884
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule135_id2136_at_idx11160
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule135_id2136_at_idx11160
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule136_id2137_at_idx11216
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule136_id2137_at_idx11216
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule137_id2138_at_idx11272
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule137_id2138_at_idx11272
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16)
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule138_id2139_at_idx11328
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule138_id2139_at_idx11328
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16)
-    ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
-    %1:fpr(p0) = COPY $d0
-    %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule339_id2369_at_idx26608
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-  - { id: 5, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%3' }
-  - { reg: '$s1', virtual-reg: '%4' }
-  - { reg: '$s2', virtual-reg: '%5' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
-    %5:fpr(s32) = COPY $s2
-    %4:fpr(s32) = COPY $s1
-    %3:fpr(s32) = COPY $s0
-    %1:fpr(s32) = G_FNEG %5
-    %0:fpr(s32) = G_FNEG %4
-    %2:fpr(s32) = G_FMA %0, %3, %1
-    $noreg = PATCHABLE_RET %2(s32)
-
-...
----
-name:            test_rule340_id2370_at_idx26714
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-  - { id: 5, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-  - { reg: '$d2', virtual-reg: '%5' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
-    %5:fpr(s64) = COPY $d2
-    %4:fpr(s64) = COPY $d1
-    %3:fpr(s64) = COPY $d0
-    %1:fpr(s64) = G_FNEG %5
-    %0:fpr(s64) = G_FNEG %4
-    %2:fpr(s64) = G_FMA %0, %3, %1
-    $noreg = PATCHABLE_RET %2(s64)
-
-...
----
-name:            test_rule341_id2371_at_idx26820
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-  - { id: 5, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%3' }
-  - { reg: '$s1', virtual-reg: '%4' }
-  - { reg: '$s2', virtual-reg: '%5' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
-    %5:fpr(s32) = COPY $s2
-    %4:fpr(s32) = COPY $s1
-    %3:fpr(s32) = COPY $s0
-    %1:fpr(s32) = G_FNEG %5
-    %0:fpr(s32) = G_FNEG %4
-    %2:fpr(s32) = G_FMA %3, %0, %1
-    $noreg = PATCHABLE_RET %2(s32)
-
-...
----
-name:            test_rule342_id2372_at_idx26926
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-  - { id: 5, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-  - { reg: '$d2', virtual-reg: '%5' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
-    %5:fpr(s64) = COPY $d2
-    %4:fpr(s64) = COPY $d1
-    %3:fpr(s64) = COPY $d0
-    %1:fpr(s64) = G_FNEG %5
-    %0:fpr(s64) = G_FNEG %4
-    %2:fpr(s64) = G_FMA %3, %0, %1
-    $noreg = PATCHABLE_RET %2(s64)
-
-...
----
-name:            test_rule343_id1266_at_idx27032
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule343_id1266_at_idx27032
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
-    %4:fpr(<8 x s8>) = COPY $d1
-    %3:fpr(<8 x s8>) = COPY $d0
-    %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
-    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %2:fpr(<8 x s16>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
-
-...
----
-name:            test_rule344_id1268_at_idx27128
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule344_id1268_at_idx27128
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]
-    %4:fpr(<4 x s16>) = COPY $d1
-    %3:fpr(<4 x s16>) = COPY $d0
-    %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
-    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %2:fpr(<4 x s32>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
-
-...
----
-name:            test_rule345_id1270_at_idx27224
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule345_id1270_at_idx27224
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]
-    %4:fpr(<2 x s32>) = COPY $d1
-    %3:fpr(<2 x s32>) = COPY $d0
-    %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
-    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %2:fpr(<2 x s64>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
-
-...
----
-name:            test_rule346_id1326_at_idx27320
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule346_id1326_at_idx27320
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]
-    %4:fpr(<8 x s8>) = COPY $d1
-    %3:fpr(<8 x s8>) = COPY $d0
-    %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %2:fpr(<8 x s16>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
-
-...
----
-name:            test_rule347_id1328_at_idx27416
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule347_id1328_at_idx27416
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]
-    %4:fpr(<4 x s16>) = COPY $d1
-    %3:fpr(<4 x s16>) = COPY $d0
-    %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %2:fpr(<4 x s32>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
-
-...
----
-name:            test_rule348_id1330_at_idx27512
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule348_id1330_at_idx27512
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]
-    %4:fpr(<2 x s32>) = COPY $d1
-    %3:fpr(<2 x s32>) = COPY $d0
-    %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %2:fpr(<2 x s64>) = G_ADD %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
-
-...
----
-name:            test_rule349_id1308_at_idx27608
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule349_id1308_at_idx27608
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]
-    %4:fpr(<8 x s8>) = COPY $d1
-    %3:fpr(<8 x s8>) = COPY $d0
-    %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
-    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %2:fpr(<8 x s16>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
-
-...
----
-name:            test_rule350_id1310_at_idx27704
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule350_id1310_at_idx27704
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]
-    %4:fpr(<4 x s16>) = COPY $d1
-    %3:fpr(<4 x s16>) = COPY $d0
-    %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
-    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %2:fpr(<4 x s32>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
-
-...
----
-name:            test_rule351_id1312_at_idx27800
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule351_id1312_at_idx27800
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]
-    %4:fpr(<2 x s32>) = COPY $d1
-    %3:fpr(<2 x s32>) = COPY $d0
-    %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
-    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %2:fpr(<2 x s64>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
-
-...
----
-name:            test_rule352_id1356_at_idx27896
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule352_id1356_at_idx27896
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]
-    %4:fpr(<8 x s8>) = COPY $d1
-    %3:fpr(<8 x s8>) = COPY $d0
-    %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
-    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %2:fpr(<8 x s16>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<8 x s16>)
-
-...
----
-name:            test_rule353_id1358_at_idx27992
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule353_id1358_at_idx27992
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]
-    %4:fpr(<4 x s16>) = COPY $d1
-    %3:fpr(<4 x s16>) = COPY $d0
-    %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
-    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %2:fpr(<4 x s32>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<4 x s32>)
-
-...
----
-name:            test_rule354_id1360_at_idx28088
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%3' }
-  - { reg: '$d1', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule354_id1360_at_idx28088
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]
-    %4:fpr(<2 x s32>) = COPY $d1
-    %3:fpr(<2 x s32>) = COPY $d0
-    %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
-    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %2:fpr(<2 x s64>) = G_SUB %0, %1
-    $noreg = PATCHABLE_RET %2(<2 x s64>)
-
-...
----
-name:            test_rule928_id2367_at_idx60019
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%2' }
-  - { reg: '$s1', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule928_id2367_at_idx60019
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
-    %4:fpr(s32) = COPY $s2
-    %3:fpr(s32) = COPY $s1
-    %2:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FNEG %4
-    %1:fpr(s32) = G_FMA %0, %2, %3
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule929_id2368_at_idx60105
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule929_id2368_at_idx60105
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
-    %4:fpr(s64) = COPY $d2
-    %3:fpr(s64) = COPY $d1
-    %2:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FNEG %4
-    %1:fpr(s64) = G_FMA %0, %2, %3
-    $noreg = PATCHABLE_RET %1(s64)
-
-...
----
-name:            test_rule930_id2446_at_idx60191
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
-    %4:fpr(<2 x s32>) = COPY $d2
-    %3:fpr(<2 x s32>) = COPY $d1
-    %2:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FNEG %4
-    %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
-
-...
----
-name:            test_rule931_id2447_at_idx60277
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
-    %4:fpr(<4 x s32>) = COPY $q2
-    %3:fpr(<4 x s32>) = COPY $q1
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FNEG %4
-    %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule932_id2448_at_idx60363
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
-    %4:fpr(<2 x s64>) = COPY $q2
-    %3:fpr(<2 x s64>) = COPY $q1
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FNEG %4
-    %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule934_id429_at_idx60537
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%2' }
-  - { reg: '$s1', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule934_id429_at_idx60537
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
-    %4:fpr(s32) = COPY $s2
-    %3:fpr(s32) = COPY $s1
-    %2:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FNEG %4
-    %1:fpr(s32) = G_FMA %2, %0, %3
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule935_id430_at_idx60625
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule935_id430_at_idx60625
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
-    %4:fpr(s64) = COPY $d2
-    %3:fpr(s64) = COPY $d1
-    %2:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FNEG %4
-    %1:fpr(s64) = G_FMA %2, %0, %3
-    $noreg = PATCHABLE_RET %1(s64)
-
-...
----
-name:            test_rule938_id899_at_idx60889
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule938_id899_at_idx60889
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
-    %4:fpr(<2 x s32>) = COPY $d2
-    %3:fpr(<2 x s32>) = COPY $d1
-    %2:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FNEG %4
-    %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
-    $noreg = PATCHABLE_RET %1(<2 x s32>)
-
-...
----
-name:            test_rule939_id900_at_idx60977
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule939_id900_at_idx60977
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
-    %4:fpr(<4 x s32>) = COPY $q2
-    %3:fpr(<4 x s32>) = COPY $q1
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FNEG %4
-    %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule940_id901_at_idx61065
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule940_id901_at_idx61065
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
-    %4:fpr(<2 x s64>) = COPY $q2
-    %3:fpr(<2 x s64>) = COPY $q1
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FNEG %4
-    %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule942_id435_at_idx61241
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%2' }
-  - { reg: '$s1', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule942_id435_at_idx61241
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
-    %4:fpr(s32) = COPY $s2
-    %3:fpr(s32) = COPY $s1
-    %2:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FNEG %4
-    %1:fpr(s32) = G_FMA %2, %3, %0
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule943_id436_at_idx61329
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule943_id436_at_idx61329
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
-    %4:fpr(s64) = COPY $d2
-    %3:fpr(s64) = COPY $d1
-    %2:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FNEG %4
-    %1:fpr(s64) = G_FMA %2, %3, %0
-    $noreg = PATCHABLE_RET %1(s64)
-
-...
----
-name:            test_rule944_id3803_at_idx61417
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule944_id3803_at_idx61417
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]]
-    %4:fpr(<8 x s8>) = COPY $d2
-    %3:fpr(<8 x s8>) = COPY $d1
-    %2:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_MUL %3, %4
-    %1:fpr(<8 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
-
-...
----
-name:            test_rule945_id3804_at_idx61505
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule945_id3804_at_idx61505
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]]
-    %4:fpr(<16 x s8>) = COPY $q2
-    %3:fpr(<16 x s8>) = COPY $q1
-    %2:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_MUL %3, %4
-    %1:fpr(<16 x s8>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
-
-...
----
-name:            test_rule946_id3805_at_idx61593
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule946_id3805_at_idx61593
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]]
-    %4:fpr(<4 x s16>) = COPY $d2
-    %3:fpr(<4 x s16>) = COPY $d1
-    %2:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_MUL %3, %4
-    %1:fpr(<4 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
-
-...
----
-name:            test_rule947_id3806_at_idx61681
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule947_id3806_at_idx61681
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]]
-    %4:fpr(<8 x s16>) = COPY $q2
-    %3:fpr(<8 x s16>) = COPY $q1
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_MUL %3, %4
-    %1:fpr(<8 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule950_id3869_at_idx61945
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule950_id3869_at_idx61945
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule951_id3871_at_idx62021
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule951_id3871_at_idx62021
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule952_id3873_at_idx62097
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule952_id3873_at_idx62097
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule953_id3887_at_idx62173
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule953_id3887_at_idx62173
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule954_id3889_at_idx62249
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule954_id3889_at_idx62249
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule955_id3891_at_idx62325
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule955_id3891_at_idx62325
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_ADD %0, %2
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule956_id927_at_idx62401
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule956_id927_at_idx62401
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]]
-    %4:fpr(<8 x s8>) = COPY $d2
-    %3:fpr(<8 x s8>) = COPY $d1
-    %2:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_MUL %3, %4
-    %1:fpr(<8 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
-
-...
----
-name:            test_rule957_id928_at_idx62489
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule957_id928_at_idx62489
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]]
-    %4:fpr(<16 x s8>) = COPY $q2
-    %3:fpr(<16 x s8>) = COPY $q1
-    %2:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_MUL %3, %4
-    %1:fpr(<16 x s8>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
-
-...
----
-name:            test_rule958_id929_at_idx62577
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule958_id929_at_idx62577
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]]
-    %4:fpr(<4 x s16>) = COPY $d2
-    %3:fpr(<4 x s16>) = COPY $d1
-    %2:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_MUL %3, %4
-    %1:fpr(<4 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
-
-...
----
-name:            test_rule959_id930_at_idx62665
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule959_id930_at_idx62665
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]]
-    %4:fpr(<8 x s16>) = COPY $q2
-    %3:fpr(<8 x s16>) = COPY $q1
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_MUL %3, %4
-    %1:fpr(<8 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule962_id1272_at_idx62929
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule962_id1272_at_idx62929
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule963_id1274_at_idx63005
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule963_id1274_at_idx63005
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule964_id1276_at_idx63081
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule964_id1276_at_idx63081
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule965_id1332_at_idx63157
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule965_id1332_at_idx63157
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule966_id1334_at_idx63233
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule966_id1334_at_idx63233
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule967_id1336_at_idx63309
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule967_id1336_at_idx63309
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_ADD %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule977_id933_at_idx64051
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule977_id933_at_idx64051
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLSv8i8_:%[0-9]+]]:fpr64 = MLSv8i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i8_]]
-    %4:fpr(<8 x s8>) = COPY $d2
-    %3:fpr(<8 x s8>) = COPY $d1
-    %2:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_MUL %3, %4
-    %1:fpr(<8 x s8>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s8>)
-
-...
----
-name:            test_rule978_id934_at_idx64139
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule978_id934_at_idx64139
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLSv16i8_:%[0-9]+]]:fpr128 = MLSv16i8 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLSv16i8_]]
-    %4:fpr(<16 x s8>) = COPY $q2
-    %3:fpr(<16 x s8>) = COPY $q1
-    %2:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_MUL %3, %4
-    %1:fpr(<16 x s8>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<16 x s8>)
-
-...
----
-name:            test_rule979_id935_at_idx64227
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule979_id935_at_idx64227
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MLSv4i16_:%[0-9]+]]:fpr64 = MLSv4i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLSv4i16_]]
-    %4:fpr(<4 x s16>) = COPY $d2
-    %3:fpr(<4 x s16>) = COPY $d1
-    %2:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_MUL %3, %4
-    %1:fpr(<4 x s16>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s16>)
-
-...
----
-name:            test_rule980_id936_at_idx64315
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$q1', virtual-reg: '%3' }
-  - { reg: '$q2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule980_id936_at_idx64315
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MLSv8i16_:%[0-9]+]]:fpr128 = MLSv8i16 [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i16_]]
-    %4:fpr(<8 x s16>) = COPY $q2
-    %3:fpr(<8 x s16>) = COPY $q1
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_MUL %3, %4
-    %1:fpr(<8 x s16>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule983_id1314_at_idx64579
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule983_id1314_at_idx64579
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule984_id1316_at_idx64655
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule984_id1316_at_idx64655
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule985_id1318_at_idx64731
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule985_id1318_at_idx64731
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule986_id1362_at_idx64807
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule986_id1362_at_idx64807
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]
-    %3:fpr(<8 x s8>) = COPY $d0
-    %2:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
-    %1:fpr(<8 x s16>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<8 x s16>)
-
-...
----
-name:            test_rule987_id1364_at_idx64883
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule987_id1364_at_idx64883
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]
-    %3:fpr(<4 x s16>) = COPY $d0
-    %2:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
-    %1:fpr(<4 x s32>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<4 x s32>)
-
-...
----
-name:            test_rule988_id1366_at_idx64959
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%2' }
-  - { reg: '$d0', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $d0
-
-    ; CHECK-LABEL: name: test_rule988_id1366_at_idx64959
-    ; CHECK: liveins: $q0, $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]
-    %3:fpr(<2 x s32>) = COPY $d0
-    %2:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
-    %1:fpr(<2 x s64>) = G_SUB %2, %0
-    $noreg = PATCHABLE_RET %1(<2 x s64>)
-
-...
----
-name:            test_rule990_id432_at_idx65123
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%2' }
-  - { reg: '$s1', virtual-reg: '%3' }
-  - { reg: '$s2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1, $s2
-
-    ; CHECK-LABEL: name: test_rule990_id432_at_idx65123
-    ; CHECK: liveins: $s0, $s1, $s2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
-    %4:fpr(s32) = COPY $s2
-    %3:fpr(s32) = COPY $s1
-    %2:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FMA %2, %3, %4
-    %1:fpr(s32) = G_FNEG %0
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule991_id433_at_idx65211
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-  - { reg: '$d2', virtual-reg: '%4' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule991_id433_at_idx65211
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
-    %4:fpr(s64) = COPY $d2
-    %3:fpr(s64) = COPY $d1
-    %2:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FMA %2, %3, %4
-    %1:fpr(s64) = G_FNEG %0
-    $noreg = PATCHABLE_RET %1(s64)
-
-...
----
-name:            test_rule993_id420_at_idx65375
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%2' }
-  - { reg: '$s1', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $s0, $s1
-
-    ; CHECK-LABEL: name: test_rule993_id420_at_idx65375
-    ; CHECK: liveins: $s0, $s1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]]
-    %3:fpr(s32) = COPY $s1
-    %2:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FMUL %2, %3
-    %1:fpr(s32) = G_FNEG %0
-    $noreg = PATCHABLE_RET %1(s32)
-
-...
----
-name:            test_rule994_id421_at_idx65451
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%2' }
-  - { reg: '$d1', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule994_id421_at_idx65451
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]]
-    %3:fpr(s64) = COPY $d1
-    %2:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FMUL %2, %3
-    %1:fpr(s64) = G_FNEG %0
-    $noreg = PATCHABLE_RET %1(s64)
-
-...
----
-name:            test_rule1230_id2969_at_idx81784
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-liveins:
-  - { reg: '$x0', virtual-reg: '%0' }
-  - { reg: '$x1', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $x0, $x1
-
-    ; CHECK-LABEL: name: test_rule1230_id2969_at_idx81784
-    ; CHECK: liveins: $x0, $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
-    ; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store 8)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:gpr(p0) = COPY $x1
-    %0:gpr(<8 x s8>) = COPY $x0
-    G_STORE %0(<8 x s8>), %1(p0) :: (store 8)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule1231_id2970_at_idx81816
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-liveins:
-  - { reg: '$x0', virtual-reg: '%0' }
-  - { reg: '$x1', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $x0, $x1
-
-    ; CHECK-LABEL: name: test_rule1231_id2970_at_idx81816
-    ; CHECK: liveins: $x0, $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
-    ; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store 8)
-    ; CHECK: $noreg = PATCHABLE_RET
-    %1:gpr(p0) = COPY $x1
-    %0:gpr(<4 x s16>) = COPY $x0
-    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
-    $noreg = PATCHABLE_RET
-
-...
----
-name:            test_rule1239_id894_at_idx82201
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-  - { reg: '$d2', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1, $d2
-
-    ; CHECK-LABEL: name: test_rule1239_id894_at_idx82201
-    ; CHECK: liveins: $d0, $d1, $d2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
-    %3:fpr(<2 x s32>) = COPY $d2
-    %2:fpr(<2 x s32>) = COPY $d1
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1240_id895_at_idx82269
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-  - { reg: '$q2', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule1240_id895_at_idx82269
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
-    %3:fpr(<4 x s32>) = COPY $q2
-    %2:fpr(<4 x s32>) = COPY $q1
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1241_id896_at_idx82337
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-  - { reg: '$q2', virtual-reg: '%3' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1, $q2
-
-    ; CHECK-LABEL: name: test_rule1241_id896_at_idx82337
-    ; CHECK: liveins: $q0, $q1, $q2
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
-    %3:fpr(<2 x s64>) = COPY $q2
-    %2:fpr(<2 x s64>) = COPY $q1
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1244_id751_at_idx82487
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1244_id751_at_idx82487
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_ADD %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1245_id752_at_idx82530
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1245_id752_at_idx82530
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_ADD %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1246_id753_at_idx82573
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1246_id753_at_idx82573
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_ADD %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1247_id754_at_idx82616
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1247_id754_at_idx82616
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_ADD %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1254_id1162_at_idx82913
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1254_id1162_at_idx82913
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1255_id1163_at_idx82956
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1255_id1163_at_idx82956
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1256_id1751_at_idx82999
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1256_id1751_at_idx82999
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1259_id1754_at_idx83128
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1259_id1754_at_idx83128
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_AND %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1268_id829_at_idx83513
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1268_id829_at_idx83513
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]]
-    %2:fpr(<2 x s32>) = COPY $d1
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FADD %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1269_id830_at_idx83556
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1269_id830_at_idx83556
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]]
-    %2:fpr(<4 x s32>) = COPY $q1
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FADD %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1270_id831_at_idx83599
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1270_id831_at_idx83599
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]]
-    %2:fpr(<2 x s64>) = COPY $q1
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FADD %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1276_id849_at_idx83857
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1276_id849_at_idx83857
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
-    %2:fpr(<2 x s32>) = COPY $d1
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FDIV %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1277_id850_at_idx83900
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1277_id850_at_idx83900
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
-    %2:fpr(<4 x s32>) = COPY $q1
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FDIV %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1278_id851_at_idx83943
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1278_id851_at_idx83943
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
-    %2:fpr(<2 x s64>) = COPY $q1
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FDIV %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1284_id909_at_idx84201
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1284_id909_at_idx84201
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]]
-    %2:fpr(<2 x s32>) = COPY $d1
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FMUL %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1285_id910_at_idx84244
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1285_id910_at_idx84244
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]]
-    %2:fpr(<4 x s32>) = COPY $q1
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FMUL %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1286_id911_at_idx84287
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1286_id911_at_idx84287
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]]
-    %2:fpr(<2 x s64>) = COPY $q1
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FMUL %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1292_id924_at_idx84545
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1292_id924_at_idx84545
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
-    %2:fpr(<2 x s32>) = COPY $d1
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FSUB %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1293_id925_at_idx84588
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1293_id925_at_idx84588
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
-    %2:fpr(<4 x s32>) = COPY $q1
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FSUB %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1294_id926_at_idx84631
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1294_id926_at_idx84631
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
-    %2:fpr(<2 x s64>) = COPY $q1
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FSUB %1, %2
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1296_id939_at_idx84715
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1296_id939_at_idx84715
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MULv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1297_id940_at_idx84758
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1297_id940_at_idx84758
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MULv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1298_id941_at_idx84801
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1298_id941_at_idx84801
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MULv4i16_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1299_id942_at_idx84844
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1299_id942_at_idx84844
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[MULv8i16_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_MUL %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1304_id1174_at_idx85055
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1304_id1174_at_idx85055
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_OR %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1305_id1175_at_idx85098
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1305_id1175_at_idx85098
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_OR %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1306_id1827_at_idx85141
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1306_id1827_at_idx85141
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_OR %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1309_id1830_at_idx85270
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1309_id1830_at_idx85270
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_OR %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1315_id1051_at_idx85522
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1315_id1051_at_idx85522
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_SUB %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1316_id1052_at_idx85565
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1316_id1052_at_idx85565
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_SUB %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1317_id1053_at_idx85608
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1317_id1053_at_idx85608
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_SUB %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1318_id1054_at_idx85651
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1318_id1054_at_idx85651
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_SUB %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1329_id1170_at_idx86118
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1329_id1170_at_idx86118
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]]
-    %2:fpr(<8 x s8>) = COPY $d1
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s8>) = G_XOR %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1330_id1171_at_idx86161
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1330_id1171_at_idx86161
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]]
-    %2:fpr(<16 x s8>) = COPY $q1
-    %1:fpr(<16 x s8>) = COPY $q0
-    %0:fpr(<16 x s8>) = G_XOR %1, %2
-    $noreg = PATCHABLE_RET %0(<16 x s8>)
-
-...
----
-name:            test_rule1331_id1791_at_idx86204
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-  - { reg: '$d1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $d0, $d1
-
-    ; CHECK-LABEL: name: test_rule1331_id1791_at_idx86204
-    ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]]
-    %2:fpr(<4 x s16>) = COPY $d1
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s16>) = G_XOR %1, %2
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1334_id1794_at_idx86333
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-  - { reg: '$q1', virtual-reg: '%2' }
-body:             |
-  bb.0.entry:
-    liveins: $q0, $q1
-
-    ; CHECK-LABEL: name: test_rule1334_id1794_at_idx86333
-    ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]]
-    %2:fpr(<8 x s16>) = COPY $q1
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s16>) = G_XOR %1, %2
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1337_id2925_at_idx86462
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1337_id2925_at_idx86462
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1338_id2928_at_idx86507
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1338_id2928_at_idx86507
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1339_id2931_at_idx86552
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1339_id2931_at_idx86552
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1582_id372_at_idx97075
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$s0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $s0
-
-    ; CHECK-LABEL: name: test_rule1582_id372_at_idx97075
-    ; CHECK: liveins: $s0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNEGSr]]
-    %1:fpr(s32) = COPY $s0
-    %0:fpr(s32) = G_FNEG %1
-    $noreg = PATCHABLE_RET %0(s32)
-
-...
----
-name:            test_rule1583_id373_at_idx97110
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1583_id373_at_idx97110
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNEGDr]]
-    %1:fpr(s64) = COPY $d0
-    %0:fpr(s64) = G_FNEG %1
-    $noreg = PATCHABLE_RET %0(s64)
-
-...
----
-name:            test_rule1586_id597_at_idx97215
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1586_id597_at_idx97215
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FNEG %1
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1587_id598_at_idx97250
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1587_id598_at_idx97250
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNEGv4f32_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FNEG %1
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1588_id599_at_idx97285
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1588_id599_at_idx97285
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f64_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FNEG %1
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1592_id2383_at_idx97425
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1593_id2385_at_idx97458
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1602_id587_at_idx97771
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1602_id587_at_idx97771
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1603_id588_at_idx97806
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1603_id588_at_idx97806
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1604_id589_at_idx97841
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1604_id589_at_idx97841
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1613_id592_at_idx98156
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1613_id592_at_idx98156
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1614_id593_at_idx98191
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1614_id593_at_idx98191
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1615_id594_at_idx98226
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1615_id594_at_idx98226
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1619_id2389_at_idx98366
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1620_id2390_at_idx98399
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1621_id2923_at_idx98432
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1621_id2923_at_idx98432
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]]
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1622_id2926_at_idx98477
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1622_id2926_at_idx98477
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]]
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1623_id2929_at_idx98522
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1623_id2929_at_idx98522
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1632_id687_at_idx98847
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1632_id687_at_idx98847
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1633_id688_at_idx98882
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1633_id688_at_idx98882
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1634_id689_at_idx98917
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1634_id689_at_idx98917
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1635_id748_at_idx98952
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1635_id748_at_idx98952
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[XTNv8i8_]]
-    %1:fpr(<8 x s16>) = COPY $q0
-    %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)
-    $noreg = PATCHABLE_RET %0(<8 x s8>)
-
-...
----
-name:            test_rule1636_id749_at_idx98987
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1636_id749_at_idx98987
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[XTNv4i16_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s16>)
-
-...
----
-name:            test_rule1637_id750_at_idx99022
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1637_id750_at_idx99022
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[XTNv2i32_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1647_id731_at_idx99386
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1647_id731_at_idx99386
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s32>)
-
-...
----
-name:            test_rule1648_id732_at_idx99421
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1648_id732_at_idx99421
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
-    %1:fpr(<4 x s32>) = COPY $q0
-    %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1649_id733_at_idx99456
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$q0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $q0
-
-    ; CHECK-LABEL: name: test_rule1649_id733_at_idx99456
-    ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
-    ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
-    %1:fpr(<2 x s64>) = COPY $q0
-    %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...
----
-name:            test_rule1650_id2924_at_idx99491
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1650_id2924_at_idx99491
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
-    %1:fpr(<8 x s8>) = COPY $d0
-    %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
-    $noreg = PATCHABLE_RET %0(<8 x s16>)
-
-...
----
-name:            test_rule1651_id2927_at_idx99536
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1651_id2927_at_idx99536
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
-    %1:fpr(<4 x s16>) = COPY $d0
-    %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
-    $noreg = PATCHABLE_RET %0(<4 x s32>)
-
-...
----
-name:            test_rule1652_id2930_at_idx99581
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-liveins:
-  - { reg: '$d0', virtual-reg: '%1' }
-body:             |
-  bb.0.entry:
-    liveins: $d0
-
-    ; CHECK-LABEL: name: test_rule1652_id2930_at_idx99581
-    ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
-    ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
-    %1:fpr(<2 x s32>) = COPY $d0
-    %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
-    $noreg = PATCHABLE_RET %0(<2 x s64>)
-
-...