Index: include/llvm/CodeGen/MachineRegisterInfo.h =================================================================== --- include/llvm/CodeGen/MachineRegisterInfo.h +++ include/llvm/CodeGen/MachineRegisterInfo.h @@ -20,6 +20,7 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringSet.h" #include "llvm/ADT/iterator_range.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/LowLevelType.h" @@ -75,6 +76,13 @@ VirtReg2IndexFunctor> VRegInfo; + /// Map for recovering vreg name from vreg number. + /// This map is used by the MIR Printer. + IndexedMap VReg2Name; + + /// StringSet that is used to unique vreg names. + StringSet<> VRegNames; + /// The flag is true upon \p UpdatedCSRs initialization /// and false otherwise. bool IsUpdatedCSRsInitialized; @@ -418,6 +426,20 @@ /// specified register (it may be live-in). bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } + StringRef getVRegName(unsigned Reg) const { + return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; + } + + void insertVRegByName(StringRef Name, unsigned Reg) { + assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) && + "Named VRegs Must be Unique."); + if (!Name.empty()) { + VRegNames.insert(Name); + VReg2Name.grow(Reg); + VReg2Name[Reg] = Name.str(); + } + } + /// Return true if there is exactly one operand defining the specified /// register. bool hasOneDef(unsigned RegNo) const { @@ -722,7 +744,7 @@ /// temporarily while constructing machine instructions. Most operations are /// undefined on an incomplete register until one of setRegClass(), /// setRegBank() or setSize() has been called on it. - unsigned createIncompleteVirtualRegister(); + unsigned createIncompleteVirtualRegister(StringRef Name = ""); /// getNumVirtRegs - Return the number of virtual registers created. unsigned getNumVirtRegs() const { return VRegInfo.size(); } Index: include/llvm/CodeGen/TargetRegisterInfo.h =================================================================== --- include/llvm/CodeGen/TargetRegisterInfo.h +++ include/llvm/CodeGen/TargetRegisterInfo.h @@ -1161,7 +1161,8 @@ /// /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, - unsigned SubRegIdx = 0); + unsigned SubRegIdx = 0, + const MachineRegisterInfo *MRI = nullptr); /// Create Printable object to print register units on a \ref raw_ostream. /// Index: lib/CodeGen/MIRParser/MILexer.h =================================================================== --- lib/CodeGen/MIRParser/MILexer.h +++ lib/CodeGen/MIRParser/MILexer.h @@ -118,6 +118,7 @@ Identifier, IntegerType, NamedRegister, + NamedVirtualRegister, MachineBasicBlockLabel, MachineBasicBlock, PointerType, @@ -170,7 +171,7 @@ bool isRegister() const { return Kind == NamedRegister || Kind == underscore || - Kind == VirtualRegister; + Kind == NamedVirtualRegister || Kind == VirtualRegister; } bool isRegisterFlag() const { Index: lib/CodeGen/MIRParser/MILexer.cpp =================================================================== --- lib/CodeGen/MIRParser/MILexer.cpp +++ lib/CodeGen/MIRParser/MILexer.cpp @@ -410,6 +410,16 @@ return isIdentifierChar(C) && C != '.'; } +static Cursor lexNamedVirtualRegister(Cursor C, MIToken &Token) { + Cursor Range = C; + C.advance(); // Skip '%' + while (isRegisterChar(C.peek())) + C.advance(); + Token.reset(MIToken::NamedVirtualRegister, Range.upto(C)) + .setStringValue(Range.upto(C).drop_front(1)); // Drop the '%' + return C; +} + static Cursor maybeLexRegister(Cursor C, MIToken &Token, ErrorCallbackType ErrorCallback) { if (C.peek() != '%' && C.peek() != '$') @@ -419,7 +429,9 @@ if (isdigit(C.peek(1))) return lexVirtualRegister(C, Token); - // ErrorCallback(Token.location(), "Named vregs are not yet supported."); + if (isRegisterChar(C.peek(1))) + return lexNamedVirtualRegister(C, Token); + return None; } Index: lib/CodeGen/MIRParser/MIParser.h =================================================================== --- lib/CodeGen/MIRParser/MIParser.h +++ lib/CodeGen/MIRParser/MIParser.h @@ -56,6 +56,7 @@ DenseMap MBBSlots; DenseMap VRegInfos; + StringMap VRegInfosNamed; DenseMap FixedStackObjectSlots; DenseMap StackObjectSlots; DenseMap ConstantPoolSlots; @@ -67,6 +68,7 @@ const Name2RegBankMap &Names2RegBanks); VRegInfo &getVRegInfo(unsigned VReg); + VRegInfo &getVRegInfoNamed(StringRef RegName); }; /// Parse the machine basic block definitions, and skip the machine Index: lib/CodeGen/MIRParser/MIParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIParser.cpp +++ lib/CodeGen/MIRParser/MIParser.cpp @@ -98,6 +98,18 @@ return *I.first->second; } +VRegInfo &PerFunctionMIParsingState::getVRegInfoNamed(StringRef RegName) { + assert(RegName != "" && "Expected named reg."); + + auto I = VRegInfosNamed.insert(std::make_pair(RegName.str(), nullptr)); + if (I.second) { + VRegInfo *Info = new (Allocator) VRegInfo; + Info->VReg = MF.getRegInfo().createIncompleteVirtualRegister(RegName); + I.first->second = Info; + } + return *I.first->second; +} + namespace { /// A wrapper struct around the 'MachineOperand' struct that includes a source @@ -182,6 +194,7 @@ bool parseNamedRegister(unsigned &Reg); bool parseVirtualRegister(VRegInfo *&Info); + bool parseNamedVirtualRegister(VRegInfo *&Info); bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo); bool parseRegisterFlag(unsigned &Flags); bool parseRegisterClassOrBank(VRegInfo &RegInfo); @@ -949,7 +962,18 @@ return false; } +bool MIParser::parseNamedVirtualRegister(VRegInfo *&Info) { + assert(Token.is(MIToken::NamedVirtualRegister) && "Expected NamedVReg token"); + StringRef Name = Token.stringValue(); + // TODO: Check that the VReg name is not the same as a physical register name. + // If it is, then print a warning (when warnings are implemented). + Info = &PFS.getVRegInfoNamed(Name); + return false; +} + bool MIParser::parseVirtualRegister(VRegInfo *&Info) { + if (Token.is(MIToken::NamedVirtualRegister)) + return parseNamedVirtualRegister(Info); assert(Token.is(MIToken::VirtualRegister) && "Needs VirtualRegister token"); unsigned ID; if (getUnsigned(ID)) @@ -965,6 +989,7 @@ return false; case MIToken::NamedRegister: return parseNamedRegister(Reg); + case MIToken::NamedVirtualRegister: case MIToken::VirtualRegister: if (parseVirtualRegister(Info)) return true; @@ -1952,6 +1977,7 @@ case MIToken::underscore: case MIToken::NamedRegister: case MIToken::VirtualRegister: + case MIToken::NamedVirtualRegister: return parseRegisterOperand(Dest, TiedDefIdx); case MIToken::IntegerLiteral: return parseImmediateOperand(Dest); Index: lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIRParser.cpp +++ lib/CodeGen/MIRParser/MIRParser.cpp @@ -512,13 +512,12 @@ MachineRegisterInfo &MRI = MF.getRegInfo(); bool Error = false; // Create VRegs - for (auto P : PFS.VRegInfos) { - const VRegInfo &Info = *P.second; + auto populateVRegInfo = [&] (const VRegInfo &Info, StringRef Name) { unsigned Reg = Info.VReg; switch (Info.Kind) { case VRegInfo::UNKNOWN: error(Twine("Cannot determine class/bank of virtual register ") + - Twine(P.first) + " in function '" + MF.getName() + "'"); + Twine(Name) + " in function '" + MF.getName() + "'"); Error = true; break; case VRegInfo::NORMAL: @@ -532,6 +531,18 @@ MRI.setRegBank(Reg, *Info.D.RegBank); break; } + }; + + for (auto I = PFS.VRegInfosNamed.begin(), E = PFS.VRegInfosNamed.end(); + I != E; I++) { + const VRegInfo &Info = *I->second; + StringRef Name = I->first(); + populateVRegInfo(Info, Name); + } + + for (auto P : PFS.VRegInfos) { + const VRegInfo &Info = *P.second; + populateVRegInfo(Info, ""); } // Compute MachineRegisterInfo::UsedPhysRegMask Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -267,6 +267,8 @@ unsigned Reg = TargetRegisterInfo::index2VirtReg(I); yaml::VirtualRegisterDefinition VReg; VReg.ID = I; + if (RegInfo.getVRegName(Reg) != "") + continue; ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); unsigned PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) Index: lib/CodeGen/MachineOperand.cpp =================================================================== --- lib/CodeGen/MachineOperand.cpp +++ lib/CodeGen/MachineOperand.cpp @@ -739,7 +739,15 @@ OS << "debug-use "; if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable()) OS << "renamable "; - OS << printReg(Reg, TRI); + + const MachineRegisterInfo *MRI = nullptr; + if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (const MachineFunction *MF = getMFIfAvailable(*this)) { + MRI = &MF->getRegInfo(); + } + } + + OS << printReg(Reg, TRI, 0, MRI); // Print the sub register. if (unsigned SubReg = getSubReg()) { if (TRI) Index: lib/CodeGen/MachineRegisterInfo.cpp =================================================================== --- lib/CodeGen/MachineRegisterInfo.cpp +++ lib/CodeGen/MachineRegisterInfo.cpp @@ -150,10 +150,11 @@ return true; } -unsigned MachineRegisterInfo::createIncompleteVirtualRegister() { +unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); VRegInfo.grow(Reg); RegAllocHints.grow(Reg); + insertVRegByName(Name, Reg); return Reg; } Index: lib/CodeGen/TargetRegisterInfo.cpp =================================================================== --- lib/CodeGen/TargetRegisterInfo.cpp +++ lib/CodeGen/TargetRegisterInfo.cpp @@ -86,14 +86,20 @@ namespace llvm { Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, - unsigned SubIdx) { - return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { + unsigned SubIdx, const MachineRegisterInfo *MRI) { + return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { if (!Reg) OS << "$noreg"; else if (TargetRegisterInfo::isStackSlot(Reg)) OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); - else if (TargetRegisterInfo::isVirtualRegister(Reg)) - OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); + else if (TargetRegisterInfo::isVirtualRegister(Reg)) { + StringRef Name = MRI ? MRI->getVRegName(Reg) : ""; + if (Name != "") { + OS << '%' << Name; + } else { + OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); + } + } else if (!TRI) OS << '$' << "physreg" << Reg; else if (Reg < TRI->getNumRegs()) { Index: test/CodeGen/MIR/AArch64/namedvregs.mir =================================================================== --- /dev/null +++ test/CodeGen/MIR/AArch64/namedvregs.mir @@ -0,0 +1,26 @@ +# RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -run-pass none %s | FileCheck %s +... +--- +name: namedVRegFunc +body: | + bb.0: + liveins: $x0, $w0, $d0, $d1 + %0:fpr64 = COPY $d0 + %1:fpr64 = COPY $d1 + + ;CHECK: %foo:gpr32 = COPY $w0 + ;CHECK: %bar:gpr32 = COPY $x0 + ;CHECK: %foobar:gpr32 = COPY %foo + ;CHECK: COPY %foobar + ;CHECK: %baz:gpr32 = COPY + ;CHECK: $w0 = COPY %baz + + %foo:gpr32 = COPY $w0 + %bar:gpr32 = COPY $x0 + %foobar:gpr32 = COPY %foo + %2:gpr32 = COPY %foobar + %baz:gpr32 = COPY %2 + $w0 = COPY %baz + RET_ReallyLR implicit $w0 + +...