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Differential D43807

ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
ClosedPublic

Authored by pcc on Feb 26 2018, 9:46 PM.

Details

Reviewers
olista01
efriedma
t.p.northover
Commits
rGe8436e863154: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
rL326226: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

Diff Detail

Repository
rL LLVM

Event Timeline

pcc created this revision.Feb 26 2018, 9:46 PM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, srhines. · View Herald TranscriptFeb 26 2018, 9:46 PM
Harbormaster completed remote builds in B15460: Diff 136035.Feb 26 2018, 9:48 PM
olista01 accepted this revision.Feb 27 2018, 4:13 AM

LGTM, thanks.

This revision is now accepted and ready to land.Feb 27 2018, 4:13 AM
Closed by commit rL326226: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. (authored by pcc). · Explain WhyFeb 27 2018, 11:03 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
3 lines
test/
CodeGen/
Thumb2/
11 lines

Diff 136110

llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Show First 20 Lines • Show All 483 Lines • ▼ Show 20 Linesbool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
// Memory operands in inline assembly always use AddrModeT2_i12. // Memory operands in inline assembly always use AddrModeT2_i12.
if (Opcode == ARM::INLINEASM) if (Opcode == ARM::INLINEASM)
AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
Offset += MI.getOperand(FrameRegIdx+1).getImm(); Offset += MI.getOperand(FrameRegIdx+1).getImm();
unsigned PredReg; unsigned PredReg;
if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) { if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
!MI.definesRegister(ARM::CPSR)) {
// Turn it into a move. // Turn it into a move.
MI.setDesc(TII.get(ARM::tMOVr)); MI.setDesc(TII.get(ARM::tMOVr));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
// Remove offset and remaining explicit predicate operands. // Remove offset and remaining explicit predicate operands.
do MI.RemoveOperand(FrameRegIdx+1); do MI.RemoveOperand(FrameRegIdx+1);
while (MI.getNumOperands() > FrameRegIdx+1); while (MI.getNumOperands() > FrameRegIdx+1);
MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI); MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
MIB.add(predOps(ARMCC::AL)); MIB.add(predOps(ARMCC::AL));
▲ Show 20 Lines • Show All 178 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/cmp-frame.ll

; RUN: llc < %s | FileCheck %s
target triple = "thumbv7-linux-androideabi"
define i1 @f() {
%a = alloca i8*
; CHECK: adds.w r0, sp, #0
; CHECK: it ne
%cmp = icmp ne i8** %a, null
ret i1 %cmp
}