Index: docs/AMDGPUUsage.rst =================================================================== --- docs/AMDGPUUsage.rst +++ docs/AMDGPUUsage.rst @@ -64,8 +64,7 @@ ============ ============================================================== Environment Description ============ ============================================================== - ** Defaults to ``opencl``. - ``opencl`` OpenCL compute kernel (see :ref:`amdgpu-opencl`). + ** Default. ``hcc`` AMD HC language compute kernel (see :ref:`amdgpu-hcc`). ============ ============================================================== @@ -3782,9 +3781,6 @@ OpenCL ------ -When generating code for the OpenCL language the target triple environment -should be ``opencl`` or ``amdgizcl`` (see :ref:`amdgpu-target-triples`). - When the language is OpenCL the following differences occur: 1. The OpenCL memory model is used (see :ref:`amdgpu-amdhsa-memory-model`). @@ -3804,7 +3800,7 @@ When generating code for the OpenCL language the target triple environment should be ``hcc`` (see :ref:`amdgpu-target-triples`). -When the language is OpenCL the following differences occur: +When the language is HCC the following differences occur: 1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`). Index: include/llvm/ADT/Triple.h =================================================================== --- include/llvm/ADT/Triple.h +++ include/llvm/ADT/Triple.h @@ -204,7 +204,6 @@ Cygnus, AMDOpenCL, CoreCLR, - OpenCL, Simulator, // Simulator variants of other systems, e.g., Apple's iOS LastEnvironmentType = Simulator }; Index: lib/Support/Triple.cpp =================================================================== --- lib/Support/Triple.cpp +++ lib/Support/Triple.cpp @@ -234,7 +234,6 @@ case Cygnus: return "cygnus"; case AMDOpenCL: return "amdopencl"; case CoreCLR: return "coreclr"; - case OpenCL: return "opencl"; case Simulator: return "simulator"; } @@ -525,7 +524,6 @@ .StartsWith("cygnus", Triple::Cygnus) .StartsWith("amdopencl", Triple::AMDOpenCL) .StartsWith("coreclr", Triple::CoreCLR) - .StartsWith("opencl", Triple::OpenCL) .StartsWith("simulator", Triple::Simulator) .Default(Triple::UnknownEnvironment); } Index: lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.h +++ lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -212,11 +212,6 @@ return TargetTriple.getOS() == Triple::Mesa3D; } - bool isOpenCLEnv() const { - return TargetTriple.getEnvironment() == Triple::OpenCL || - TargetTriple.getEnvironmentName() == "amdgizcl"; - } - bool isAmdPalOS() const { return TargetTriple.getOS() == Triple::AMDPAL; } @@ -537,12 +532,13 @@ return isAmdHsaOS() ? 8 : 4; } + /// \returns Number of bytes of arguments that are passed to a shader or + /// kernel in addition to the explicit ones declared for the function. unsigned getImplicitArgNumBytes(const MachineFunction &MF) const { if (isMesaKernel(MF)) return 16; - if (isAmdHsaOS() && isOpenCLEnv()) - return 32; - return 0; + return AMDGPU::getIntegerAttribute( + MF.getFunction(), "amdgpu-implicitarg-num-bytes", 0); } // Scratch is allocated in 256 dword per wave blocks for the entire Index: test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll +++ test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll @@ -1,12 +1,10 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 0 -; HSA-OPENCL: kernarg_segment_byte_size = 32 +; HSA: kernarg_segment_byte_size = 0 ; MESA: kernarg_segment_byte_size = 16 ; HSA: s_load_dword s0, s[4:5], 0x0 @@ -17,11 +15,24 @@ ret void } +; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 + +; HSA: kernarg_segment_byte_size = 32 +; MESA: kernarg_segment_byte_size = 16 + +; HSA: s_load_dword s0, s[4:5], 0x0 +define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + ; GCN-LABEL: {{^}}kernel_implicitarg_ptr: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 112 -; HSA-OPENCL: kernarg_segment_byte_size = 144 +; HSA: kernarg_segment_byte_size = 112 ; MESA: kernarg_segment_byte_size = 464 ; HSA: s_load_dword s0, s[4:5], 0x1c @@ -32,12 +43,38 @@ ret void } +; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 + +; HSA: kernarg_segment_byte_size = 144 +; MESA: kernarg_segment_byte_size = 464 + +; HSA: s_load_dword s0, s[4:5], 0x1c +define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + ; GCN-LABEL: {{^}}func_implicitarg_ptr: ; GCN: s_waitcnt ; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 -define void @func_implicitarg_ptr() #1 { +define void @func_implicitarg_ptr() #0 { + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load = load volatile i32, i32 addrspace(4)* %cast + ret void +} + +; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr: +; GCN: s_waitcnt +; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} +; GCN-NEXT: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define void @opencl_func_implicitarg_ptr() #0 { %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* %load = load volatile i32, i32 addrspace(4)* %cast @@ -46,8 +83,7 @@ ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-NOENV: kernarg_segment_byte_size = 0 -; HSA-OPENCL: kernarg_segment_byte_size = 32 +; HSA: kernarg_segment_byte_size = 0 ; MESA: kernarg_segment_byte_size = 16 ; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_swappc_b64 @@ -56,10 +92,20 @@ ret void } +; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: kernarg_segment_byte_size = 32 +; MESA: kernarg_segment_byte_size = 16 +; GCN: s_mov_b64 s[6:7], s[4:5] +; GCN: s_swappc_b64 +define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 { + call void @func_implicitarg_ptr() + ret void +} + ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func: ; GCN: enable_sgpr_kernarg_segment_ptr = 1 -; HSA-OPENCL: kernarg_segment_byte_size = 144 -; HSA-NOENV: kernarg_segment_byte_size = 112 +; HSA: kernarg_segment_byte_size = 112 ; MESA: kernarg_segment_byte_size = 464 ; HSA: s_add_u32 s6, s4, 0x70 @@ -72,11 +118,35 @@ ret void } +; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func: +; GCN: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: kernarg_segment_byte_size = 144 +; MESA: kernarg_segment_byte_size = 464 + +; HSA: s_add_u32 s6, s4, 0x70 +; MESA: s_add_u32 s6, s4, 0x1c0 + +; GCN: s_addc_u32 s7, s5, 0{{$}} +; GCN: s_swappc_b64 +define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 { + call void @func_implicitarg_ptr() + ret void +} + ; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func: ; GCN-NOT: s6 ; GCN-NOT: s7 ; GCN-NOT: s[6:7] -define void @func_call_implicitarg_ptr_func() #1 { +define void @func_call_implicitarg_ptr_func() #0 { + call void @func_implicitarg_ptr() + ret void +} + +; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func: +; GCN-NOT: s6 +; GCN-NOT: s7 +; GCN-NOT: s[6:7] +define void @opencl_func_call_implicitarg_ptr_func() #0 { call void @func_implicitarg_ptr() ret void } @@ -85,7 +155,21 @@ ; GCN: s_waitcnt ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0{{$}} -define void @func_kernarg_implicitarg_ptr() #1 { +define void @func_kernarg_implicitarg_ptr() #0 { + %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() + %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* + %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr + %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg + ret void +} + +; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr: +; GCN: s_waitcnt +; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} +; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0{{$}} +define void @opencl_func_kernarg_implicitarg_ptr() #0 { %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* @@ -110,5 +194,5 @@ declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2 attributes #0 = { nounwind noinline } -attributes #1 = { nounwind noinline } +attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="32" } attributes #2 = { nounwind readnone speculatable } Index: test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll +++ test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll @@ -1,9 +1,6 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s -; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s -; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; ALL-LABEL: {{^}}test: ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 @@ -32,8 +29,7 @@ } ; ALL-LABEL: {{^}}test_implicit_alignment -; HSA-NOENV: kernarg_segment_byte_size = 10 -; HSA-OPENCL: kernarg_segment_byte_size = 48 +; HSA: kernarg_segment_byte_size = 10 ; OS-MESA3D: kernarg_segment_byte_size = 28 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 @@ -49,6 +45,23 @@ ret void } +; ALL-LABEL: {{^}}opencl_test_implicit_alignment +; HSA: kernarg_segment_byte_size = 48 +; OS-MESA3D: kernarg_segment_byte_size = 28 +; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc +; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 +; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 +; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] +; MESA: buffer_store_dword [[V_VAL]] +; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] +define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 { + %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() + %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* + %val = load i32, i32 addrspace(4)* %arg.ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + ; ALL-LABEL: {{^}}test_no_kernargs: ; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: s_load_dword s{{[0-9]+}}, s[4:5] @@ -66,3 +79,4 @@ attributes #0 = { nounwind readnone } attributes #1 = { nounwind } +attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="32" } Index: unittests/ADT/TripleTest.cpp =================================================================== --- unittests/ADT/TripleTest.cpp +++ unittests/ADT/TripleTest.cpp @@ -283,12 +283,6 @@ EXPECT_EQ(Triple::AMDHSA, T.getOS()); EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); - T = Triple("amdgcn-amd-amdhsa-opencl"); - EXPECT_EQ(Triple::amdgcn, T.getArch()); - EXPECT_EQ(Triple::AMD, T.getVendor()); - EXPECT_EQ(Triple::AMDHSA, T.getOS()); - EXPECT_EQ(Triple::OpenCL, T.getEnvironment()); - T = Triple("amdgcn-amd-amdpal"); EXPECT_EQ(Triple::amdgcn, T.getArch()); EXPECT_EQ(Triple::AMD, T.getVendor());