Index: lib/Target/X86/X86InstructionSelector.cpp
===================================================================
--- lib/Target/X86/X86InstructionSelector.cpp
+++ lib/Target/X86/X86InstructionSelector.cpp
@@ -350,6 +350,8 @@
   case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC:
     return selectTruncOrPtrToInt(I, MRI, MF);
+  case TargetOpcode::G_INTTOPTR:
+    return selectCopy(I, MRI);
   case TargetOpcode::G_ZEXT:
     return selectZext(I, MRI, MF);
   case TargetOpcode::G_ANYEXT:
Index: lib/Target/X86/X86LegalizerInfo.cpp
===================================================================
--- lib/Target/X86/X86LegalizerInfo.cpp
+++ lib/Target/X86/X86LegalizerInfo.cpp
@@ -124,11 +124,13 @@
   setAction({G_GEP, p0}, Legal);
   setAction({G_GEP, 1, s32}, Legal);
 
-  if (!Subtarget.is64Bit())
+  if (!Subtarget.is64Bit()) {
     getActionDefinitionsBuilder(G_PTRTOINT)
         .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
         .maxScalar(0, s32)
         .widenScalarToNextPow2(0, /*Min*/ 8);
+    getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s32, p0});
+  }
 
   // Control-flow
   setAction({G_BRCOND, s1}, Legal);
@@ -194,6 +196,7 @@
       .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
       .maxScalar(0, s64)
       .widenScalarToNextPow2(0, /*Min*/ 8);
+  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s64, p0});
 
   // Constants
   setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
Index: test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i32* @inttoptr_p0_s32(i32 %val) {
+  entry:
+    %0 = inttoptr i32 %val to i32*
+    ret i32* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: inttoptr_p0_s32
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: $eax = COPY [[MOV32rm]]
+    ; CHECK: RET 0, implicit $eax
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(p0) = G_INTTOPTR %0(s32)
+    $eax = COPY %2(p0)
+    RET 0, implicit $eax
+
+...
Index: test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i64* @inttoptr_p0_s64(i64 %val) {
+  entry:
+    %0 = inttoptr i64 %val to i64*
+    ret i64* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: inttoptr_p0_s64
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK: $rax = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $rax
+    %0:gpr(s64) = COPY $rdi
+    %1:gpr(p0) = G_INTTOPTR %0(s64)
+    $rax = COPY %1(p0)
+    RET 0, implicit $rax
+
+...