Index: lib/Target/X86/X86InstructionSelector.cpp =================================================================== --- lib/Target/X86/X86InstructionSelector.cpp +++ lib/Target/X86/X86InstructionSelector.cpp @@ -81,8 +81,8 @@ MachineFunction &MF) const; bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; - bool selectTrunc(MachineInstr &I, MachineRegisterInfo &MRI, - MachineFunction &MF) const; + bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI, @@ -347,8 +347,9 @@ return selectConstant(I, MRI, MF); case TargetOpcode::G_FCONSTANT: return materializeFP(I, MRI, MF); + case TargetOpcode::G_PTRTOINT: case TargetOpcode::G_TRUNC: - return selectTrunc(I, MRI, MF); + return selectTruncOrPtrToInt(I, MRI, MF); case TargetOpcode::G_ZEXT: return selectZext(I, MRI, MF); case TargetOpcode::G_ANYEXT: @@ -645,7 +646,7 @@ return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } -// Helper function for selectTrunc and selectAnyext. +// Helper function for selectTruncOrPtrToInt and selectAnyext. // Returns true if DstRC lives on a floating register class and // SrcRC lives on a 128-bit vector class. static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, @@ -670,10 +671,12 @@ return true; } -bool X86InstructionSelector::selectTrunc(MachineInstr &I, - MachineRegisterInfo &MRI, - MachineFunction &MF) const { - assert((I.getOpcode() == TargetOpcode::G_TRUNC) && "unexpected instruction"); +bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + assert((I.getOpcode() == TargetOpcode::G_TRUNC || + I.getOpcode() == TargetOpcode::G_PTRTOINT) && + "unexpected instruction"); const unsigned DstReg = I.getOperand(0).getReg(); const unsigned SrcReg = I.getOperand(1).getReg(); @@ -685,7 +688,10 @@ const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); if (DstRB.getID() != SrcRB.getID()) { - DEBUG(dbgs() << "G_TRUNC input/output on different banks\n"); + if (I.getOpcode() == TargetOpcode::G_TRUNC) + DEBUG(dbgs() << "G_TRUNC input/output on different banks\n"); + else + DEBUG(dbgs() << "G_PTRTOINT input/output on different banks\n"); return false; } Index: lib/Target/X86/X86LegalizerInfo.cpp =================================================================== --- lib/Target/X86/X86LegalizerInfo.cpp +++ lib/Target/X86/X86LegalizerInfo.cpp @@ -124,6 +124,12 @@ setAction({G_GEP, p0}, Legal); setAction({G_GEP, 1, s32}, Legal); + if (!Subtarget.is64Bit()) + getActionDefinitionsBuilder(G_PTRTOINT) + .legalForCartesianProduct({s1, s8, s16, s32}, {p0}) + .maxScalar(0, s32) + .widenScalarToNextPow2(0, /*Min*/ 8); + // Control-flow setAction({G_BRCOND, s1}, Legal); @@ -161,6 +167,11 @@ if (!Subtarget.is64Bit()) return; + const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8); + const LLT s1 = LLT::scalar(1); + const LLT s8 = LLT::scalar(8); + const LLT s16 = LLT::scalar(16); + const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); const LLT s128 = LLT::scalar(128); @@ -179,6 +190,10 @@ // Pointer-handling setAction({G_GEP, 1, s64}, Legal); + getActionDefinitionsBuilder(G_PTRTOINT) + .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0}) + .maxScalar(0, s64) + .widenScalarToNextPow2(0, /*Min*/ 8); // Constants setAction({TargetOpcode::G_CONSTANT, s64}, Legal); Index: test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir @@ -0,0 +1,143 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + + define i1 @ptrtoint_s1_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i1 + ret i1 %0 + } + + define i8 @ptrtoint_s8_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i8 + ret i8 %0 + } + + define i16 @ptrtoint_s16_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i16 + ret i16 %0 + } + + define i32 @ptrtoint_s32_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i32 + ret i32 %0 + } + +... +--- +name: ptrtoint_s1_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true } +body: | + bb.1.entry: + ; CHECK-LABEL: name: ptrtoint_s1_p0 + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0) + ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit + ; CHECK: $al = COPY [[COPY]] + ; CHECK: RET 0, implicit $al + %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0 + %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2:gpr(s1) = G_PTRTOINT %0(p0) + %3:gpr(s8) = G_ANYEXT %2(s1) + $al = COPY %3(s8) + RET 0, implicit $al + +... +--- +name: ptrtoint_s8_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true } +body: | + bb.1.entry: + ; CHECK-LABEL: name: ptrtoint_s8_p0 + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0) + ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit + ; CHECK: $al = COPY [[COPY]] + ; CHECK: RET 0, implicit $al + %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0 + %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2:gpr(s8) = G_PTRTOINT %0(p0) + $al = COPY %2(s8) + RET 0, implicit $al + +... +--- +name: ptrtoint_s16_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true } +body: | + bb.1.entry: + ; CHECK-LABEL: name: ptrtoint_s16_p0 + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0) + ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[MOV32rm]].sub_16bit + ; CHECK: $ax = COPY [[COPY]] + ; CHECK: RET 0, implicit $ax + %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0 + %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2:gpr(s16) = G_PTRTOINT %0(p0) + $ax = COPY %2(s16) + RET 0, implicit $ax + +... +--- +name: ptrtoint_s32_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true } +body: | + bb.1.entry: + ; CHECK-LABEL: name: ptrtoint_s32_p0 + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0) + ; CHECK: $eax = COPY [[MOV32rm]] + ; CHECK: RET 0, implicit $eax + %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0 + %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2:gpr(s32) = G_PTRTOINT %0(p0) + $eax = COPY %2(s32) + RET 0, implicit $eax + +... Index: test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir @@ -0,0 +1,162 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + + define i1 @ptrtoint_s1_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i1 + ret i1 %0 + } + + define i8 @ptrtoint_s8_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i8 + ret i8 %0 + } + + define i16 @ptrtoint_s16_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i16 + ret i16 %0 + } + + define i32 @ptrtoint_s32_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i32 + ret i32 %0 + } + + define i64 @ptrtoint_s64_p0(i64* %p) { + entry: + %0 = ptrtoint i64* %p to i64 + ret i64 %0 + } + +... +--- +name: ptrtoint_s1_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: ptrtoint_s1_p0 + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK: $al = COPY [[COPY1]] + ; CHECK: RET 0, implicit $al + %0:gpr(p0) = COPY $rdi + %1:gpr(s1) = G_PTRTOINT %0(p0) + %2:gpr(s8) = G_ANYEXT %1(s1) + $al = COPY %2(s8) + RET 0, implicit $al + +... +--- +name: ptrtoint_s8_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: ptrtoint_s8_p0 + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK: $al = COPY [[COPY1]] + ; CHECK: RET 0, implicit $al + %0:gpr(p0) = COPY $rdi + %1:gpr(s8) = G_PTRTOINT %0(p0) + $al = COPY %1(s8) + RET 0, implicit $al + +... +--- +name: ptrtoint_s16_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: ptrtoint_s16_p0 + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK: $ax = COPY [[COPY1]] + ; CHECK: RET 0, implicit $ax + %0:gpr(p0) = COPY $rdi + %1:gpr(s16) = G_PTRTOINT %0(p0) + $ax = COPY %1(s16) + RET 0, implicit $ax + +... +--- +name: ptrtoint_s32_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: ptrtoint_s32_p0 + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit + ; CHECK: $eax = COPY [[COPY1]] + ; CHECK: RET 0, implicit $eax + %0:gpr(p0) = COPY $rdi + %1:gpr(s32) = G_PTRTOINT %0(p0) + $eax = COPY %1(s32) + RET 0, implicit $eax + +... +--- +name: ptrtoint_s64_p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: ptrtoint_s64_p0 + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: $rax = COPY [[COPY]] + ; CHECK: RET 0, implicit $rax + %0:gpr(p0) = COPY $rdi + %1:gpr(s64) = G_PTRTOINT %0(p0) + $rax = COPY %1(s64) + RET 0, implicit $rax + +...