Index: test/CodeGen/AArch64/test-update_mir_test_checks.py-itself.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/test-update_mir_test_checks.py-itself.mir
@@ -0,0 +1,128 @@
+# UNSUPPORTED: system-windows
+#
+# RUN: sed -e 's/^# RUN-NESTED:/# RUN:/' %s | sed -e 's/^# SOURCE.*$//' > %t \
+# RUN:   && %S/../../../utils/update_mir_test_checks.py --add-vreg-checks \
+# RUN:     %t 2>&1 | FileCheck %s --check-prefix=STDERR \
+# RUN:   && cat %t | FileCheck %s --check-prefix=SOURCE
+#
+# RUN-NESTED: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \
+# RUN-NESTED:     -x mir -verify-machineinstrs -simplify-mir -o - | FileCheck %s
+
+# STDERR-NOT:  WARNING
+# STDERR:      WARNING: [[TMP_FILE_NAME:/.*\.tmp]]: Skipping non-llc RUN line:
+# STDERR-SAME:     sed -e {{.*}} RUN-NESTED{{.*}}SOURCE{{.*}}STDERR{{.*}}SOURCE
+# STDERR-NOT:  WARNING
+
+# SOURCE:      WARNING
+# SOURCE-NEXT: WARNING
+# SOURCE-NEXT:     sed
+# SOURCE-NEXT: WARNING
+#
+# SOURCE-LABEL: --- |
+# SOURCE-NEXT:   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+# SOURCE-NEXT:   target triple = "aarch64-apple-ios"
+# SOURCE-NOT: SOURCE
+# SOURCE:        define void @return_only() #0 {
+# SOURCE-NEXT:   entry:
+# SOURCE-NEXT:     ret void
+# SOURCE-NEXT:   }
+# SOURCE-NOT: SOURCE
+# SOURCE:        define i32 @some_math(i32 %a, i32 %b) #0 {
+# SOURCE-NEXT:   entry:
+# SOURCE-NEXT:     %add = add i32 %b, %a
+# SOURCE-NEXT:     ret i32 %add
+# SOURCE-NEXT:   }
+# SOURCE-NOT: SOURCE
+# SOURCE:        attributes #0 = { nounwind readnone ssp }
+# SOURCE-NEXT: ...
+# SOURCE-NEXT: ---
+# SOURCE-NEXT: name:            return_only
+# SOURCE-NEXT: alignment:       2
+# SOURCE-NEXT: legalized:       true
+# SOURCE-NEXT: regBankSelected: true
+# SOURCE-NEXT: tracksRegLiveness: true
+# SOURCE-NEXT: body:             |
+# SOURCE-NEXT:   bb.1.entry:
+# SOURCE-NEXT:     ; CHECK-LABEL: name: return_only
+# SOURCE-NEXT:     ; CHECK: RET_ReallyLR
+# SOURCE-NEXT:     RET_ReallyLR
+# SOURCE-NEXT: ...
+# SOURCE-NEXT: ---
+# SOURCE-NEXT: name:            some_math
+# SOURCE-NEXT: alignment:       2
+# SOURCE-NEXT: legalized:       true
+# SOURCE-NEXT: regBankSelected: true
+# SOURCE-NEXT: tracksRegLiveness: true
+# SOURCE-NEXT: registers:
+# SOURCE-NEXT:   - { id: 0, class: gpr }
+# SOURCE-NEXT:   - { id: 1, class: gpr }
+# SOURCE-NEXT:   - { id: 2, class: gpr }
+# SOURCE-NEXT: body:             |
+# SOURCE-NEXT:   bb.1.entry:
+# SOURCE-NEXT:     liveins: $w0, $w1
+# SOURCE-NOT: SOURCE
+# SOURCE:          ; CHECK-LABEL: name: some_math
+# SOURCE-NEXT:     ; CHECK: registers:
+# SOURCE-NEXT:     ; CHECK-NEXT: id: 0, class: gpr32
+# SOURCE-NEXT:     ; CHECK-NEXT: id: 1, class: gpr32
+# SOURCE-NEXT:     ; CHECK-NEXT: id: 2, class: gpr32
+# SOURCE-NEXT:     ; CHECK: liveins: $w0, $w1
+# SOURCE-NEXT:     ; CHECK: {{\[}}[COPY:%[0-9]+]]:gpr32 = COPY $w0
+# SOURCE-NEXT:     ; CHECK: {{\[}}[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+# SOURCE-NEXT:     ; CHECK: {{\[}}[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr
+# SOURCE-SAME:     {{\[}}[COPY1]], {{\[}}[COPY]]
+# SOURCE-NEXT:     ; CHECK: $w0 = COPY {{\[}}[ADDWrr]]
+# SOURCE-NEXT:     ; CHECK: RET_ReallyLR implicit $w0
+# SOURCE-NEXT:     %0:gpr(s32) = COPY $w0
+# SOURCE-NEXT:     %1:gpr(s32) = COPY $w1
+# SOURCE-NEXT:     %2:gpr(s32) = G_ADD %1, %0
+# SOURCE-NEXT:     $w0 = COPY %2(s32)
+# SOURCE-NEXT:     RET_ReallyLR implicit $w0
+# SOURCE-NEXT: ...
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-apple-ios"
+
+  define void @return_only() #0 {
+  entry:
+    ret void
+  }
+
+  define i32 @some_math(i32 %a, i32 %b) #0 {
+  entry:
+    %add = add i32 %b, %a
+    ret i32 %add
+  }
+
+  attributes #0 = { nounwind readnone ssp }
+...
+---
+name:            return_only
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    RET_ReallyLR
+...
+---
+name:            some_math
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $w0, $w1
+
+    %0:gpr(s32) = COPY $w0
+    %1:gpr(s32) = COPY $w1
+    %2:gpr(s32) = G_ADD %1, %0
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+...
Index: utils/update_mir_test_checks.py
===================================================================
--- utils/update_mir_test_checks.py
+++ utils/update_mir_test_checks.py
@@ -51,7 +51,7 @@
     r'^---$'
     r'\n'
     r'^ *name: *(?P<func>[A-Za-z0-9_.-]+)$'
-    r'(?:.*?(?P<vregs>^ *registers: *(?:\n *- {[^\n]+$)*))?'
+    r'(?:(?:.(?!\.\.\.))*?(?P<vregs>^ *registers: *(?:\n *- {[^\n]+$)*))?'
     r'.*?'
     r'^ *body: *\|\n'
     r'(?P<body>.*?)\n'