Index: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
@@ -328,7 +328,7 @@
   bool HasLineAttributes = false;
 
   // Print the preds of this block according to the CFG.
-  if (!pred_empty()) {
+  if (!pred_empty() && IsStandalone) {
     if (Indexes) OS << '\t';
     // Don't indent(2), align with previous line attributes.
     OS << "; predecessors: ";
@@ -354,7 +354,7 @@
            << format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
            << ')';
     }
-    if (!Probs.empty()) {
+    if (!Probs.empty() && IsStandalone) {
       // Print human readable probabilities as comments.
       OS << "; ";
       for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
@@ -419,7 +419,7 @@
   if (IsInBundle)
     OS.indent(2) << "}\n";
 
-  if (IrrLoopHeaderWeight) {
+  if (IrrLoopHeaderWeight && IsStandalone) {
     if (Indexes) OS << '\t';
     OS.indent(2) << "; Irreducible loop header weight: "
                  << IrrLoopHeaderWeight.getValue() << '\n';
Index: llvm/trunk/lib/CodeGen/MachineFunction.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp
@@ -522,9 +522,8 @@
   MST.incorporateFunction(getFunction());
   for (const auto &BB : *this) {
     OS << '\n';
-    // If we print the whole function, don't print any verbose information,
-    // since that information is already present.
-    BB.print(OS, MST, Indexes, /*IsStandalone=*/false);
+    // If we print the whole function, print it at its most verbose level.
+    BB.print(OS, MST, Indexes, /*IsStandalone=*/true);
   }
 
   OS << "\n# End machine code for function " << getName() << ".\n\n";
Index: llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
+++ llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -29,7 +29,7 @@
 ; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
 ; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK:  STRXui %{{.*}}, %fixed-stack.0
-; CHECK:  STRXui [[VRB]], %fixed-stack.1
+; CHECK:  STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
Index: llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll
+++ llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll
@@ -119,7 +119,7 @@
 ; CHECK-CFG-DAG: t2B %bb.3
 
 ; CHECK-CFG-DAG: %bb.2
-; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0
+; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}{{[^,]*}}, 0
 ; CHECK-CFG-DAG: t2Bcc %bb.5
 
 ; CHECK-CFG-DAG: %bb.4
Index: llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
===================================================================
--- llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
+++ llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
@@ -3,7 +3,7 @@
 
 ; Check that the generated post-increment load has TBAA information.
 ; CHECK-LABEL: Machine code for function fred:
-; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa=
+; CHECK: = V6_vL32b_pi %{{[0-9]+}}{{[^,]*}}, 64; mem:LD64[{{.*}}](tbaa=
 
 target triple = "hexagon"
 
Index: llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -42,7 +42,7 @@
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def $cr0
+; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
 ; CHECK: BCC 76, killed [[CREG]]
   %1 = and i32 %a, 10