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[LLD] [COFF] Add support for ARM64 secrel relocations for add/load instructions

Authored by mstorsjo on Feb 14 2018, 5:34 AM.

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mstorsjo created this revision.Feb 14 2018, 5:34 AM
mstorsjo retitled this revision from [LLD] [COFF] Add support for secrel relocations for add/load instructions to [LLD] [COFF] Add support for ARM64 secrel relocations for add/load instructions.Feb 14 2018, 5:42 AM
ruiu added inline comments.Feb 15 2018, 9:06 PM
226–230 ↗(On Diff #134558)

You should factor out this part of code.

233 ↗(On Diff #134558)

Why do you need to check for Shift?

mstorsjo added inline comments.Feb 15 2018, 10:18 PM
226–230 ↗(On Diff #134558)

Ok, will do

233 ↗(On Diff #134558)

When using these relocations, you'd normally use them in a pair with SECREL_HIGH12A plus SECREL_LOW12A/L. It's very much expected and ok that the actual section relative offset is larger than 12 bits, and only the truncated lower 12 bits go with the LOW12A/L relocations. For the HIGH12A relocation, there's no corresponding larger relocation that could be used to handle the rest, so if the code uses that relocation, and there's overflow when writing the high part of it, we have an issue.

Another way of writing the same would be to always check if the section relative offset is over 24 bits, regardless of which of these relocations are used.

mstorsjo updated this revision to Diff 134558.Feb 15 2018, 10:26 PM

Factorized the initial part of calculating the section relative offset.

ruiu accepted this revision.Feb 16 2018, 10:31 AM


Hmm, factoring that common part out doesn't seem good as I anticipated. Free free to revert it and submit. I'll try to make some cleanup on that code if possible.

This revision is now accepted and ready to land.Feb 16 2018, 10:31 AM
This revision was automatically updated to reflect the committed changes.